CN111933201B

CN111933201B - Method and device for programming memory system and memory system

Info

Publication number: CN111933201B
Application number: CN202010810560.9A
Authority: CN
Inventors: 万维俊
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2020-08-13
Filing date: 2020-08-13
Publication date: 2021-03-23
Anticipated expiration: 2040-08-13
Also published as: CN111933201A; CN112967746A; CN112967746B

Abstract

Embodiments of the present description provide a programming method, device and memory system of a memory system. In the programming method, an intermediate register in a page buffer of a memory system is used to store program state information. When the memory system is programmed, for each round of programming, determining a current memory cell to be programmed and verified according to programming inhibition information stored in an intermediate register corresponding to each memory cell, and performing programming verification on the determined current memory cell to be programmed and verified by using each verification level from an initial verification level to a maximum verification level in a current programming process. In addition, after the current programming verification is finished, the programming state information stored in the corresponding intermediate register is updated according to the programming verification result of each current memory cell to be programmed and verified. With the programming method, lossless programming for the memory system can be realized without setting a special register to store the programming state information.

Description

Method and device for programming memory system and memory system

Technical Field

Embodiments of the present specification relate generally to the field of memory, and more particularly, to methods, devices, and memory systems for programming memory systems.

Background

NAND flash memory is a type of nonvolatile storage medium that has been widely used including notebooks, mobile phones, and hard disk drives. In programming NAND flash memory, to reduce system cost, the host will not save programming data after the host sends the data to the NAND flash memory. In this case, the original program data may be lost when a program error occurs.

In order to prevent the original program data from being lost when a program error occurs, a data register is provided in a page buffer of the NAND flash memory. During data programming, the data register buffers the programming data. In addition, a special register is also arranged in the page buffer, and the special register is used for storing programming state information (inhibit information) of the memory unit, and the inhibit information is used for indicating whether the programming aiming at the memory unit is successful or not. When the inhibit information indicates a programming failure, the program data is read from the data register. However, such a NAND flash memory requires a dedicated register to be provided in the page buffer, thereby increasing the cost and space size of the NAND flash memory.

Disclosure of Invention

In view of the foregoing, embodiments of the present specification provide methods, devices, and memory systems for programming memory systems. In the programming method, an intermediate register in a page buffer of a memory system is used to store program inhibit information. During cyclic programming of a page to be programmed of a memory cell array, for each round of programming, determining a current memory cell to be programmed and verified according to program inhibition information stored in an intermediate register corresponding to each memory cell of the page to be programmed, and performing program verification on the determined current memory cell to be programmed and verified by using each verification level from a starting verification level of a current programming process to a maximum verification level, wherein the starting verification level of the current programming process is determined according to a verification failure statistical result of program verification for the starting verification level of a previous programming process in the previous programming process. In addition, in the programming method, after the current program verification is finished, the program inhibition information stored in the corresponding intermediate register is updated according to the program verification result of each current memory cell to be program-verified. With the programming method, lossless programming for the memory system can be realized without setting a special register to store the programming state information.

According to an aspect of embodiments of the present specification, there is provided a method for programming a memory system, the memory system including a page buffer including an intermediate register for buffering intermediate processing results during programming and storing program inhibit information after each round of programming is ended, the program inhibit information indicating whether programming for a memory cell is successful, the method including: the following programming process is performed in a loop until the starting verify level of the current programming process is greater than the maximum verify level: determining a current memory unit to be programmed according to programming inhibition information stored in an intermediate register corresponding to each memory unit in a memory page to be programmed of a memory unit array; using the current programming voltage to perform current programming on the determined current memory cell to be programmed; determining a current to-be-programmed verification storage unit according to programming inhibition information stored in an intermediate register corresponding to each storage unit of the to-be-programmed page; performing program verification on the determined current memory cell to be program-verified using each of the verify levels from the start verify level to the maximum verify level of the current programming process; counting a verification failure statistic result of the program verification for the initial verification level; determining an initial verification level of a next programming process according to the verification failure statistical result; and updating the program inhibition information stored in the corresponding intermediate register according to the program verification result of each current memory cell to be programmed and verified.

Optionally, in one example of the above aspect, determining the initial verify level for the next programming process according to the verify failure statistics comprises: determining a start verify level of the current programming process as a start verify level of a next programming process when the verification failure statistics indicate that there are memory cells for program verification of the start verify level that have failed programming; determining a next verify level of a start verify level of the current programming process as a start verify level of a next programming process when the verify failure statistics indicate that there are no memory cells for which programming fails to verify for the start verify level.

Optionally, in an example of the foregoing aspect, the determining a current memory cell to be programmed according to program inhibit information stored in an intermediate register corresponding to each memory cell in the memory page to be programmed of the memory cell array includes: determining the bit line voltage of each memory cell according to the program inhibition information stored in the intermediate register corresponding to each memory cell in the to-be-programmed memory page of the memory cell array, wherein the current programming voltage for performing the current programming on the determined current to-be-programmed memory cell comprises the following steps: the current programming is performed by applying a current programming voltage to the word lines of the individual memory cells of the memory page and applying the determined bit line voltage to the bit lines of the individual memory cells of the memory page.

Optionally, in an example of the foregoing aspect, the page buffer includes an offset information register, and determining the bit line voltage of each memory cell according to program inhibit information stored in an intermediate register corresponding to each memory cell in a memory page to be programmed of the memory cell array includes: determining the bit line voltage of each memory cell in a to-be-programmed memory page of a memory cell array according to program inhibit information stored in an intermediate register corresponding to the memory cell and bias information in a corresponding bias information register, the method further comprising: performing bias verification on the current to-be-programmed verified memory cells using each of verify levels from a start verify level to a maximum verify level of the current programming process; and updating the bias information stored in the bias information register corresponding to the memory unit according to the bias verification result of each memory unit in the current memory unit to be programmed and verified.

Optionally, in an example of the foregoing aspect, determining, according to program inhibit information stored in an intermediate register corresponding to each memory cell in a memory page to be programmed of the memory cell array and bias information in a corresponding bias information register, a bit line voltage of the memory cell includes: determining a first bit line voltage of each memory cell according to programming inhibition information stored in an intermediate register corresponding to each memory cell in a memory page to be programmed of a memory cell array, wherein the first bit line voltage comprises one of a low level and a high level; writing the offset information in the offset information register of each storage unit into a corresponding intermediate register; the first bit line voltage of each memory cell is adjusted to a second bit line voltage including one of a low level, a middle level, and a high level according to the bias information in each intermediate register.

Optionally, in one example of the above aspect, the method further comprises: and restoring the programming inhibition information stored in the intermediate register of each page buffer according to the current starting verification level and the data bit of the data register in each page buffer.

Optionally, in one example of the above aspect, the memory system comprises a TLC NAND flash memory and the data registers comprise a low bit data register, an intermediate bit data register, and a high bit data register.

Optionally, in one example of the above aspect, the current programming voltage is generated in incremental step programming pulses.

According to another aspect of embodiments of the present specification, there is provided a memory controller for programming a memory system, the memory system including a page buffer including an intermediate register for buffering intermediate processing results during programming and storing program inhibit information after each round of programming is ended, the program inhibit information indicating whether programming for a memory cell is successful, the memory controller being configured to: the following programming process is performed in a loop until the starting verify level of the current programming process is greater than the maximum verify level: determining a current memory unit to be programmed according to programming inhibition information stored in an intermediate register corresponding to each memory unit in a memory page to be programmed of a memory unit array; using the current programming voltage to perform current programming on the determined current memory cell to be programmed; determining a current to-be-programmed verification storage unit according to programming inhibition information stored in an intermediate register corresponding to each storage unit of the to-be-programmed page; performing program verification on the determined current memory cell to be program-verified using each of the verify levels from the start verify level to the maximum verify level of the current programming process; counting a verification failure statistic result of the program verification for the initial verification level; determining an initial verification level of a next programming process according to the verification failure statistical result; and updating the program inhibition information stored in the corresponding intermediate register according to the program verification result of each current memory cell to be programmed and verified.

Optionally, in one example of the above aspect, the memory controller is configured to: determining a start verify level of the current programming process as a start verify level of a next programming process when the verification failure statistics indicate that there are memory cells for program verification of the start verify level that have failed programming; determining a next verify level of a start verify level of the current programming process as a start verify level of a next programming process when the verify failure statistics indicate that there are no memory cells for which programming fails to verify for the start verify level.

Optionally, in one example of the above aspect, the plurality of memory cells of each memory page are coupled to a same wordline and the respective memory cells of each memory page are coupled to different bitlines, the memory controller is configured to: determining the bit line voltage of each memory cell according to the program inhibition information stored in the intermediate register corresponding to each memory cell in a memory page to be programmed of a memory cell array, applying the current program voltage to the word line of each memory cell of the memory page and applying the determined bit line voltage to the bit line of each memory cell of the memory page to perform current programming.

Optionally, in one example of the above aspect, the page buffer includes a bias information register, and the memory controller is configured to: determining a bit line voltage of each memory cell in a memory page to be programmed of a memory cell array according to program inhibit information stored in an intermediate register corresponding to the memory cell and bias information in a corresponding bias information register, the memory controller being further configured to: performing bias verification on the current to-be-programmed verified memory cells using each of verify levels from a start verify level to a maximum verify level of the current programming process; and updating the bias information stored in the bias information register corresponding to the memory unit according to the bias verification result of each memory unit in the current memory unit to be programmed and verified.

Optionally, in one example of the above aspect, the memory controller is configured to: determining a first bit line voltage of each memory cell according to programming inhibition information stored in an intermediate register corresponding to each memory cell in a memory page to be programmed of a memory cell array, wherein the first bit line voltage comprises one of a low level and a high level; writing the offset information in the offset information register of each storage unit into a corresponding intermediate register; the first bit line voltage of each memory cell is adjusted to a second bit line voltage including one of a low level, a middle level, and a high level according to the bias information in each intermediate register.

Optionally, in one example of the above aspect, the memory controller is further configured to: and restoring the programming inhibition information stored in the intermediate register of each page buffer according to the initial verification level and the data bit of the data register in each page buffer.

According to another aspect of embodiments of the present specification, there is provided a memory system including: an array of memory cells coupled to at least one word line and at least one bit line, the array of memory cells organized into memory pages, each memory page including a plurality of memory cells, the plurality of memory cells being multi-level cells, a voltage generation circuit coupled to at least one word line for generating programming voltages and respective verify levels for the memory cells of the array of memory cells; a page buffer coupled to at least one bit line, the page buffer including an intermediate register to buffer intermediate processing results during programming and to store program inhibit information after each round of programming, the program inhibit information indicating whether programming for memory cells, one page buffer per memory cell, is successful; and a memory controller configured to: the following programming process is performed in a loop until the starting verify level of the current programming process is greater than the maximum verify level: determining a current memory unit to be programmed according to programming inhibition information stored in an intermediate register corresponding to each memory unit in a memory page to be programmed of a memory unit array; using the current programming voltage to perform current programming on the determined current memory cell to be programmed; determining a current to-be-programmed verification storage unit according to programming inhibition information stored in an intermediate register corresponding to each storage unit of the to-be-programmed page; performing program verification on the determined current memory cell to be program-verified using each of the verify levels from the start verify level to the maximum verify level of the current programming process; counting a verification failure statistic result of the program verification for the initial verification level; determining an initial verification level of a next programming process according to the verification failure statistical result; and updating the program inhibition information stored in the corresponding intermediate register according to the program verification result of each current memory cell to be programmed and verified.

According to another aspect of embodiments of the present specification, there is provided a computing device including: at least one processor, and a memory coupled with the at least one processor, the memory storing instructions that, when executed by the at least one processor, cause the at least one processor to perform a programming method as described above.

According to another aspect of embodiments herein, there is provided a machine-readable storage medium storing executable instructions that, when executed, cause the machine to perform a programming method as described above.

Drawings

A further understanding of the nature and advantages of the present disclosure may be realized by reference to the following drawings. In the drawings, similar components or features may have the same reference numerals.

FIG. 1 illustrates an example architectural diagram of a memory system with lossless mode programming capability.

FIG. 2 illustrates an example schematic diagram of storage information for various registers in a page buffer of the memory system shown in FIG. 1.

FIG. 3 illustrates an example flow chart of a memory cell programming process for the memory system shown in FIG. 1.

Fig. 4 is a schematic diagram illustrating a change in storage information of an intermediate register during the programming of the memory cell shown in fig. 3.

FIG. 5 illustrates an example architectural diagram of a memory system according to embodiments of the present description.

FIG. 6 illustrates an example flow diagram of a method for programming a memory system in accordance with embodiments of the present description.

FIG. 7 illustrates an example architectural diagram of a memory system according to embodiments of the present description.

FIG. 8 illustrates another example flow diagram of a method for programming a memory system in accordance with embodiments of the present description.

Fig. 9 is a schematic diagram illustrating a change in storage information of an intermediate register during the programming of the memory cell shown in fig. 8.

FIG. 10 illustrates a schematic diagram of a computing device for operation of a memory controller, according to embodiments of the present description.

Detailed Description

The subject matter described herein will now be discussed with reference to example embodiments. It should be understood that these embodiments are discussed only to enable those skilled in the art to better understand and thereby implement the subject matter described herein, and are not intended to limit the scope, applicability, or examples set forth in the claims. Changes may be made in the function and arrangement of elements discussed without departing from the scope of the disclosure. Various examples may omit, substitute, or add various procedures or components as needed. For example, the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. In addition, features described with respect to some examples may also be combined in other examples.

As used herein, the term "include" and its variants mean open-ended terms in the sense of "including, but not limited to. The term "based on" means "based at least in part on". The terms "one embodiment" and "an embodiment" mean "at least one embodiment". The term "another embodiment" means "at least one other embodiment". The terms "first," "second," and the like may refer to different or the same object. Other definitions, whether explicit or implicit, may be included below. The definition of a term is consistent throughout the specification unless the context clearly dictates otherwise.

In this specification, the term "lossless mode programming" may refer to a programming mode that does not cause loss of original program data in the event of a program error.

FIG. 1 illustrates an example architecture diagram of a memory system 1 with lossless mode programming capability.

As shown in fig. 1, the memory system 1 includes a voltage generation circuit 10, a memory controller 12, a page buffer 14, and a memory cell array 16. In some embodiments of the present description, the memory system 1 may be a flash memory, for example, a NAND flash memory.

The memory cell array 16 includes a plurality of memory cells, and the plurality of memory cells in the memory cell array 16 are organized into a plurality of memory pages, each memory page includes a plurality of memory cells, and the plurality of memory cells of each memory page are coupled to the same wordline. In addition, each of the plurality of memory cells of each memory page is coupled to a different bit line.

The voltage generation circuit 10 is coupled with the memory cell array 16 via word lines. The voltage generation circuit 10 is configured to generate a program voltage required for page programming, and apply the generated program voltage to the memory cells of the corresponding page via the word line for programming, thereby implementing programming for the memory cells on the page. Further, the voltage generation circuit 10 is also configured to generate respective verification voltages required for program verification.

In one example of the present specification, the memory Cell may be a multi-level Cell (MLC), for example, a three-level Cell (TLC), a four-level Cell (QLC), or the like. The memory cells may store data in multiple states. For example, in the case of a TLC storage unit, the storage unit may store data in eight states. In the case of a QLC memory cell, the memory cell can store sixteen states of data.

For example, the memory cell may include a floating gate transistor FT. During a program operation of the memory cell, a gate terminal of the floating gate transistor FT of the memory cell may receive a program voltage from a word line, and a first terminal of the floating gate transistor FT may receive a bias voltage. In some embodiments, the programming voltage may be larger than the bias voltage and such that a high voltage is present between the gate terminal and the first terminal of the floating gate transistor FT, whereby electrons will be injected into the floating gate structure of the floating gate transistor FT, thereby enabling data programming and the threshold voltage of the floating gate transistor FT to be raised.

By injecting sufficient electrons into the gate structure of the floating gate transistor FT, the threshold voltage of the floating gate transistor FT is increased to a desired level. Accordingly, the state of data stored in the memory cell can be recognized according to the level of the threshold voltage of the floating gate transistor FT of the memory cell.

For example, in the case where the memory cell is a TLC type memory cell, the memory cell may store eight different data states, and accordingly, there are seven verification voltages, i.e., first to seventh verification voltages, where the first verification voltage is the smallest and the seventh verification voltage is the largest. If the threshold voltage of the memory cell is less than the first verify voltage, the memory cell is considered to be unprogrammed and the memory cell is determined to have the first program state. If the threshold voltage of the memory cell is greater than the first verify voltage but less than the second verify voltage, the memory cell is determined to have the second program state. If the threshold voltage of the memory cell is greater than the second verify voltage but less than the third verify voltage, the memory cell is determined to have a third programmed state, and so on. In some other embodiments, the memory cells may store more or fewer data states.

One page buffer 14 for each memory location. As shown in fig. 1, the page buffer 14 includes an intermediate register 141, a bias information register 143, a program status register 145, and a data register 147. FIG. 2 illustrates an example schematic diagram of storage information for various registers in a page buffer of the memory system shown in FIG. 1.

As shown in fig. 2, the intermediate register 141 is used to buffer the intermediate processing result when data reading and programming are performed. In other words, the intermediate register 141 is used for the intermediate dump process. The offset information register 143 is used to buffer offset information.

The program status register 145 is used to buffer program inhibit information (inhibit information). The inhibit information is used to indicate whether programming for the memory cell was successful. When the value of the inhibit information is 1, it indicates that the programming is successful for the corresponding memory cell, and when the value of the inhibit information is 0, it indicates that the programming is unsuccessful for the corresponding memory cell. In programming a memory cell, the bias information stored in the bias register 143 and the program inhibit information stored in the program status register 145 are used to determine the bit line voltage required for the memory cell. Specifically, in one example, memory controller 12 determines a first bit line voltage for each memory cell in a memory page to be programmed of the memory cell array based on program inhibit information stored in an intermediate register corresponding to each memory cell, the first bit line voltage including one of a low level and a high level. Subsequently, the memory controller 12 writes the offset information in the offset information register of each memory cell to the corresponding intermediate register; then, the bias information in each intermediate register is read, and the first bit line voltage of each memory cell is adjusted to a second bit line voltage including one of a low level, an intermediate level and a high level according to the read bias information, wherein the intermediate level is greater than the low level but less than the high level.

The data register 147 is used to buffer data to be programmed into a page of the memory cell array. When the storage unit is a TLC type storage unit, the data register 147 may include three data registers: LP (lower Page) register, MP (middle Page) register, and UP (upper Page) register. The LP register is used for caching low-bit data in the three-bit data, the MP register is used for caching middle-bit data in the three-bit data, and the UP register is used for caching high-bit data in the three-bit data.

The memory controller 12 is coupled to the voltage generation circuit 10, the page buffer 14, and the memory cell array 16 for controlling a program operation for memory cells of the memory cell array 16. FIG. 3 illustrates an example flow chart of a memory cell programming process for the memory system shown in FIG. 1.

As shown in fig. 3, in performing programming, at 301, data required for a programming operation for the memory system is prepared. Then, the operations 302-307 are performed in a loop until the starting verify level is greater than the maximum verify level.

At 302, under the control of the memory controller 12, a program voltage is applied to the memory cells of the memory page to be programmed. Specifically, memory controller 12 determines the memory cells that need to be programmed based on the program inhibit information in program status register 145 and the bias information in bias information register 143. Subsequently, a program voltage is applied to the selected memory cell to be programmed to perform programming. For example, the memory controller 12 may control the voltage generation circuit 10 to generate a programming voltage required for page programming and apply the programming voltage to each memory cell of a memory page to be programmed via a word line. In addition, memory controller 12 buffers the program inhibit information in program status register 145 to intermediate register 141, reads the program inhibit information in intermediate register 141, and determines the first bit line voltage on each memory cell based on the read program inhibit information. The first bit line voltage includes one of a low level and a high level. For example, for a memory cell whose value of program inhibit information is "1", its bit line voltage is determined to be high, that is, the memory cell is not programmed. For a memory cell whose value of program inhibit information is "0", its bit line voltage is determined to be low level. In addition, the memory controller 12 buffers the offset information in the offset information register of each memory cell into a corresponding intermediate register, reads the offset information in each intermediate register, and adjusts the first bit line voltage of each memory cell to a second bit line voltage including one of a low level, an intermediate level, and a high level according to the read offset information. According to the bit line voltage supply manner, a memory cell of which the supplied bit line voltage is at a low level or an intermediate level can be programmed, and data buffered in the corresponding data register is programmed into the memory cell.

In performing program verification, at 303, for each verify level, memory controller 12 determines the memory cells to be program verified corresponding to that verify level based on the program inhibit information in program status register 145 and the data bits in data register 147. At 304, for each verify level, program verify is performed on the determined memory cells to be program verified, while program verify operations are not performed on the remaining memory cells on the memory page. In addition, the program verify results for each verify level are updated into the program status register 145.

Specifically, for each verify level, memory controller 12 writes the data bits in data register 147 to intermediate register 141. Then, the memory controller 12 writes the program inhibit information in the program status register 145 into the intermediate register 141, and then the memory controller 12 controls the intermediate register 141 to perform calculation on the data bits and the program inhibit information and determines the bit line voltage of each memory cell according to the calculation result. Then, the memory controller 12 supplies the determined bit line voltage to the bit line of each memory cell to perform program verification, thereby determining a memory cell to be program-verified corresponding to the verify level.

At 305, for each verify level, bias verification is performed on the determined memory cells to be programmed corresponding to the verify level, and the bias information in the corresponding bias information register is updated according to the bias verification result of each memory cell.

Next, at 306, it is determined whether a loop over condition is satisfied, i.e., the starting verify level is greater than the maximum verify level. If the loop-ending condition is satisfied, the programming process ends. If not, at 307, the program voltage is increased and the next loop process is performed back to 302.

Fig. 4 is a schematic diagram illustrating a change in storage information of an intermediate register during the programming of the memory cell shown in fig. 3. As shown in fig. 4, in the programming process, first, the memory controller 12 buffers the program inhibit information in the program status register 145 to the intermediate register 141 and supplies the first bit line voltage to the bit line of each memory cell according to the program inhibit information. Next, the memory controller 12 buffers the bias information in the bias status register 143 to the intermediate register 141, thereby adjusting the first bit line voltage to the second bit line voltage according to the bias information. Subsequently, in the program verification process, the memory controller 12 buffers the program inhibit information in the program status register 145 and the data bits in the data register 147 into the intermediate register 141, and controls the intermediate register 141 to perform calculation on the program inhibit information and the data bits, thereby buffering the calculation result in the intermediate register 141.

In the above memory system, an additional program status register needs to be added in the memory system, thereby increasing the CMOS cost of peripheral circuits of the memory system. In addition, the added program status register also increases the occupation space of the peripheral circuits of the memory system, thereby being disadvantageous to the miniaturization of the memory system.

To address the above-mentioned problems, this patent proposes a scheme for programming a memory system. With this programming scheme, lossless programming for a memory system can be achieved without requiring the memory system to add a program status register.

FIG. 5 illustrates an example architectural diagram of a memory system 500 according to embodiments of the present description.

As shown in fig. 5, the memory system 500 includes a voltage generation circuit 510, a memory controller 520, a page buffer 530, and a memory cell array 540.

The voltage generation circuit 510 is coupled to the memory controller 520. The voltage generation circuit 510 is configured to generate a program voltage required for page programming under the control of the memory control 520. In addition, the voltage generation circuit 510 is coupled to the memory cell array 540 via at least one word line, and applies the generated programming voltage to the memory cells of the corresponding page via the word line for programming, thereby implementing programming for the memory cells on the page.

One page buffer 530 per memory cell. The page buffer 530 includes an intermediate register 531 and a data register 533. The intermediate register 531 is used to buffer the intermediate processing result during programming and store program inhibit information (inhibit information) after each round of programming is finished, the program inhibit information being used to indicate whether programming for the memory cell is successful or not.

The data register 533 is used to buffer data to be programmed into a page of the memory cell array 540. When the memory cell array is a TLC type memory cell array, the data register 533 may include three data registers: LP (lower Page) register, MP (middle Page) register, and UP (upper Page) register. The LP register is used for caching low-bit data in the three-bit data, the MP register is used for caching middle-bit data in the three-bit data, and the UP register is used for caching high-bit data in the three-bit data.

The memory controller 520 is coupled with the voltage generation circuit 510, the page buffer 530, and the memory cell array 540, and is configured to program and program verify memory cells on a page of the memory cell array 540. The operation of the memory controller 520 will be described in detail below with reference to fig. 6.

FIG. 6 illustrates an example flow diagram of a method for programming a memory system in accordance with embodiments of the present description. The method is performed by the memory controller 520.

As shown in fig. 6, at 601, data required for a program operation of a memory system is prepared. Then, the operations 602-612 are performed in a loop until the starting verify level is greater than the maximum verify level.

At step 602, the current programming voltage generated via the voltage generation circuit 510 is applied to each memory cell of the page to be programmed of the memory cell array for current programming under the control of the memory controller 520. Specifically, the current memory cell to be programmed is determined according to the program inhibition information stored in the intermediate register corresponding to each memory cell in the memory page to be programmed of the memory cell array. Then, the determined memory cell to be currently programmed is currently programmed using the current program voltage generated via the voltage generation circuit 510. For example, the memory controller 520 applies the current program voltage generated via the voltage generation circuit 510 to the word lines of the respective memory cells of the page to be programmed of the memory cell array to perform the current programming. At the first cycle, the current programming voltage applied is the initial programming voltage. At a subsequent cycle, the current program voltage applied is determined based on the program voltage of the previous cycle. For example, voltage generation circuit 510 may be controlled to generate the current programming voltage in incremental step programming pulses.

In one example, the plurality of memory cells of each memory page are coupled to the same wordline, and the individual memory cells of each memory page are coupled to different bitlines. Determining the current memory cell to be programmed according to the program inhibiting information stored in the intermediate register corresponding to each memory cell in the memory page to be programmed of the memory cell array may include: and determining the bit line voltage of each memory cell according to the programming inhibition information stored in the intermediate register corresponding to each memory cell in the memory page to be programmed of the memory cell array. For example, for a memory cell whose program inhibit information is "1", its bit line voltage is determined to be high level. For a memory cell whose program inhibit information is "0", its bit line voltage is determined to be a low level. Accordingly, the current programming of the determined current memory cell to be programmed using the current programming voltage generated via the voltage generation circuit includes: the current programming is performed by applying the current programming voltage generated via the voltage generation circuit to the word lines of the respective memory cells of the memory page and applying the determined bit line voltage to the bit lines of the respective memory cells of the memory page.

In addition, in the case that the page buffer includes an offset register, the memory controller 320 further determines the bit line voltage of each memory cell of the page to be programmed according to the offset information in the offset information register corresponding to the memory cell and the data bit stored in the data register. Accordingly, memory controller 320 applies the determined bit line voltage for each memory cell to the bit line for that memory cell for the current programming.

At 603, the memory controller 520 determines the current to-be-programmed verification memory cell according to the program inhibit information stored in the intermediate register corresponding to each memory cell of the to-be-programmed page. Specifically, the memory controller 520 may read program inhibit information stored in an intermediate register corresponding to each memory cell of the page to be programmed, and determine a current memory cell to be program-verified according to the read program inhibit information. For example, when the read program inhibit information is "1", it indicates that the corresponding memory cell has been successfully programmed, thereby excluding the memory cell from the memory cells currently to be program-verified. In other words, the memory controller 320 determines only the memory cell of which the current program inhibit information is "0" as the memory cell to be program-verified currently.

Next, at 604, program verification is performed on the determined memory cells currently to be program-verified using the initial verification level of the current programming process, and program inhibit information stored in the corresponding intermediate register is updated based on the program verification result for each memory cell.

At 605, memory controller 520 counts the verify failure statistics for program verify for the starting verify level. Here, the verification failure statistics VFC may be an indication value for indicating that there is a memory cell of which verification has failed, for example, a VFC of "1" indicates that there is a memory cell of which verification has failed, and a VFC of "0" indicates that there is no memory cell of which verification has failed. Accordingly, in program verification for all memory cells to be programmed to the program state corresponding to the initial verify level, VFC is assigned to "1" if there are memory cells that fail program verification. Alternatively, the verification failure statistics VFC may be a count of the memory cells in which verification fails. Accordingly, if there are N memory cells that fail program verification, VFC is assigned to "N". In one example, after counting the VFC value, memory controller 520 may write the counted VFC value to an offset information register for subsequent use by memory controller 520.

Then, the memory controller 520 determines the initial verify level of the next programming process according to the verify failure statistics. For example, in one example, at 606, it is determined whether the verification failure statistics indicate that all memory cells programmed through (i.e., VFC pass. When the verification failure statistics indicate that there are memory cells for program verification of the starting verification level that have failed programming, memory control 520 determines the starting verification level of the current programming process (e.g., LV2) as the starting verification level of the next programming process and proceeds to 608. When the verification failure statistics indicate that there are no memory cells that failed programming for the program verification of the starting verification level (e.g., LV2), at 607, the next verification level (LV3) of the starting verification level (e.g., LV2) of the current program process is determined as the starting verification level of the next program process and proceeds to 608.

Subsequently, at 608, for each of the verify levels from the next verify voltage to the maximum verify level of the initial verify level, program verify for the verify level is performed on the determined current memory cells to be program-verified, and program inhibit information in the corresponding intermediate register is updated according to the program verify result of each current memory cell to be program-verified.

At 609, it is determined whether the starting verify level is greater than the maximum verify level. For example, in the case of a TLC memory cell, it is determined whether the initial verify level is equal to LV 8. If equal to LV8, the programming process ends.

If not, then at 610, memory controller 520 controls voltage generation circuit 510 to increase the programming voltage for the next programming pass. For example, in one example, the program voltage may be increased in incremental step programming pulse fashion, i.e., one step voltage at a time.

FIG. 7 illustrates an example architectural diagram of a memory system 700 according to embodiments of the present description. As shown in fig. 7, the memory system 700 includes a voltage generation circuit 710, a memory controller 720, a page buffer 730, and a memory cell array 740. The memory system 700 shown in fig. 7 is a modification of the memory system 500 shown in fig. 5. Compared to the memory system 500, only the offset information register 733 is added to the page buffer 730, and the structures and functions of the other components are identical. For simplicity of description, only the differences will be described in detail below.

The offset information register 733 is used to buffer offset information after each round of programming is completed. The bias information is used along with program inhibit information to determine the bit line voltage required for the memory cell when programming the memory cell.

In addition, the offset information register 733 may also be used to buffer Verify Failure statistics (VFC) for program Verify against a start Verify level during program Verify. The verify failure statistics are used by the memory controller 520 to determine the initial verify level for the next programming process.

As shown in fig. 8, at 801, data required for a program operation for a memory system is prepared. Then, the operations 802 through 813 are performed in a loop until the starting verify level is greater than the maximum verify level.

In step 802, a current program voltage generated via the voltage generation circuit 710 is applied to each memory cell of a page to be programmed of the memory cell array for current programming under the control of the memory controller 720. Specifically, the current memory cell to be programmed is determined according to the program inhibition information stored in the intermediate register corresponding to each memory cell in the memory page to be programmed of the memory cell array. Then, the determined memory cell to be currently programmed is currently programmed using the current program voltage generated via the voltage generation circuit 710. For example, the memory controller 720 applies the current program voltage generated via the voltage generation circuit 710 to the word lines of the respective memory cells of the page to be programmed of the memory cell array to perform the current programming. At the first cycle, the current programming voltage applied is the initial programming voltage. At a subsequent cycle, the current program voltage applied is determined based on the program voltage of the previous cycle. For example, the voltage generation circuit 710 may be controlled to generate the current programming voltage in incremental step programming pulses.

In one example, the plurality of memory cells of each memory page are coupled to the same wordline, and the individual memory cells of each memory page are coupled to different bitlines. When determining the current memory cell to be programmed, the memory controller 720 determines the bit line voltage of each memory cell according to the program inhibit information stored in the intermediate register corresponding to each memory cell in the memory page to be programmed of the memory cell array and the bias information in the corresponding bias information register. For example, in one example, memory controller 720 determines a first bit line voltage for each memory cell in a memory page to be programmed of the memory cell array based on program inhibit information stored in an intermediate register corresponding to each memory cell, the first bit line voltage including one of a low level and a high level. For example, for a memory cell whose program inhibit information is "1", its bit line voltage is determined to be high level. For a memory cell whose program inhibit information is "0", its bit line voltage is determined to be a low level. Next, the memory controller 720 buffers the offset information in the offset information register of each memory cell to the corresponding intermediate register; and adjusting the first bit line voltage of each memory cell to a second bit line voltage including one of a low level, a middle level, and a high level according to the bias information in each intermediate register. For example, the low level on the corresponding portion of the memory cells may be adjusted to the intermediate level based on the bias information. Subsequently, the memory controller 720 applies the current program voltage generated via the voltage generation circuit to the word lines of the respective memory cells of the memory page and applies the determined bit line voltage to the bit lines of the respective memory cells of the memory page for the current programming.

At 803, memory controller 720 restores the program inhibit information in the intermediate register based on the start verify level of the current programming process and the data bits of the data register. For example, assuming that the start verify level is LV2, program inhibit information of memory cells in which data bits stored in the data register correspond to LV2 to LV7 is determined to be "0", and program inhibit information of memory cells in which data bits stored in the data register correspond to LV1 is determined to be "1".

At 804, the memory controller 720 determines the current to-be-programmed memory cells according to the program inhibit information stored in the intermediate register corresponding to each memory cell of the to-be-programmed page. Specifically, the memory controller 520 may read program inhibit information stored in an intermediate register corresponding to each memory cell of the page to be programmed, and determine a current memory cell to be program-verified according to the read program inhibit information. For example, when the read program inhibit information is "1", it indicates that the corresponding memory cell has been successfully programmed, thereby excluding the memory cell from the memory cells currently to be program-verified. In other words, the memory controller 320 determines only the memory cell of which the current program inhibit information is "0" as the memory cell to be program-verified currently.

Next, at 805, using the initial verify level of the current programming process, program verification is performed on the determined memory cells currently to be program-verified, and the program inhibit information stored in the corresponding intermediate register is updated according to the program verify result of each memory cell.

At 806, memory controller 720 counts the verify failure statistics for the program verify for the initial verify level. Here, the verification failure statistics VFC may be an indication value for indicating that there is a memory cell of which verification has failed, for example, a VFC of "1" indicates that there is a memory cell of which verification has failed, and a VFC of "0" indicates that there is no memory cell of which verification has failed. Accordingly, in program verification for all memory cells to be programmed to the program state corresponding to the initial verify level, VFC is assigned to "1" if there are memory cells that fail program verification. Alternatively, the verification failure statistics VFC may be a count of the memory cells in which verification fails. Accordingly, if there are N memory cells that fail program verification, VFC is assigned to "N". In one example, after counting the VFC value, memory controller 720 may write the counted VFC value to an offset information register for subsequent use by memory controller 720.

Then, the memory controller 720 determines the initial verify level of the next programming process according to the verify failure statistics. For example, in one example, at 807, it is determined whether the verify failure statistics indicate that all memory cells programmed through (i.e., VFC pass. When the verification failure statistics indicate that there are memory cells for program verification of the starting verify level that have failed programming, memory control 720 determines the starting verify level of the current programming process (e.g., LV2) as the starting verify level of the next programming process and proceeds to 809. When the verification failure statistics indicate that there are no memory cells that failed programming for the program verification of the starting verification level (e.g., LV2), at 808, the next verification level (LV3) of the starting verification level (e.g., LV2) of the current programming process is determined to be the starting verification level of the next programming process and proceeds to 809.

At 809, the memory controller 720 performs bias verification for the determined current memory cells to be program-verified with respect to the initial verification level, and updates the bias information in the bias information register corresponding to each memory cell according to the bias verification result of each current memory cell to be program-verified.

Subsequently, program verify and bias verify for the determined current memory cell to be program-verified are performed for each of the verify levels from the next verify voltage to the maximum verify level of the starting verify level. Specifically, at 810, program verification is performed on the determined current memory cells to be program-verified using the verify level, and program inhibit information in the corresponding intermediate register is updated according to the program-verify result of each current memory cell to be program-verified. At 811, bias verification is performed on the determined current memory cells to be program verified using the verify levels, and the bias information in the corresponding bias information register is updated according to the bias verification result of each current memory cell to be program verified.

At 812, it is determined whether the starting verify level is greater than the maximum verify level. For example, in the case of a TLC memory cell, it is determined whether the initial verify level is equal to LV 8. If equal to LV8, the programming process ends.

If not, then at 813 memory controller 720 controls voltage generation circuit 710 to increase the programming voltage for the next programming pass. For example, in one example, the program voltage may be increased in incremental step programming pulse fashion, i.e., one step voltage at a time.

Fig. 9 is a schematic diagram illustrating a change in storage information of an intermediate register during the programming of the memory cell shown in fig. 8. As shown in fig. 9, at the time of program start, the intermediate register buffers program inhibit information and provides a first bit line voltage to a bit line of each memory cell according to the program inhibit information. The memory controller then buffers the bias information in the bias status register to an intermediate register, thereby adjusting the first bit line voltage to the second bit line voltage based on the bias information. Subsequently, during the program verification process, the memory controller buffers the data bits in the data register into the intermediate register, and restores the program inhibit information in the intermediate register according to the data bits in the intermediate register and the start verification level, and buffers the restored program inhibit information into the intermediate register. In addition, after the program verification is finished, the program inhibition information in the intermediate register is updated according to the program verification result.

A memory system programming method and a memory controller according to embodiments of the present specification are described above with reference to fig. 1 to 9. The above memory controller may be implemented in hardware, or may be implemented in software, or a combination of hardware and software.

FIG. 10 illustrates a schematic diagram of a computing device for operation of a memory controller, according to embodiments of the present description. As shown in fig. 10, the computing device 1000 may include at least one processor 1010, storage (e.g., non-volatile storage) 1020, memory 1030, and a communication interface 1040, and the at least one processor 1010, storage 1020, memory 1030, and communication interface 1040 are connected together via a bus 1060. The at least one processor 1010 executes at least one computer-readable instruction (i.e., an element described above as being implemented in software) stored or encoded in memory.

In one embodiment, computer-executable instructions are stored in the memory that, when executed, cause the at least one processor 1010 to: the following programming process is performed in a loop until the starting verify level of the current programming process is greater than the maximum verify level: determining a current memory unit to be programmed according to programming inhibition information stored in an intermediate register corresponding to each memory unit in a memory page to be programmed of a memory unit array; using the current programming voltage to perform current programming on the determined current memory cell to be programmed; determining a current to-be-programmed verification storage unit according to programming inhibition information stored in an intermediate register corresponding to each storage unit of the to-be-programmed page; performing program verification on the determined current memory cell to be program-verified using each of the maximum verify levels from the initial verify level of the current programming process; counting a verification failure statistical result of the program verification for the initial verification level; determining an initial verification level of a next programming process according to the verification failure statistical result; and updating the program inhibition information stored in the corresponding intermediate register according to the program verification result of each current memory cell to be programmed and verified.

It should be appreciated that the computer-executable instructions stored in the memory, when executed, cause the at least one processor 1010 to perform the various operations and functions described above in connection with fig. 1-9 in the various embodiments of the present description.

According to one embodiment, a program product, such as a machine-readable medium (e.g., a non-transitory machine-readable medium), is provided. A machine-readable medium may have instructions (i.e., elements described above as being implemented in software) that, when executed by a machine, cause the machine to perform various operations and functions described above in connection with fig. 1-9 in the various embodiments of the present specification. Specifically, a system or apparatus may be provided which is provided with a readable storage medium on which software program code implementing the functions of any of the above embodiments is stored, and causes a computer or processor of the system or apparatus to read out and execute instructions stored in the readable storage medium.

In this case, the program code itself read from the readable medium can realize the functions of any of the above-described embodiments, and thus the machine-readable code and the readable storage medium storing the machine-readable code form part of the present invention.

Examples of the readable storage medium include floppy disks, hard disks, magneto-optical disks, optical disks (e.g., CD-ROMs, CD-R, CD-RWs, DVD-ROMs, DVD-RAMs, DVD-RWs), magnetic tapes, nonvolatile memory cards, and ROMs. Alternatively, the program code may be downloaded from a server computer or from the cloud via a communications network.

It will be understood by those skilled in the art that various changes and modifications may be made in the above-disclosed embodiments without departing from the spirit of the invention. Accordingly, the scope of the invention should be determined from the following claims.

It should be noted that not all steps and units in the above flows and system structure diagrams are necessary, and some steps or units may be omitted according to actual needs. The execution order of the steps is not fixed, and can be determined as required. The apparatus structures described in the above embodiments may be physical structures or logical structures, that is, some units may be implemented by the same physical entity, or some units may be implemented by a plurality of physical entities, or some units may be implemented by some components in a plurality of independent devices.

In the above embodiments, the hardware units or modules may be implemented mechanically or electrically. For example, a hardware unit, module or processor may comprise permanently dedicated circuitry or logic (such as a dedicated processor, FPGA or ASIC) to perform the corresponding operations. The hardware units or processors may also include programmable logic or circuitry (e.g., a general purpose processor or other programmable processor) that may be temporarily configured by software to perform the corresponding operations. The specific implementation (mechanical, or dedicated permanent, or temporarily set) may be determined based on cost and time considerations.

The detailed description set forth above in connection with the appended drawings describes exemplary embodiments but does not represent all embodiments that may be practiced or fall within the scope of the claims. The term "exemplary" used throughout this specification means "serving as an example, instance, or illustration," and does not mean "preferred" or "advantageous" over other embodiments. The detailed description includes specific details for the purpose of providing an understanding of the described technology. However, the techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described embodiments.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for programming a memory system, the memory system including a page buffer including an intermediate register for buffering intermediate processing results during programming and storing program inhibit information after each round of programming, the program inhibit information indicating whether programming for a memory cell was successful, the method comprising:

the following programming process is performed in a loop until the starting verify level of the current programming process is greater than the maximum verify level:

determining a current memory unit to be programmed according to programming inhibition information stored in an intermediate register corresponding to each memory unit in a memory page to be programmed of a memory unit array;

using the current programming voltage to perform current programming on the determined current memory cell to be programmed;

determining a current to-be-programmed verification storage unit according to programming inhibition information stored in an intermediate register corresponding to each storage unit of the to-be-programmed page;

performing program verification on the current memory cell to be program-verified using each of verify levels from a start verify level to a maximum verify level of the current programming process;

counting a verification failure statistic result of the program verification for the initial verification level;

determining an initial verification level of a next programming process according to the verification failure statistical result; and

and updating the program inhibition information stored in the corresponding intermediate register according to the program verification result of each current memory cell to be programmed and verified.

2. The method of claim 1, wherein determining an initial verify level for a next programming process based on the verify failure statistics comprises:

determining a start verify level of the current programming process as a start verify level of a next programming process when the verification failure statistics indicate that there are memory cells for program verification of the start verify level that have failed programming;

determining a next verify level of a start verify level of the current programming process as a start verify level of a next programming process when the verify failure statistics indicate that there are no memory cells for which programming fails to verify for the start verify level.

3. The method of claim 1, wherein the plurality of memory cells of each memory page are coupled to a same wordline and the individual memory cells of each memory page are coupled to different bitlines,

determining a current memory cell to be programmed according to program inhibit information stored in an intermediate register corresponding to each memory cell in a memory page to be programmed of a memory cell array includes:

determining the bit line voltage of each memory cell according to the program inhibition information stored in the intermediate register corresponding to each memory cell in the memory page to be programmed of the memory cell array,

the current programming of the determined current memory cell to be programmed using the current programming voltage includes:

the current programming is performed by applying a current programming voltage to the word lines of the individual memory cells of the memory page and applying the determined bit line voltage to the bit lines of the individual memory cells of the memory page.

4. The method of claim 3, wherein the page buffer includes a bias information register,

determining the bit line voltage of each memory cell according to program inhibit information stored in an intermediate register corresponding to each memory cell in a memory page to be programmed of a memory cell array comprises:

determining the bit line voltage of each memory cell in the memory page to be programmed of the memory cell array according to the program inhibiting information stored in the intermediate register corresponding to the memory cell and the bias information in the corresponding bias information register,

the method further comprises the following steps:

performing bias verification on the current to-be-programmed verified memory cells using each of verify levels from a start verify level to a maximum verify level of the current programming process; and

and updating the bias information stored in the bias information register corresponding to each current memory cell to be programmed and verified according to the bias verification result of the memory cell.

5. The method of claim 4, wherein,

determining the bit line voltage of the memory cell according to the program inhibit information stored in the intermediate register corresponding to each memory cell in the to-be-programmed memory page of the memory cell array and the bias information in the corresponding bias information register, includes:

determining a first bit line voltage of each memory cell according to programming inhibition information stored in an intermediate register corresponding to each memory cell in a memory page to be programmed of a memory cell array, wherein the first bit line voltage comprises one of a low level and a high level;

writing the offset information in the offset information register of each storage unit into a corresponding intermediate register;

the first bit line voltage of each memory cell is adjusted to a second bit line voltage including one of a low level, a middle level, and a high level according to the bias information in each intermediate register.

6. The method of claim 5, further comprising:

and restoring the programming inhibition information stored in the intermediate register of each page buffer according to the initial verification level and the data bit of the data register in each page buffer.

7. The method of claim 6, wherein the memory system comprises a TLC NAND flash memory and the data registers comprise a low bit data register, an intermediate bit data register, and a high bit data register.

8. The method of claim 1, wherein the current programming voltage is generated in incremental step programming pulses.

9. A memory controller for programming a memory system, the memory system comprising a page buffer, the page buffer comprising an intermediate register for buffering intermediate processing results during programming and storing program inhibit information after each round of programming, the program inhibit information indicating whether programming for a memory cell was successful, the memory controller configured to:

10. The memory controller of claim 9, wherein the memory controller is configured to:

11. The memory controller of claim 9, wherein the plurality of memory cells of each memory page are coupled to a same wordline and the respective memory cells of each memory page are coupled to different bitlines,

the memory controller is configured to:

determining a bit line voltage of each memory cell according to program inhibit information stored in an intermediate register corresponding to each memory cell in a memory page to be programmed of the memory cell array, an

12. The memory controller of claim 11, wherein the page buffer comprises an offset information register,

the memory controller is configured to determine a bit line voltage of each memory cell in a memory page to be programmed of the memory cell array according to program inhibit information stored in an intermediate register corresponding to the memory cell and bias information in a corresponding bias information register,

the memory controller is further configured to:

performing bias verification on the current memory cell to be program-verified using each of verify levels from a start verify level to a maximum verify level of the current programming process, and

13. The memory controller of claim 12, wherein the memory controller is configured to:

14. The memory controller of claim 13, wherein the memory controller is further configured to:

15. A memory system, comprising:

an array of memory cells coupled to at least one word line and at least one bit line, the array of memory cells organized into memory pages, each memory page including a plurality of memory cells,

a voltage generation circuit coupled to at least one word line for generating programming voltages and respective verify levels for memory cells of the memory cell array;

a page buffer coupled to at least one bit line, the page buffer including an intermediate register to buffer intermediate processing results during programming and to store program inhibit information after each round of programming, the program inhibit information indicating whether programming for memory cells, one page buffer per memory cell, is successful; and

a memory controller configured to: the following programming process is performed in a loop until the starting verify level of the current programming process is greater than the maximum verify level:

16. A computing device, comprising:

at least one processor, and

a memory coupled with the at least one processor, the memory storing instructions that, when executed by the at least one processor, cause the at least one processor to perform the method of any of claims 1-8.

17. A machine-readable storage medium storing executable instructions that, when executed, cause the machine to perform the method of any one of claims 1 to 8.