CN111933198B

CN111933198B - Matchline detection circuit for Content Addressable Memory (CAM)

Info

Publication number: CN111933198B
Application number: CN202010958505.4A
Authority: CN
Inventors: 郭建华
Original assignee: New H3C Semiconductor Technology Co Ltd
Current assignee: New H3C Semiconductor Technology Co Ltd
Priority date: 2020-09-14
Filing date: 2020-09-14
Publication date: 2021-02-05
Anticipated expiration: 2040-09-14
Also published as: CN111933198A

Abstract

The application provides a matchline detection circuit of a Content Addressable Memory (CAM), wherein the CAM comprises a plurality of CAM units which are arranged in M rows and N columns, a plurality of local detection circuits and a global output circuit are configured on the N CAM units corresponding to each row, each local detection circuit is connected with the corresponding CAM unit through a local matchline, the local detection circuits are connected with each other through a global matchline, the global matchline is connected with the global output circuit, and M and N are natural numbers greater than 1, wherein: each local detection circuit for obtaining a local matching result; and the global output circuit is used for obtaining and outputting the data matching result corresponding to the row based on the local matching result output to the global matching line by each local detection circuit. By adopting the detection circuit, the charging and discharging time of the local match line is saved, so that the data searching speed of the CAM memory is improved.

Description

Matchline detection circuit for Content Addressable Memory (CAM)

Technical Field

The present application relates to the field of integrated circuit technologies, and in particular, to a matchline detection circuit for a content addressable memory CAM.

Background

A Content Addressable Memory (CAM) is a Memory mainly used for realizing a fast table lookup function, and the CAM can compare data to be queried with data stored in each row, so as to realize parallel lookup of the CAM, so that the CAM has high-efficiency and fast search capability, and is mainly applied to high-speed application occasions such as a cache, a router, a switch and the like in a CPU. The CAM includes a plurality of CAM cells, Match Lines (ML), and Search lines (SL/SLB) on which the CAM cells are mounted. Along with the increase of the data volume to be inquired, the IO number of the CAM is increased, so that the CAM cells hung on the matched line are increased, the capacitance of the matched line is increased, the charging and discharging time of the matched line is influenced finally, and the data searching speed is reduced.

When searching data from a CAM in the prior art, all CAM cells included in the CAM are connected to a detection circuit through a match line, and as the search data increases, the number of CAM cells hung on the match line increases, the load on the match line increases, the charging and discharging time of the match line is longer, and the search speed for searching the data in the CAM through the detection circuit is slower.

Therefore, how to increase the speed of searching data in the CAM is one of the considerable technical problems.

Disclosure of Invention

In view of the foregoing, the present application provides a matchline detection circuit for a content addressable memory CAM to increase the speed of searching data from the CAM.

Specifically, the method is realized through the following technical scheme:

according to a first aspect of the present application, a matchline detection circuit of a content addressable memory CAM is provided, where the content addressable memory CAM includes a plurality of CAM cells arranged in M rows and N columns, the N CAM cells corresponding to each row are configured with a plurality of local detection circuits and a global output circuit, each local detection circuit is connected to the corresponding CAM cell through a local matchline, the local detection circuits are connected to each other through a global matchline, the global matchline is connected to the global output circuit, and M and N are both natural numbers greater than 1, where:

each local detection circuit is used for precharging the local match line connected with the local detection circuit; after data to be queried is input into a CAM unit corresponding to the CAM unit, charging a local match line connected with the CAM unit, obtaining a local match result of the data to be queried according to the state of the local match line connected with the CAM unit, and outputting the local match result to a global match line;

and the global output circuit is used for obtaining and outputting the data matching result corresponding to the row based on the local matching result output to the global matching line by each local detection circuit.

According to a second aspect of the present application, there is provided a CAM comprising match line detection circuitry of a content addressable memory CAM as provided by the first aspect of the present application.

According to a third aspect of the present application, there is provided a data matching method based on a match line detection circuit of a content addressable memory CAM provided in the first aspect of the present application, including:

for each row of the content addressable memory, respectively precharging its connected local match lines through each local detection circuit connected to the row;

when data to be inquired is input into the CAM unit corresponding to the row, the local matched line connected with the CAM unit is charged through the local detection circuit connected with the CAM unit;

obtaining a local matching result of the data to be queried according to the state of the connected local matching line, and outputting the local matching result to a global matching line;

and outputting the data matching result corresponding to the row based on the local matching result output to the global matching line by the global output circuit based on each local detection circuit.

The beneficial effects of the embodiment of the application are as follows:

the CAM unit corresponding to each row in the content addressable memory is provided with the local detection circuits, the local detection circuits respectively detect the local matching results of the corresponding CAM units, the global output circuit respectively outputs the local matching results of the global match line based on the local detection circuits and outputs the data matching results corresponding to the row.

Drawings

FIG. 1 is a schematic diagram of a matchline detect circuit of a current CAM;

FIG. 2 is a schematic diagram illustrating a structure of a matchline detect circuit of a CAM according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of another CAM matchline detection circuit according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a CAM cell according to an embodiment of the present disclosure;

FIG. 5 is a timing diagram of a detection process of the detection circuit shown in FIG. 1;

FIG. 6 is a timing diagram illustrating the detection process of the matchline detection circuit of the CAM according to an embodiment of the present disclosure.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the corresponding listed items.

It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.

The inventor finds that, the CAM memory is formed by m rows and n columns of CAM cells, and a currently provided CAM detection circuit can be referred to as shown in fig. 1, for convenience of illustration, fig. 1 only shows the detection circuit of n columns of CAM cells in the first row, and the CAM cells in each row are hooked on the match lines corresponding to the row, that is, m rows correspond to m match lines, for example, n CAM cells in the first row shown in fig. 1 are hooked on a match line ml <1>, for the CAM cells in the first row, since n CAM cells are hooked on a match line ml <1>, the capacitance load of the match line ml <1> is extremely large when data is queried, and the charging and discharging time of the match line is longer as the capacitance load of the match line is larger, and the data lookup speed of the CAM cell is slower.

In view of the above, the present application provides a matchline detection circuit for a content addressable memory, where a plurality of local detection circuits are configured for a CAM cell corresponding to each row in the content addressable memory, the local detection circuits respectively detect local matching results of the corresponding CAM cells, and then a global output circuit outputs a data matching result corresponding to the row based on the local matching results respectively output to the global matchline by the local detection circuits.

The match line detection circuit of the content addressable memory CAM provided in the present application is described in detail below.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a matchline detection circuit of a content addressable memory CAM provided by the present application, where the content addressable memory CAM includes a plurality of CAM cells arranged in M rows and N columns, and based on the arrangement of the CAM cells in the CAM memory, in order to facilitate detection of data in the CAM memory, a plurality of Local detection circuits (L1-Lx) and a Global output circuit G are configured in the N CAM cells (CAM cell 0-CAM cell N) corresponding to each row of the CAM memory, that is, x is a value greater than or equal to 2, and each Local detection circuit is connected to the corresponding CAM cell by a Local Matchline (LML), and the Local detection circuits are connected to each other by a Global matchline (Global matchline), and the Global matchline GML is connected to the Global output circuit G, and as shown in fig. 2, M and N are both natural numbers greater than 1, wherein:

each local detection circuit for precharging a local match line connected thereto; after data to be queried is input into a CAM unit corresponding to the CAM unit, charging a local match line connected with the CAM unit, obtaining a local match result of the data to be queried according to the state of the local match line connected with the CAM unit, and outputting the local match result to a global match line;

the global output circuit is configured to obtain and output a data matching result corresponding to the row based on the local matching result output to the global match line by each local detection circuit.

The CAM cells detected by the local detection circuits (L1-Lx) may be the same or different.

Specifically, according to the present application, for N CAM cells in each row, the N CAM cells are divided into a plurality of sub-arrays, and then a local detection circuit is configured for each sub-array, for example, x sub-arrays are divided from the N CAM cells in the first row, which respectively are: CAM cells 1 to H are a sub-array, CAM cells h +1 to I are a sub-array and … …, CAM cells i +1 to N are a sub-array, CAM cells N +1 to N are a sub-array and so on, then X sub-arrays, that is, CAM cells included in the X sub-arrays, are respectively provided with X local detection circuits L1 to Lx, for the CAM cells included in each sub-array, the local detection circuits are connected with the CAM cells included in the sub-array through local matchlines, referring to FIG. 2, CAM cells 0 to H corresponding to the M-th row are connected with a local detection circuit L1 through local matchlines LML < M > _1, CAM cells h +1 to H are connected with a local detection circuit L2 through local matchlines LML < M > _2, … …, CAM cells N +1 to N are connected with a local detection circuit Lx through local matchlines LML < M > _ x and so on, namely, the local matching results of each local detection circuit in the first row are sequentially recorded as LML <1> _ b _ 1-LML <1> _ b _ x, and the local matching results of each local detection circuit in the M-th row are sequentially recorded as LML < M > _ b _ 1-LML < M > _ b _ x; therefore, the capacitance load of each local match line is greatly reduced, and the charging and discharging time of each local match line is greatly shortened, so that the data matching speed of the CAM can be improved.

When the local detection circuit is configured for CAM cells, N CAM cells per row may be divided into x sub-arrays, where the CAM cells included in each sub-array obtained by the division are consecutively numbered.

In addition, when the detection circuit is used for searching data to be inquired, the local match line and the global match line are precharged firstly, so that the local match line and the global match line can work normally. After the precharge is completed, data matching is performed, that is, in the data comparison stage, each local detection circuit detects a data query result, also called a local matching result, of the corresponding CAM cell, and then the local matching result is introduced to the global match line, so that the global output circuit G connected to the global match line outputs a data matching result corresponding to the row, that is, a result of whether the data to be queried matches the data stored in the N CAM cells of the row based on the local matching result detected by each local detection circuit, and in general, the data matching is represented by "1", and the data mismatch is represented by "0".

In the present application, the timing of inputting the data to be queried to the CAM cell may be before the local match line is precharged, or after the local match line is precharged, but before the local match line is charged.

Optionally, the match line detection circuit of the CAM provided by the present application further includes: a plurality of global matchline control circuits GC 1-GCx are respectively interposed between each local detection circuit and the global matchline, as also shown in FIG. 2, wherein:

each global matching line control circuit is used for outputting a first level switching signal corresponding to the local matching result output by the local detection circuit connected with the global matching line control circuit under the action of the local matching result output by the local detection circuit connected with the global matching line control circuit;

the global output circuit is specifically configured to obtain and output a data matching result corresponding to the row based on the first level shift signal corresponding to each local matching result.

It should be noted that, when the global match line control circuit in the present application is used in combination with a global output circuit, the internal structure of any one circuit changes, and the content structure of the other circuit needs to adapt to the changed current, so as to not only charge and discharge the global match line, but also accurately obtain and output the match result of the line.

Specifically, since a plurality of local detection circuits are allocated to the CAM cells in any row, the global match line is also segmented, that is, a global match line control circuit is provided between each local detection circuit and the global match line, so as to control charging and discharging of the global match line, convert the local match result output by the local detection circuit connected thereto, output a first level conversion signal, and apply the first level conversion signal to the global match line. And then, the global output circuit obtains and outputs the data matching result corresponding to the row according to the first level conversion signal corresponding to each local matching result output by each global matching line control circuit. It should be noted that the first level-shift signal can represent each local match result, and referring to fig. 2, the global match lines for each global precharge circuit partition in the first row are sequentially denoted as GML <1> _1 to GML <1> _ x, the global match lines for each global precharge circuit partition in the mth row are sequentially denoted as GML < M > _1 to GML < M > _ x,

optionally, each global match line control circuit comprises a first field effect transistor, wherein: the first end of the first field effect transistor is connected with the corresponding local detection circuit; the second end of the first field effect transistor is connected with a ground end or a global match line; and the third end of the first field effect transistor is connected with a global matching line or a global output circuit.

Specifically, the first field effect transistors may be NMOS transistors, and the first, second, and third ends of the NMOS transistors are gates, sources, and drains, respectively, as shown in fig. 3, and the NMOS transistors corresponding to MNg 1-MNgx in fig. 3 are the x first field effect transistors, that is, the x global matching line control circuits GC 1-GCx. It should be noted that, since the global match line control circuit is connected to the global match lines, it can be understood that a plurality of global match line control circuits divide a global match line into a plurality of segments, that is, form segmented global match lines, referring to global match lines GML < M > _1 to global match lines GML < M > _ x in fig. 3.

It should be noted that, the first field effect transistor may also be a PMOS transistor, and in the case of the PMOS transistor, the internal structure of the global output circuit also needs to be changed adaptively to meet the requirement of implementing the charging and discharging capability of the global match line, and also can accurately obtain and output the matching result of the line.

Optionally, in this embodiment, each CAM unit is numbered in sequence, and a connection relationship between three terminals of the first field-effect transistor connected to the local detection circuit corresponding to the first number and the last number varies according to a circuit structure, which may specifically include the following two cases:

the first condition is as follows: the second end of the first field effect transistor connected with the local detection circuit for processing the first serial number is connected with the ground end, the third end of the first field effect transistor is connected with the global matchline, the second end of the first field effect transistor connected with the local detection circuit for processing the last serial number is connected with the global matchline, and the third end of the first field effect transistor is connected with the global output circuit.

Case two: the second end of the first field effect transistor connected with the local detection circuit for processing the last number is connected with the ground end, the third end of the first field effect transistor is connected with the global matchline, the second end of the first field effect transistor connected with the local detection circuit for processing the first number is connected with the global matchline, and the third end of the first field effect transistor is connected with the global output circuit.

Specifically, for convenience of description, the first case is taken as an example, the numbers of the N CAM cells corresponding to each row of the CAM memory are shown in fig. 2, CAM cells 0 to N are numbered consecutively, and accordingly, when the local detection circuits are configured, the configured local detection circuits are assigned in the order of the numbers, for example, CAM cells 0 to h correspond to local detection circuit L1, CAM cells h +1 to CAM cells correspond to local detection circuit L2, and so on. On this basis, when the first fet is an NMOS transistor, please refer to fig. 3, in which the local sensing circuit for processing the first number is marked as a local sensing circuit L1, the gate of the NMOS transistor MNg1 connected to the local sensing circuit L1 is connected to the local sensing circuit, the source of MNg1 is connected to ground, and the drain of MNg1 is connected to the global match line; similarly, if the local detection circuit for processing the last serial number is the local detection circuit Lx, the gate of the NMOS transistor MNgx connected to the local detection circuit Lx is connected to the local detection circuit Lx, the source of the NMOS transistor MNgx is connected to the global match line, and the drain of the NMOS transistor MNgx is connected to the global output circuit.

It should be noted that, when the connection relationship is the second case, the drain of the first field effect transistor corresponding to the second case is connected to the global output circuit, which is equivalent to changing the arrangement of the CAM cells 1 to N from left to right in fig. 2 into the CAM cells N to 1 from left to right.

Optionally, the match line detection circuit of the CAM provided in this embodiment further includes: a plurality of global precharge circuits GY 1-GYx, the number of the global precharge circuits is the same as the number of the local detection circuits, each global precharge circuit is connected to a global match line by a global match line control circuit corresponding to a corresponding local detection circuit, as shown in fig. 2, wherein:

each global precharge circuit is used for precharging the global match line connected with the global precharge circuit.

Specifically, as shown in fig. 2, the global match line control circuit GC1 of the global precharge circuit GY1 coupled to the local detection circuit L1 is coupled to the global match line GML < M > _1, the global match line control circuit GCx of the global precharge circuit GYx coupled to the local detection circuit Lx is coupled to the global match line GML < M > _ x, and the global precharge circuit GYx-1 and the corresponding global match line control circuit GCx-1 (not shown) are coupled to the global match line GML < M > _ x-1 in fig. 2. After each global pre-charging circuit is used for pre-charging the respective global match line, the charging and discharging of the global match line are controlled by the global match line control circuit.

Furthermore, each global precharge circuit GY 1-GYx comprises a second field effect transistor, a first end of the second field effect transistor is used for inputting a first precharge signal, a second end of the second field effect transistor is connected with a power supply input end, and a third end of the second field effect transistor is connected with a global match line.

Specifically, the second field effect transistor may be a PMOS transistor, and the first end, the second end, and the third end of the PMOS transistor are respectively a gate, a source, and a drain, and the gate of the PMOS transistor is used for inputting the first precharge signal, the source is used for inputting the power voltage, and the drain of the PMOS transistor is connected to the global match line, that is, the drain of the global match line control circuit corresponding to the local detection circuit, as shown in fig. 3, the PMOS transistors corresponding to MPg 1-MPgx in fig. 3 are x global precharge circuits GY 1-GYx, and gprc _ n in fig. 3 is the first precharge signal.

Optionally, the global output circuit provided by the present application includes a first half latch circuit, where:

and the first half latch circuit is respectively connected with the power supply input end and the global matchline and used for obtaining and outputting the data matching result corresponding to the row based on the first level conversion signal corresponding to each local matching result.

Specifically, after each local detection circuit introduces the local match result of the corresponding CAM cell to the global match line, that is, after the first level shift signal is applied to the global match line, the first half latch circuit obtains the data match result corresponding to the row based on each first level shift signal.

Optionally, the first latch circuit in this application includes a third field effect transistor and a first inverter, a first terminal of the third field effect transistor is connected to an output terminal of the first inverter, a second terminal of the third field effect transistor is connected to the power input terminal, and a third terminal of the third field effect transistor is connected to an input terminal of the first inverter and a third terminal of the third field effect transistor, respectively. Specifically, the third fet may be a PMOS transistor, and please refer to fig. 3, where MPgb in fig. 3 is the third fet. The first end, the second end and the third end of the third field effect transistor are respectively a grid electrode, a source electrode and a drain electrode. The input end of the first inverter is used to input the level signal of the global match line under the action of each local match result, the output end of the first inverter is used to output the data match result corresponding to the row, and the INVg1 in fig. 3 is the first inverter.

Specifically, in general, when the local matching results of the local detection circuits are all the same and are at a high level 1, it is indicated that the data to be queried is successfully matched, and other situations indicate that the data to be queried is not successfully matched. For example, if the local matching result output by each local detection circuit is high level 1, which indicates that each local matching result is a successful match, the NMOS transistor of the global matching line control circuit connected to each local detection circuit is turned on, so that the drain voltage of each NMOS transistor is low level 0, that is, the first level shift signal corresponding to each local detection circuit is low level 0, which may be understood as performing an and operation on each first level shift signal on the global matching line, and in order to output an accurate matching result, by setting the first inverter, each first level shift signal is input to the first inverter, and then an accurate global matching result, that is, the global matching result is high level, which indicates that the data stored in the row of CAM cells is hit. For example, when the local match result output by the local detection circuit L1 is high level 1, indicating that the local match result is a successful match, the NMOS transistor MNg1 of the global match line control circuit connected to the local detection circuit is turned on, so that the drain voltage of MNg1 is low level 0, i.e., the first level shift signal corresponding to the local detection circuit L1 is low level 0, and at this time, the local match result output by the local detection circuit Lx is low level 0, indicating that the local match result is a failed match, the MNgx connected to the local detection circuit Lx is not turned on, so that the drain voltage of MNgx is high level 1, i.e., the first level shift signal corresponding to the local detection circuit Lx is high level 1, and the voltage of the global GML < M > _1 is high level, i.e., when there is a match failure of a partial CAM cell (CAM cell detected by the local detection circuit Lx), indicating that the data match result corresponding to the row is a match failure, by providing the first inverter, when the first level shift signal (high level 1) corresponding to the local detection circuit Lx is input to the first inverter, a low level is output, that is, a result of a matching failure is output, thereby realizing accurate output of a data search result of the CAM cell corresponding to the row.

Optionally, each local detection circuit provided by the present application includes a first pre-charge circuit, a second pre-charge circuit, a second half latch circuit, and a local match line control circuit, wherein: the first precharge circuit, the charge circuit, and the local match line control circuit are connected to a local match line corresponding to the local detection circuit, and the second precharge circuit is connected to the local match line control circuit and the second half latch circuit, respectively, wherein:

the first precharge circuit is configured to precharge a local match line corresponding to the local detection circuit;

the second precharge circuit is configured to precharge a connection line between the local match line control circuit and the second half latch circuit;

the charging circuit is configured to charge a local match line corresponding to the local detection circuit after the local match line is precharged, and compare the data to be queried with data stored in a CAM cell hung below the local match line to obtain a local match result of the data to be queried;

the local match line control circuit is used for outputting a second level conversion signal of the local match result under the action of the local match result of the data to be inquired;

the second half latch circuit is configured to convert the second level shift signal, latch, and output a local matching result of the data to be queried.

Specifically, when the local detection circuit performs data matching, the first precharge circuit precharges the local match line connected to the first precharge circuit, that is, at the precharge stage, to ensure that the local match line operates normally. Inputting data to be queried into a CAM cell hung under a local match line, entering a comparison stage after the precharge is completed, and when entering the comparison stage, defaulting that the data to be queried is input into the CAM cell hung under the local match line, charging the local match line by a charging circuit at the moment, wherein a level signal of the local match line reflects a local match result of the CAM cell, namely, when data stored in the CAM cell detected by a local detection circuit is matched with the data to be queried, a pull-down discharge channel of the local match line is closed, so that the local match line is charged to a high level, namely, a high-level local match result is obtained; when the data stored in the CAM cell detected by the local detection circuit does not match the data to be queried, the pull-down discharge channel of the local match line is turned on, so that the potential of the local match line is pulled to a low level, that is, a local match result of the low level is obtained.

On the basis, the local match result is input to a local match line control circuit, the local match line control circuit is used for controlling charging and discharging of the local match line on one hand, and on the other hand, the local match result is converted into a second level conversion signal and input to a second half latch circuit, the second level conversion signal is used for representing the local match result, and then the second half latch circuit converts and latches the local match result based on the data to be queried inquired by the CAM unit corresponding to the local detection circuit after the second level conversion signal is input.

Optionally, the first precharge circuit provided by the present application includes a fourth field effect transistor, a first end of the fourth field effect transistor is configured to input the second precharge signal, a second end of the fourth field effect transistor is connected to a ground terminal, and a third end of the fourth field effect transistor is connected to the local matchline, and is configured to precharge the local matchline connected to the third end of the fourth field effect transistor. Specifically, the fourth fet may be an NMOS transistor, and as shown in fig. 3, the first terminal, the second terminal, and the third terminal of the fourth fet are respectively a gate, a source, and a drain, for example, MN1 to MNx1 in fig. 3 are the fourth fet, and prc in fig. 3 is a second precharge signal.

Optionally, the second precharge circuit provided by the present application includes a fifth field effect transistor, a first end of the fifth field effect transistor is used for inputting a third precharge signal, a second end of the fifth field effect transistor is connected to the power supply input end, and a third end of the fifth field effect transistor is connected to the local match line control circuit. Specifically, the fifth fet may be a PMOS transistor, and as shown in fig. 3, the first terminal, the second terminal, and the third terminal of the fifth fet are respectively a gate, a source, and a drain, for example, MP2 to MPx2 in fig. 3 are the fifth fet, and prc _ n in fig. 3 is a third precharge signal.

Optionally, the charging circuit provided by the present application includes a current source and a sixth field effect transistor, wherein a first end of the current source is connected to the power input end, a second end of the current source is connected to a second end of the sixth field effect transistor, a first end of the sixth field effect transistor is used for inputting an enable signal en, and a third end of the sixth field effect transistor is connected to the local match line. Specifically, the sixth fet may be a PMOS transistor, and as shown in fig. 3, the first terminal, the second terminal, and the third terminal of the sixth fet are respectively a gate, a source, and a drain, and MP 1-MPx 1 in fig. 3 are the sixth fet.

Optionally, the local match line control circuit provided by the present application includes a seventh fet, a first terminal of the seventh fet is connected to the local match line, a second terminal of the seventh fet is connected to the ground terminal, and a third terminal of the seventh fet is connected to a third terminal of the fifth fet. Specifically, the seventh fet may be an NMOS transistor, and as shown in fig. 3, the first terminal, the second terminal, and the third terminal of the seventh fet are respectively a gate, a source, and a drain, and MN2 to MNx2 in fig. 3 are the seventh fet.

Optionally, the second half latch circuit provided by the present application includes an eighth fet and a second inverter, a first end of the eighth fet is connected to an output end of the second inverter, a second end of the eighth fet is connected to the power input end, and a third end of the eighth fet is connected to an input end of the second inverter, a third end of the fifth fet, and a third end of the seventh fet, respectively. Specifically, the eighth fet may be a PMOS transistor, and as shown in fig. 3, the first terminal, the second terminal, and the third terminal of the eighth fet are respectively a gate, a source, and a drain, and MP 3-MPx 3 in fig. 3 are the eighth fet. The input end of the second inverter is used for inputting the voltage of the corresponding local match line, the output end of the second inverter is used for outputting the data matching result of the corresponding CAM cell, and INV 1-INVx 1 in FIG. 3 are the second inverter.

Optionally, each CAM cell in the present application includes a memory cell and a pull-down channel circuit controlled by an internal node of the memory cell and data to be queried, where the pull-down channel is used to input the data to be queried and then output a local match result through a local match line. The internal storage structure of the CAM cell is various, the structure of the CAM cell is not limited in the present application, and for the convenience of understanding, fig. 4 shows the internal structure of the CAM cell, and the data to be queried is input through the search line SL/SLB, but fig. 4 does not constitute the structural limitation of the CAM cell.

By implementing the detection circuit provided by the application, aiming at each row of the CAM memory, the data search results of the corresponding CAM cells are respectively detected by utilizing the plurality of local detection circuits, so that the load of the whole row of CAM hung to a match line is greatly reduced compared with the capacitive load of the local match lines connected with the plurality of local detection circuits, the local matching result of the local detection circuit for detecting the corresponding CAM cells can be shortened, and the plurality of local detection circuits are implemented in parallel, so that the data search result of the row is effectively shortened, and each row of the CAM memory is implemented in the above-mentioned way, so that the data search speed of searching data from the CAM memory is obviously increased.

In order to better understand the processing procedure of the match line detection circuit of the CAM provided by the present application, the detection circuit shown in fig. 3 is taken as an example to illustrate the working principle of the detection circuit provided by the present application, and it should be noted that when data is searched from the CAM memory, the data is queried row by row, therefore, when the detection circuit is designed, one detection circuit is connected to each row, and the processing procedure of each row is the same. For convenience of description, the circuit for detecting the N CAM cells corresponding to the mth row in the CAM memory of fig. 3 is taken as an example, the device is used for detecting that CAM units 0-CAM units h are connected with a local detection circuit L1 through local matching lines of LML < M > _1, CAM units N + 1-CAM units N are connected with a local detection circuit Lx through local matching lines of LML < M > _ x, NOMS (fourth field effect transistors) of a first pre-charging circuit in each local detection circuit are sequentially MN 1-MNx 1, PMOS (fifth field effect transistors) of a second pre-charging circuit are sequentially MP 2-MPx 2, NMOS (sixth field effect transistors) of each charging circuit are MP 1-MPx 1, NMOS (seventh field effect transistors) of each local matching line control circuit are sequentially MN 2-MNx 2, PMOS (eighth field effect transistors) of each second half latch circuit are sequentially MP 3-MPx 3, and INV phase inverters in each second half latch circuit are sequentially Vx 35 1-INx 1; recording local matching results of all local detection circuits in the M-th row as LML < M > _ b _ 1-LML < M > _ b _ x in sequence; correspondingly, the global match lines segmented by the global pre-charging circuits of the Mth row are sequentially marked as GML < M > _ 1-GML < M > _ x, and NMOS tubes (first field effect tubes) of the global match line control circuits are MNg 1-MNgx; the PMOS (second field effect transistor) of each global precharge circuit is MPg 1-MPgx, the PMOS (third field effect transistor) in the first half latch circuit is MPgb, and the first inverter in the first half latch circuit is INVg 1.

On this basis, in the detection of the states of the CAM cells included in the row, two stages of precharging and comparing are included, taking the example of detecting the CAM cells 0 to h by the local detection circuit L1 as an example, in the precharging stage, the MN1 inputs the second precharge signal prc of high level to pull the level signal of the local match line LML < M > _1 to the ground, i.e., low level 0, and at this time, the third precharge signal prc _ n of low level precharges the connection line connected to the drain terminal of the local match line control circuit MN2 to high level VDD through the MP2, so that the local match result LML < M > _ b _1 output through the second inverter INV1 is pulled to the ground, i.e., low level 0 through the second half latch circuit. The data to be queried is input during this precharge phase and can be given via the look-up line SL/SLB. Since the local matching result LML < M > _ b _1 is applied to the gate of MNg1, since MNg1 is an NMOS transistor, MNg1 is in the off state when the gate inputs a low level of 0; at this time, the enable signal en input by the charging circuit is at a high level, and the charging path of the corresponding local match line LML < M > _1 is disconnected, since the local match line LML < M > _1 in the precharge stage needs to be pulled to the ground. The low-level first precharge signal gprc _ n in the precharge stage precharges the global match line GML < M > of each segment to a high level, and when the high-level global match line GML < M > _ x is connected to the first inverter INVg1, the global match result GML < M > _ b output by the INVg1 is low, that is, the data query result corresponding to the row is low, and since no data query is currently performed, a low level is output and latched by the half latch.

And in the comparison stage, the second pre-charge signal prc is changed to low level, the third pre-charge signal prc _ n and the first pre-charge signal gprc _ n are changed to high level, when the enable signal en is changed from high level to low level, the local match line LML < M > _1 is started to be charged through the current source, the charging current is Iml, when the data stored in the CAM cells 0-h are matched with the data to be inquired, the pull-down discharge channel of the local match line LML < M > _1 is closed, the local match line LML < M > _1 is rapidly charged to high level, when the potential of the charged local match line LML < M > _1 is greater than the threshold voltage Vtn of MN2, MN2 is conducted, so that the connection line connected with the drain of MN2 is pulled to the ground, the local match result LML < M > _ b _1 is changed to high level, the characterization match is successful, and the local match result LML < M > _ b _1 drives MNg1 to be conducted, so that the global match line GML < M > _1 is discharged, i.e., the level of the global match line GML < M > _1 connected at MNg1 becomes low; if the local match result output by the other local detection circuits is also at a high level, the respective MNgx is driven to be turned on, so that the level of the global match line is changed to a low level, and then after the first inverter INVg1 is applied, a high level is output, that is, GML < M > _ b is at a high level, that is, the data match result corresponding to the row is a successful match, which indicates that the N CAM cells in the row hit the data to be queried, that is, the data to be queried can be successfully detected by the match line detection circuit of the CAM provided by the present application.

When the data stored in the row of CAM cells is not matched with the data to be queried, that is, there is at least one local detection result of the local detection circuit as mismatch, and the local match results of the local detection circuits L1 corresponding to the CAM cells 0-h are not matched, at this time, the pull-down discharge channel of the local match line LML < M > _1 connected to the local detection circuit L1 is opened, the local match line LML < M > _1 is charged to a lower potential, the voltage of the lower point is ImlxRml/j, where j is the number of unmatched CAM cells, since the potential is less than the threshold voltage of MN2, MN2 is not opened, the local match result LML < M > _ b _1 is still kept at a low level, so that the global match line control circuit MNg1 is not opened, that is the pull-down channel of the global match line is still closed, and the level of the global match line is at a high level, when the global match line with a high level is connected to the first inverter INVg1, the first inverter INVg1 outputs a low level, i.e., GML < M > _ b is low, i.e., indicating that the match fails, and the N CAM cells in the row miss the data to be queried, i.e., the match line detection circuit of the CAM provided in the present application can output the query result of the data to be queried.

For better understanding of the CAM matchline detection circuits provided in the present application, fig. 5 and 6 show timing diagrams of the prior art and the detection circuits of the present application, and by comparison, it is found that the query speed of the prior detection circuit with each row hooked to one matchline is significantly lower than the data query speed of the detection circuit provided in the present application. In fig. 5 and 6, VDD is 800mV, 90 CAM cells are mounted on each match line in the prior art detection circuit, 30 CAM cells are mounted on each local match line in each row of the present application, which is divided into 3 local match lines, and the total number of 90 CAM cells, and the detection circuit of the local match line is consistent with the size, charging current Iml, timing relationship, and the like of the MOS transistor used in the prior art detection circuit. From the timing results, it can be found that the charging and discharging speed of the local matchlines is greatly improved compared with the prior art, in the pre-charging stage, as can be seen from fig. 5, the discharging time of the matchlines from VDD × 90% to VDD × 10% in the prior art is 142.6pS, while in the present application, as can be seen from fig. 6, the discharging time of the local matchlines from VDD × 90% to VDD × 10% in the circuit detection structure of the segmented local matchlines and a global matchline is 43.6 pS. In the comparison stage, it can be seen from fig. 5 that the charging time of the prior art lower match line from VDD × 10% to VDD × 90% is 473.3 pS; as can be seen from fig. 6, in the segmented local matchline structure of the present application, the charging time of the local matchline from VDD × 10% to VDD × 90% is 158.3 pS. In addition, the time from the enabling of the en signal to the turning of the global matching result is one of the key indexes affecting the data searching speed, and it can be seen from fig. 5 that the time of the turning is 365.7pS in the prior art; it can be seen from FIG. 6 that the turnover time is 183.1pS, which is a reduction of nearly 50%. In conclusion, the segmented local match line and global match line structure adopted by the method can obviously reduce the charging and discharging time of the match line, greatly improve the pre-charging and comparing speed, and further improve the query speed of data from the CAM memory.

Based on the same inventive concept, the present application further provides a content addressable memory CAM, which includes the match line detection circuit of the CAM provided in any of the above embodiments, where the match line detection circuit of the CAM is used to search data in the content addressable memory.

Based on the same inventive concept, the present application further provides a data matching method for a matchline detection circuit of a CAM according to any of the above embodiments of the present application, including: for each row of the content addressable memory, respectively precharging its connected local match lines through each local detection circuit connected to the row; when data to be inquired is input into the CAM unit corresponding to the row, the local matched line connected with the CAM unit is charged through the local detection circuit connected with the CAM unit; obtaining a local matching result of the data to be queried according to the state of the connected local matching line, and outputting the local matching result to a global matching line; and outputting the data matching result corresponding to the row based on the local matching result output to the global matching line by the global output circuit based on each local detection circuit.

By adopting the method, the required data can be accurately and quickly searched from the CAM memory.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.

Claims

1. A matchline detection circuit of a Content Addressable Memory (CAM), wherein the CAM comprises a plurality of CAM cells arranged in M rows and N columns, the N CAM cells corresponding to each row are configured with a plurality of local detection circuits and a global output circuit, each local detection circuit is connected with the corresponding CAM cell through a local matchline, each local detection circuit is connected with the corresponding CAM cell through a global matchline, the global matchline is connected with the global output circuit, and M and N are natural numbers greater than 1, wherein:

2. The match line detection circuit for a Content Addressable Memory (CAM) of claim 1, further comprising: a plurality of global matchline control circuits interposed between each local detection circuit and the global matchline;

3. The match line detection circuit for a Content Addressable Memory (CAM) of claim 2, wherein each global match line control circuit comprises a first Field Effect Transistor (FET), wherein:

the first end of the first field effect transistor is connected with the corresponding local detection circuit;

the second end of the first field effect transistor is connected with a ground end or a global matched line;

the third end of the first field effect transistor is connected with a global matching line or a global output circuit;

the first field effect transistor is an NMOS transistor, and the first end, the second end and the third end are respectively a grid electrode, a source electrode and a drain electrode; and when the second end of the first field effect transistor is connected with the ground end, the third end is connected with the global matchline, and when the second end of the first field effect transistor is connected with the global matchline, the third end is connected with the global output circuit.

4. The matchline detect circuit of claim 3 wherein each CAM cell is numbered sequentially, a second terminal of the first FET coupled to the local detect circuit for handling a first number being coupled to ground, and a third terminal being coupled to a global matchline; and

a second terminal of the first fet, which is connected to the local detection circuit for processing the last number, is connected to the global match line, a third terminal is connected to the global output circuit, or,

the second end of the first field effect transistor connected with the local detection circuit for processing the tail number is connected with the ground end, and the third end of the first field effect transistor is connected with the global match line; and

the second end of the first field effect transistor connected with the local detection circuit for processing the first serial number is connected with the global matching line, and the third end of the first field effect transistor is connected with the global output circuit.

5. The match line detection circuit for a Content Addressable Memory (CAM) of claim 2, further comprising: the global pre-charging circuits are the same as the local detection circuits in number, and each global pre-charging circuit is connected to a global matching line through a global matching line control circuit corresponding to the corresponding local detection circuit, wherein:

6. The matchline detection circuit for a Content Addressable Memory (CAM) of claim 5, wherein each global precharge circuit comprises a second FET, a first terminal of the second FET being for inputting a first precharge signal, a second terminal of the second FET being coupled to a power input, a third terminal of the second FET being coupled to a global matchline;

the second field effect transistor is a PMOS transistor, and the first end, the second end and the third end are respectively a grid electrode, a source electrode and a drain electrode.

7. The match line detection circuit for a Content Addressable Memory (CAM) of claim 2, wherein the global output circuit comprises:

8. The match line detection circuit for a Content Addressable Memory (CAM) of claim 1, wherein each local detection circuit comprises a first precharge circuit, a second precharge circuit, a charging circuit, a second half latch circuit, and a local match line control circuit, wherein: the first pre-charge circuit, the charge circuit and the local match line control circuit are all connected with the local match line corresponding to the local detection circuit, the second pre-charge circuit is respectively connected with the local match line control circuit and the second semi-latch circuit, and

the first pre-charging circuit is used for pre-charging the local match line corresponding to the local detection circuit;

the second pre-charging circuit is used for pre-charging a connecting line between the local matchline control circuit and the second half latch circuit;

the charging circuit is used for charging the local match line after the local match line corresponding to the local detection circuit is precharged, and comparing the data to be queried with the data stored in the CAM unit hung below the local match line to obtain a local matching result of the data to be queried;

the local match line control circuit is used for outputting a second level conversion signal of a local match result under the action of the local match result of the data to be inquired;

and the second half latch circuit is used for converting the second level conversion signal, latching and outputting a local matching result of the data to be inquired.

9. A CAM comprising match line detection circuitry for a content addressable memory CAM according to any of claims 1 to 8.

10. A data matching method based on the matchline detection circuit of CAM in any of claims 1-8, comprising: