CN111883448A - Back grinding optimization method and device applied to small chip - Google Patents
Back grinding optimization method and device applied to small chip Download PDFInfo
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- 238000000227 grinding Methods 0.000 title claims abstract description 273
- 238000000034 method Methods 0.000 title claims abstract description 58
- 238000005457 optimization Methods 0.000 title claims abstract description 14
- 235000012431 wafers Nutrition 0.000 claims abstract description 127
- 238000012360 testing method Methods 0.000 claims abstract description 113
- 230000001681 protective effect Effects 0.000 claims abstract description 85
- 239000013078 crystal Substances 0.000 claims abstract description 62
- 238000005520 cutting process Methods 0.000 claims abstract description 12
- 238000005498 polishing Methods 0.000 claims description 27
- 238000007781 pre-processing Methods 0.000 claims description 6
- 239000011241 protective layer Substances 0.000 claims description 4
- 238000005336 cracking Methods 0.000 abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000002390 adhesive tape Substances 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000009966 trimming Methods 0.000 description 3
- 239000002699 waste material Substances 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- OEBRKCOSUFCWJD-UHFFFAOYSA-N dichlorvos Chemical compound COP(=O)(OC)OC=C(Cl)Cl OEBRKCOSUFCWJD-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 description 2
- 238000005299 abrasion Methods 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
- B24B37/042—Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
- B24B37/07—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool
- B24B37/10—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool for single side lapping
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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Abstract
The invention discloses a back grinding optimization method and a back grinding optimization device applied to a small chip, wherein the method comprises the following steps: providing a plurality of groups of test wafers; performing pre-cutting operation on the front side, attaching a grinding protective film, and sequentially grinding the back side of the test wafer to obtain first state information; wherein the grinding protective film corresponding to the test wafer with the best grain first state information is a preset grinding protective film; providing a plurality of groups of test wafers again, performing precutting operation on the front surfaces of the test wafers, and attaching a preset grinding protective film; acquiring a plurality of groups of grinding parameters, and grinding the test wafer respectively to acquire second state information; the grinding parameters corresponding to the test wafer with the best second state information of the crystal grains are preset grinding parameters, and through reasonable selection of the grinding protective film and the grinding parameters, the conditions of crystal flying, crystal cracking and the like in the back grinding process can be reduced, the back grinding quality is improved, and the grinding machine is protected.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a back grinding optimization method and device applied to a small chip.
Background
The development of integrated circuit chips is continuously moving toward high density, high performance, light weight, short size, and small size, and in order to meet the IC packaging requirements, thinning the backside of a patterned silicon wafer becomes an important process in the latter half of the semiconductor fabrication process. The DBG processing technology (trimming before grinding) is to cut a certain depth notch on the front side of a silicon wafer before grinding the back side, and then grinding, so that the warping of the silicon wafer caused by thinning and the edge damage caused by scribing can be well avoided or reduced, and the breakage resistance of a chip is greatly enhanced. With the application of large-diameter silicon wafers, the thickness of the silicon wafers is correspondingly increased, the advanced packaging technology requires thinner chips, and the DBG is widely applied as a main process for thinning the back of the silicon wafers.
However, in the case of grinding a small chip, particularly when the chip size is less than 1mm × 1mm, due to the factor of smaller size of the crystal grain (die), after the pre-cut is completed, a large flying die and a large cracking die are generated in the product grinding process, the flying die has a large potential safety hazard to the grinding wheel of the grinding machine and the Gauge, and when a large amount of flying die and cracking die exist in the chip, the yield and quality of the product and the grinding machine are greatly affected.
Therefore, a new technical solution is needed to solve the problems in the prior art.
Disclosure of Invention
In view of the above problems in the prior art, an object of the present invention is to provide a method and an apparatus for optimizing backside grinding of a small chip, which can obtain a grinding protection film and grinding parameters more suitable for backside grinding of the small chip, and improve the yield and quality of the product.
In order to solve the technical problems, the specific technical scheme of the invention is as follows:
the invention provides a back grinding optimization method applied to a small chip, which is characterized by comprising the following steps of:
providing a plurality of groups of test wafers, wherein each test wafer comprises a front side formed with an integrated circuit and a back side corresponding to the front side;
performing pre-cutting operation on the front surface, attaching grinding protective films, and attaching different grinding protective films to a plurality of groups of test wafers;
sequentially grinding the back of the test wafer to obtain first state information of crystal grains bonded on the grinding protective film;
comparing the first state information, wherein the grinding protective film corresponding to the test wafer with the best first state information of the crystal grains is a preset grinding protective film;
providing a plurality of groups of test wafers again, performing precutting operation on the front surfaces of the test wafers, and attaching the preset grinding protective film;
acquiring a plurality of groups of grinding parameters, respectively grinding the test wafer, and acquiring second state information of crystal grains bonded on the grinding protective film, wherein the grinding parameters comprise grinding rotating speed and grinding vacuum degree;
and comparing the second state information, wherein the grinding parameter corresponding to the test wafer with the best second state information of the crystal grains is a preset grinding parameter.
Further, the pre-cutting operation is performed on the front surface, and a polishing protection film is attached to the front surface, and before attaching different polishing protection films to a plurality of groups of test wafers, the method further includes:
obtaining a plurality of groups of grinding protective films of different types, wherein each group of grinding protective films comprises a plurality of grinding protective films of different thicknesses.
Further, attaching different polishing protection films to the plurality of groups of test wafers comprises:
and different types of grinding protective films are attached to a plurality of groups of test wafers, wherein each group of test wafers comprises a plurality of test wafers, and the plurality of test wafers are attached with the grinding protective films with different thicknesses.
Optionally, the grinding protection film comprises a UV film E-8310, a UV film E-3281 and a UV film D-210, and the thickness of the grinding protection film is 100-400 um.
Further, the sequentially grinding the back surface of the test wafer to obtain the first state information of the die bonded to the grinding protection film includes:
acquiring a preset grinding thickness of the test wafer, and sequentially grinding the back of the test wafer according to the preset grinding thickness;
acquiring the number and integrity information of crystal grains bonded on the grinding protective film;
and acquiring first state information of the crystal grains bonded on the grinding protective film according to the number and the integrity information of the crystal grains.
Further, the obtaining of multiple groups of grinding parameters, and grinding the test wafer respectively, and obtaining second state information of the grains bonded on the grinding protection film, wherein the grinding parameters include a grinding rotation speed and a grinding vacuum degree, and the grinding parameters include:
acquiring a plurality of groups of grinding parameters and preset grinding thickness, wherein the grinding parameters comprise grinding rotating speed and grinding vacuum degree;
sequentially grinding the back of the test wafer according to the grinding parameters and the preset grinding thickness;
acquiring the number and integrity information of crystal grains bonded on the grinding protective film;
and acquiring second state information of the crystal grains bonded on the grinding protective film according to the number and the integrity information of the crystal grains.
Optionally, the predetermined milling thickness is 50um-80 um.
Optionally, the grinding rotation speed is 4000r/m-6000r/m, and the grinding vacuum degree is more than 50 Kpa.
Optionally, the pre-cutting operation on the front side of the test wafer further includes:
and forming a protective layer on the front surface of the test wafer.
On the other hand, on the basis of the provided method for optimizing back grinding applied to the small chip, the invention also discloses a device for optimizing back grinding applied to the small chip, which comprises the following steps:
the test wafer acquisition module is used for providing a plurality of groups of test wafers, and each test wafer comprises a front surface formed with an integrated circuit and a back surface corresponding to the front surface;
the first preprocessing module is used for carrying out precutting operation on the front surface, pasting grinding protective films, and pasting different grinding protective films on a plurality of groups of test wafers;
the first state information acquisition module is used for sequentially grinding the back of the test wafer to acquire first state information of crystal grains bonded on the grinding protective film;
a preset grinding protection film determining module, configured to compare the first state information, where a grinding protection film corresponding to the test wafer with the best grain first state information is a preset grinding protection film;
the second preprocessing module is used for providing a plurality of groups of test wafers again, carrying out precutting operation on the front surfaces of the test wafers and attaching the preset grinding protective film;
the second state information acquisition module is used for acquiring a plurality of groups of grinding parameters, respectively grinding the test wafer and acquiring second state information of grains bonded on the grinding protective film, wherein the grinding parameters comprise grinding rotating speed and grinding vacuum degree;
and the preset grinding parameter acquisition module is used for comparing the second state information, wherein the grinding parameter corresponding to the test wafer with the best second state information of the crystal grains is a preset grinding parameter.
By adopting the technical scheme, the back grinding optimization method and device applied to the small chip have the following beneficial effects:
1. according to the method and the device for optimizing the back grinding of the small chip, disclosed by the invention, through reasonable selection of the grinding protective film and grinding parameters, the conditions of crystal flying, crystal cracking and the like in the back grinding process can be reduced, and the back grinding quality is improved.
2. According to the method and the device for optimizing the back grinding of the small chip, disclosed by the invention, a plurality of groups of test data can be tested in an experimental mode, a better result is obtained, and the waste of wafers is avoided.
3. According to the method and the device for optimizing the back grinding of the small chip, disclosed by the invention, as the flying crystal and the cracked crystal are reduced, the damage to a grinding machine is reduced, and the use safety of the grinding machine is ensured.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings used in the description of the embodiment or the prior art will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
FIG. 1 is a schematic representation of the steps of a method of backside grinding optimization for chiplets according to the present invention;
FIG. 2 is a schematic diagram of a backside grinding optimization device for chiplets according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, apparatus, article, or device that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or device.
Example 1
The back thinning of the chip is taken as an important process in the semiconductor later-manufacturing process, the integrated circuit chip can be continuously developed towards high density, high performance, light weight, short and small direction, the chip cracking condition is easy to occur when the back thinning is carried out on the whole wafer, the chip cracking condition when the back thinning of the wafer is effectively solved by the DBG processing technology, but when the chip is small, for example, the chip size is required to be below 1mm, due to the small size of the crystal grain (die), the conditions of chip Fly-die (Fly-die) and chip crack-die (crack-die) and the like can also occur in the grinding process, so that certain potential safety hazards can be generated on grinding machine equipment, and meanwhile, the yield of products can also be reduced.
Firstly, the main process flow for the DBG processing process may be:
(1) half differentiating: half cutting: the wafer is cut to half the depth without the wafer separating.
(2) BG tape playback: and (4) sticking the BG film and sticking a back grinding protective adhesive tape.
(3) Marking: and grinding, namely grinding the back surface of the wafer, wherein the wafer is divided into small blocks and is adhered to the BG film.
(4) UV irradiation: UV light irradiation, UV irradiation, reduce BG tape tackiness.
(5) Mounting: and pasting a trimming tape, pasting the trimming tape on the front surface, and pasting the ring frame on the wafer.
(6) Peeling: tearing the adhesive tape, and tearing away the BG adhesive tape.
(7) And (3) Restore: and pushing out the product, and returning the processed product to the cassette.
(8) And Die bond, wherein the extracted Die is attached to the polar plate and connected by a crystal wire.
(9) Mould: encapsulated into a block, which is a common brown shell outside the pellet.
(10) Test: and (6) testing.
In the embodiments of the present specification, the grinding protection film (i.e., BG film) and the grinding parameters are reasonably optimized in (2) and (3) above, so as to reduce the occurrence of crystal flying and crystal cracking during the grinding process.
Referring to FIG. 1, which is a flow chart illustrating a method for optimizing backside grinding for use in a small chip according to an embodiment of the present invention, the present specification provides the method steps as described in the embodiment or the flow chart, but based on the conventional method; or the inventive process may include additional or fewer steps. The sequence of steps recited in the examples is only one of many steps performed and does not represent a unique order of execution, and the back side grinding optimization method applied to the chiplets can be performed in the order of the method shown in the examples or figures. Specifically, the method comprises the following steps:
s101: providing a plurality of groups of test wafers, wherein each test wafer comprises a front side formed with an integrated circuit and a back side corresponding to the front side;
the test wafer is a chip which is patterned, namely the laying of an integrated circuit is finished, and then the back of the test wafer is thinned according to the chip packaging and testing requirements to meet the preset requirements. To protect the front integrated circuit from the stress during the back grinding process, BG tape is attached to the front of the wafer to protect the front of the wafer.
S103: performing pre-cutting operation on the front surface, attaching grinding protective films, and attaching different grinding protective films to a plurality of groups of test wafers;
for grinding of small chips, a large number of integrated circuits on a wafer need to be divided into individual chips during pre-cutting, the thickness of the cut should be the preset thickness of the chip, so the size and requirements of the chip need to be determined in advance between step S103, and on the basis of the obtained chip size and requirements, the method can further include the following steps:
obtaining a plurality of groups of grinding protective films of different types, wherein each group of grinding protective films comprises a plurality of grinding protective films of different thicknesses.
The abrasion resistance and the adhesiveness of different types of grinding protective films are different, so that the protection capability generated for chips with different sizes and requirements in the grinding process is different, and meanwhile, the grinding protective films with different thicknesses also influence the protection result, so that after the size and the requirements of the chip are determined, a plurality of groups of grinding protective films with different types can be arranged, and each group of grinding protective films can comprise a plurality of grinding protective films with different thicknesses. Illustratively, the abrasive protective film may be selected to be a UV film, which may include different types, such as UV film E-8310, UV film E-3281, and UV film D-210, although other non-UV films or other types of UV films may be selected according to the customer's needs, and is not limited herein. The thickness of each group of grinding protective films can be selected from 100um to 400um, and the thicknesses of each group of grinding protective films can be set to 200um, 300um and 400um optionally, but are not limited thereto.
In some other embodiments, a protective layer may be attached to the front surface of the test wafer before the polishing protective film is attached, so as to further protect the integrated circuits on the front surface of the test wafer.
S105: sequentially grinding the back of the test wafer to obtain first state information of crystal grains bonded on the grinding protective film;
specifically, the same grinding parameters are adopted for grinding each test wafer, so that the protection effect of grinding protective films of different types and thicknesses can be tested, each pre-cut chip forms an individual chip after grinding, therefore, the grinding thickness should be determined firstly before grinding, and thus, excessive or insufficient grinding can be avoided.
In some other embodiments, the step S105 may further include the steps of:
s501: acquiring a preset grinding thickness of the test wafer, and sequentially grinding the back of the test wafer according to the preset grinding thickness;
s503: acquiring the number and integrity information of crystal grains bonded on the grinding protective film;
s505: and acquiring first state information of the crystal grains bonded on the grinding protective film according to the number and the integrity information of the crystal grains.
The crystal grains are chips, and the integrity information of the crystal grains can be the integrity information of the crystal grains adhered to the grinding protective film, so that the falling crystal grains can be avoided from being considered, and in principle, the falling crystal grains have no use value and can be treated as waste products. The complete chip may be a chip without any damage, or a chip with damage but without destroying its effective functional area.
When the first state information is obtained, the number of the dies and the integrity information may be set to a certain specific gravity, for example, the relative weight of the two is 50%, at most 1000 dies may be cut in the test wafer, 900 dies adhered to the polishing protection film after polishing are completed and valid, among which 800 dies are complete, the first state information of the test wafer polished this time is 900 × 50% +800 × 50% + 850, it should be noted that when the first state information is calculated, the same size wafer should be selected, and the chip size is the same, so that the obtained first state information has comparability.
The first state information obtaining method is only one of the embodiments in this specification, and may have other expressions, all of which are within the protection scope of the technical solution of the present application.
S107: comparing the first state information, wherein the grinding protective film corresponding to the test wafer with the best first state information of the crystal grains is a preset grinding protective film;
by the first state information obtaining method, the test wafer with the best first state of the crystal grains can be obtained by comparing the obtained numerical values, for example, three groups of grinding protective films are tested, namely a UV film E-8310, a UV film E-3281 and a UV film D-210; each of the polishing protection films has the same thickness, and the polishing is performed in the same polishing environment, and the obtained polishing protection film with the best state is a preset polishing protection film, it should be noted that, in some other environments, the thickness of the polishing protection film may also affect the polishing result, or different thicknesses may be set for each polishing protection film for comparison, for example, each group includes three thicknesses, which are respectively the UV films E-8310: 200um, 300um and 400 um; UV film E-3281: 200um, 300um and 400 um; UV film D-210: 200um, 300um and 400um, the obtained scores are respectively 800, 1000 and 850; 500. 650, 600; 780, 750, 700; the crystal grains in the best state can be obtained when the UV film E-8310 is 300um, so the crystal grains can be used as a preset grinding protective film.
S109: providing a plurality of groups of test wafers again, performing precutting operation on the front surfaces of the test wafers, and attaching the preset grinding protective film;
on the basis of the determined preset grinding protection film, grinding parameters are required to be optimized, step S101 is repeated, a test wafer having a front surface of the integrated circuit and a back surface corresponding to the front surface is provided, pre-cutting is performed on the test wafer on the premise of obtaining the chip size and the requirements, and the determined preset grinding protection film is attached to the front surface of the test wafer after the pre-cutting is completed.
In some other embodiments, a protective layer may be attached to the front surface of the test wafer before the polishing protective film is attached, so as to further protect the integrated circuits on the front surface of the test wafer.
S111: acquiring a plurality of groups of grinding parameters, respectively grinding the test wafer, and acquiring second state information of crystal grains bonded on the grinding protective film, wherein the grinding parameters comprise grinding rotating speed and grinding vacuum degree;
in the embodiment of the specification, more and better chip quality can be obtained by optimizing the grinding parameters, and the efficiency of the grinding machine can be improved. Specifically, a plurality of sets of grinding parameters, such as grinding rotation speed and grinding vacuum degree, can be set, for example, the grinding rotation speed is 4000r/m-6000r/m, the grinding vacuum degree is more than 50Kpa, and in some other embodiments, grinding time and other parameters can also be selected.
In some other embodiments, the step S111 may include the steps of:
s1101: acquiring a plurality of groups of grinding parameters and preset grinding thickness, wherein the grinding parameters comprise grinding rotating speed and grinding vacuum degree;
s1103: sequentially grinding the back of the test wafer according to the grinding parameters and the preset grinding thickness;
s1105: acquiring the number and integrity information of crystal grains bonded on the grinding protective film;
s1107: and acquiring second state information of the crystal grains bonded on the grinding protective film according to the number and the integrity information of the crystal grains.
The same batch of test wafers which adopt the same operation can be compared with a better group of grinding parameters through different grinding processes, and when the comparison is carried out, the second state information of the crystal grains bonded on the grinding protective film can be selected as the parameters, optionally, the second state information can be obtained in the same obtaining mode as the first state information, and of course, other methods which can realize the comparison of different crystal grain state information can also be selected.
Alternatively, the predetermined polishing thickness is determined according to the thickness of the test wafer and the thickness of the chip, and may be, for example, 50um to 80 um.
S113: and comparing the second state information, wherein the grinding parameter corresponding to the test wafer with the best second state information of the crystal grains is a preset grinding parameter.
The second state information obtained in the above way can be compared to obtain the optimal grinding parameters, for example, the second state information can be obtained by numerical value calculation method with reference to the first state information.
On the basis of the method for optimizing back grinding applied to the small chip, the embodiment of the present specification may further provide an apparatus, where the apparatus may include:
the test wafer acquisition module is used for providing a plurality of groups of test wafers, and each test wafer comprises a front surface formed with an integrated circuit and a back surface corresponding to the front surface;
the first preprocessing module is used for carrying out precutting operation on the front surface, pasting grinding protective films, and pasting different grinding protective films on a plurality of groups of test wafers;
the first state information acquisition module is used for sequentially grinding the back of the test wafer to acquire first state information of crystal grains bonded on the grinding protective film;
a preset grinding protection film determining module, configured to compare the first state information, where a grinding protection film corresponding to the test wafer with the best grain first state information is a preset grinding protection film;
the second preprocessing module is used for providing a plurality of groups of test wafers again, carrying out precutting operation on the front surfaces of the test wafers and attaching the preset grinding protective film;
the second state information acquisition module is used for acquiring a plurality of groups of grinding parameters, respectively grinding the test wafer and acquiring second state information of grains bonded on the grinding protective film, wherein the grinding parameters comprise grinding rotating speed and grinding vacuum degree;
and the preset grinding parameter acquisition module is used for comparing the second state information, wherein the grinding parameter corresponding to the test wafer with the best second state information of the crystal grains is a preset grinding parameter.
By the aid of the device, autonomous operation of back grinding optimization can be achieved, efficiency is improved, and meanwhile, the optimization process is prevented from being influenced by human participation.
The method and the device for optimizing the back grinding applied to the small chip can achieve the following beneficial effects:
1) according to the method and the device for optimizing the back grinding of the small chip, disclosed by the invention, through reasonable selection of the grinding protective film and grinding parameters, the conditions of crystal flying, crystal cracking and the like in the back grinding process can be reduced, and the back grinding quality is improved.
2) According to the method and the device for optimizing the back grinding of the small chip, disclosed by the invention, a plurality of groups of test data can be tested in an experimental mode, a better result is obtained, and the waste of wafers is avoided.
3) According to the method and the device for optimizing the back grinding of the small chip, disclosed by the invention, as the flying crystal and the cracked crystal are reduced, the damage to a grinding machine is reduced, and the use safety of the grinding machine is ensured.
While the invention has been described with reference to specific embodiments, it will be appreciated by those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the invention can be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (10)
1. A back grinding optimization method applied to a small chip is characterized by comprising the following steps:
providing a plurality of groups of test wafers, wherein each test wafer comprises a front side formed with an integrated circuit and a back side corresponding to the front side;
performing pre-cutting operation on the front surface, attaching grinding protective films, and attaching different grinding protective films to a plurality of groups of test wafers;
sequentially grinding the back of the test wafer to obtain first state information of crystal grains bonded on the grinding protective film;
comparing the first state information, wherein the grinding protective film corresponding to the test wafer with the best first state information of the crystal grains is a preset grinding protective film;
providing a plurality of groups of test wafers again, performing precutting operation on the front surfaces of the test wafers, and attaching the preset grinding protective film;
acquiring a plurality of groups of grinding parameters, respectively grinding the test wafer, and acquiring second state information of crystal grains bonded on the grinding protective film, wherein the grinding parameters comprise grinding rotating speed and grinding vacuum degree;
and comparing the second state information, wherein the grinding parameter corresponding to the test wafer with the best second state information of the crystal grains is a preset grinding parameter.
2. The method of claim 1, wherein the pre-cutting operation is performed on the front side and a polishing protection film is attached, and wherein the step of attaching different polishing protection films to the plurality of groups of test wafers further comprises:
obtaining a plurality of groups of grinding protective films of different types, wherein each group of grinding protective films comprises a plurality of grinding protective films of different thicknesses.
3. The method of claim 1, wherein attaching different polishing protective films to the plurality of groups of test wafers comprises:
and different types of grinding protective films are attached to a plurality of groups of test wafers, wherein each group of test wafers comprises a plurality of test wafers, and the plurality of test wafers are attached with the grinding protective films with different thicknesses.
4. The method of claim 2, wherein the polishing protection film comprises a UV film E-8310, a UV film E-3281 and a UV film D-210, and the polishing protection film has a thickness of 100um to 400 um.
5. The method of claim 1, wherein the sequentially polishing the back side of the test wafer to obtain the first state information of the die bonded to the polishing protection film comprises:
acquiring a preset grinding thickness of the test wafer, and sequentially grinding the back of the test wafer according to the preset grinding thickness;
acquiring the number and integrity information of crystal grains bonded on the grinding protective film;
and acquiring first state information of the crystal grains bonded on the grinding protective film according to the number and the integrity information of the crystal grains.
6. The method of claim 1, wherein the obtaining a plurality of sets of polishing parameters and polishing the test wafer respectively to obtain second state information of the die bonded to the polishing protection film comprises:
acquiring a plurality of groups of grinding parameters and preset grinding thickness, wherein the grinding parameters comprise grinding rotating speed and grinding vacuum degree;
sequentially grinding the back of the test wafer according to the grinding parameters and the preset grinding thickness;
acquiring the number and integrity information of crystal grains bonded on the grinding protective film;
and acquiring second state information of the crystal grains bonded on the grinding protective film according to the number and the integrity information of the crystal grains.
7. The method of claim 5 or 6, wherein the predetermined polishing thickness is between 50um and 80 um.
8. The method of claim 6, wherein the grinding speed is 4000 rpm to 6000 rpm and the grinding vacuum is greater than 50 Kpa.
9. The method of claim 1, further comprising, after the pre-cutting operation performed on the front side of the test wafer:
and forming a protective layer on the front surface of the test wafer.
10. A backgrinding optimization device for use with chiplets, the device comprising:
the test wafer acquisition module is used for providing a plurality of groups of test wafers, and each test wafer comprises a front surface formed with an integrated circuit and a back surface corresponding to the front surface;
the first preprocessing module is used for carrying out precutting operation on the front surface, pasting grinding protective films, and pasting different grinding protective films on a plurality of groups of test wafers;
the first state information acquisition module is used for sequentially grinding the back of the test wafer to acquire first state information of crystal grains bonded on the grinding protective film;
a preset grinding protection film determining module, configured to compare the first state information, where a grinding protection film corresponding to the test wafer with the best grain first state information is a preset grinding protection film;
the second preprocessing module is used for providing a plurality of groups of test wafers again, carrying out precutting operation on the front surfaces of the test wafers and attaching the preset grinding protective film;
the second state information acquisition module is used for acquiring a plurality of groups of grinding parameters, respectively grinding the test wafer and acquiring second state information of grains bonded on the grinding protective film, wherein the grinding parameters comprise grinding rotating speed and grinding vacuum degree;
and the preset grinding parameter acquisition module is used for comparing the second state information, wherein the grinding parameter corresponding to the test wafer with the best second state information of the crystal grains is a preset grinding parameter.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5599423A (en) * | 1995-06-30 | 1997-02-04 | Applied Materials, Inc. | Apparatus and method for simulating and optimizing a chemical mechanical polishing system |
| US20010000773A1 (en) * | 1999-08-11 | 2001-05-03 | Advanced Micro Devices, Inc. | Method for determining a polishing recipe based upon the measured pre-polish thickness of a process layer |
| TW495414B (en) * | 1999-10-12 | 2002-07-21 | Applied Materials Inc | Method of controlling a polishing machine |
| JP2012228745A (en) * | 2011-04-26 | 2012-11-22 | Sumco Corp | Polishing apparatus and polishing method |
| CN103441103A (en) * | 2013-08-29 | 2013-12-11 | 华进半导体封装先导技术研发中心有限公司 | Wafer cutting method |
| CN106716603A (en) * | 2015-09-15 | 2017-05-24 | 古河电气工业株式会社 | Adhesive tape for protecting semiconductor wafer surface |
| CN109742017A (en) * | 2019-01-25 | 2019-05-10 | 北京半导体专用设备研究所（中国电子科技集团公司第四十五研究所） | Wafer reduction process |
| CN110024102A (en) * | 2019-02-26 | 2019-07-16 | 长江存储科技有限责任公司 | For the method and apparatus in crystal column surface patch adhesive film |
-
2020
- 2020-06-18 CN CN202010559436.XA patent/CN111883448B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5599423A (en) * | 1995-06-30 | 1997-02-04 | Applied Materials, Inc. | Apparatus and method for simulating and optimizing a chemical mechanical polishing system |
| US20010000773A1 (en) * | 1999-08-11 | 2001-05-03 | Advanced Micro Devices, Inc. | Method for determining a polishing recipe based upon the measured pre-polish thickness of a process layer |
| TW495414B (en) * | 1999-10-12 | 2002-07-21 | Applied Materials Inc | Method of controlling a polishing machine |
| US6439964B1 (en) * | 1999-10-12 | 2002-08-27 | Applied Materials, Inc. | Method of controlling a polishing machine |
| JP2012228745A (en) * | 2011-04-26 | 2012-11-22 | Sumco Corp | Polishing apparatus and polishing method |
| CN103441103A (en) * | 2013-08-29 | 2013-12-11 | 华进半导体封装先导技术研发中心有限公司 | Wafer cutting method |
| CN106716603A (en) * | 2015-09-15 | 2017-05-24 | 古河电气工业株式会社 | Adhesive tape for protecting semiconductor wafer surface |
| CN109742017A (en) * | 2019-01-25 | 2019-05-10 | 北京半导体专用设备研究所（中国电子科技集团公司第四十五研究所） | Wafer reduction process |
| CN110024102A (en) * | 2019-02-26 | 2019-07-16 | 长江存储科技有限责任公司 | For the method and apparatus in crystal column surface patch adhesive film |
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