CN111879999A - A Low Temperature Coefficient Fast Voltage Detection Circuit - Google Patents

Abstract

The invention discloses a low temperature coefficient fast voltage detection circuit applied in the field of energy collection. The voltage detection circuit includes a CTAT bias circuit, a positive feedback bias circuit and a voltage detection circuit; the power supply voltage is the input signal terminal (V _in ) , the overall output signal terminal (V _out ) of the circuit; the output terminal (V _bias ) of the CTAT bias circuit is connected to the input terminal of the voltage detection circuit, and the output terminal of the voltage detection circuit is the overall output signal terminal (V _out ) of the circuit and the positive feedback bias connected to the input of the circuit. The voltage detection circuit is composed of two cascode MOS tubes. When the pull-up network current and the pull-down network current are equal, the detection voltage is reached. The upper detection tube of the voltage detection circuit is biased by the CTAT reference circuit, thereby reducing the influence of temperature on the detection voltage value. The lower detection tube of the voltage detection circuit is biased by the positive feedback bias circuit, and when the detection voltage is reached, the current of the pull-down network is reduced through the feedback network, thereby accelerating the establishment of the trigger signal at the output end.

Description

A Low Temperature Coefficient Fast Voltage Detection Circuit

technical field

The invention belongs to the field of energy collection, and particularly relates to a voltage detection circuit capable of realizing low temperature coefficient and fast speed.

Background technique

With the development of Internet of Things technology, obtaining energy from the environment to power devices is an important research direction at present. The energy harvesting circuit converts the voltage generated by the energy source to the voltage value required by the system through the conversion circuit. Since changes in the environment will cause the voltage value generated by the energy source to fluctuate, in order to stabilize the output voltage of the energy harvesting system, it is necessary to detect the input or output voltage. Since the power generated by the energy source is generally low, the power consumption of each module in the energy harvesting circuit needs to be minimized. In addition, the working environment of IoT nodes is complex, so the voltage detection circuit needs to have good temperature isolation, so that the detection voltage is not affected by temperature. In addition, the fast response of the voltage detection circuit is conducive to maintaining the stability of the output voltage of the energy harvesting system, so the present invention provides a low temperature coefficient and fast voltage detection circuit.

Usually, a bandgap reference (BGR) and a comparator are used to detect the voltage. Because the bandgap reference circuit operates at a relatively high voltage and uses a DC bias resistor, it consumes a lot of power. The energy harvesting circuit generally needs to work at low voltage and low power consumption. Some people propose a voltage detection circuit composed of two MOS tubes with a cascode structure. The detection voltage is determined by comparing the current of the pull-up network and the current of the pull-down network. The current of the pull-up network increases with the increase of the input voltage, and the current of the pull-down network remains unchanged. Different detection voltages can be achieved by setting the width to length ratio of the MOS tube. However, this method requires a very large aspect ratio, and the detection voltage value will increase with the increase of temperature, resulting in a large deviation of the voltage detection results in different environments, and when the input voltage is relatively close to the detection voltage , the trigger signal at the output is very slow to build up. Therefore, the present invention proposes a low temperature coefficient and fast voltage detection circuit. The main idea of the design is to realize the low temperature coefficient of the detection voltage by providing the upper detection tube with a bias with a temperature coefficient; to reduce the current of the pull-down network through feedback, and to speed up the Trigger the establishment of the signal.

SUMMARY OF THE INVENTION

Technical problem: The purpose of the present invention is to propose a low temperature coefficient fast voltage detection circuit applied to an energy harvesting circuit. As the basic unit of an analog circuit, the circuit can realize voltage detection in different environments.

Technical solution: In order to solve the above technical problems, a low temperature coefficient fast voltage detection circuit of the present invention adopts the following technical solutions:

The voltage detection circuit includes a CTAT bias circuit, a positive feedback bias circuit and a voltage detection circuit; the power supply voltage is the input signal terminal, the overall output signal terminal of the circuit; the CTAT (complementary to absolute temperature, CTAT) bias circuit The output terminal is connected to the input terminal of the voltage detection circuit, and the output terminal of the voltage detection circuit, that is, the overall output signal terminal of the circuit, is connected to the input terminal of the positive feedback bias circuit.

The CTAT bias circuit part consists of a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor; the positive feedback bias circuit consists of a sixth transistor and a seventh transistor; the voltage detection circuit part consists of The cascaded eighth transistor and the ninth transistor are formed.

The first transistor, the second transistor, and the eighth transistor are PMOS transistors, and the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the ninth transistor are NMOS transistors.

The fifth transistor is a thick-gate NMOS transistor with a higher threshold voltage.

In the CTAT bias circuit, the source of the first transistor is connected to the power supply voltage, that is, the input signal terminal, the gate of the first transistor is respectively connected to the drain of the first transistor and the gate of the second transistor, and the drain of the first transistor is connected to the gate of the second transistor. The electrode of the second transistor is connected to the drain of the third transistor; the source of the second transistor is connected to the power supply voltage, that is, the input signal terminal, and the drain of the second transistor is connected to the drain of the fourth transistor to form the output end of the CTAT bias circuit; the fourth transistor The gate of the fourth transistor is connected to the drain of the fourth transistor and the gate of the fifth transistor, the source of the fourth transistor is connected to the drain of the fifth transistor and connected to the gate of the third transistor to provide the gate of the third transistor Bias; the drains of the fifth and third transistors are grounded.

In the described positive feedback bias circuit, the drain of the sixth transistor is connected to the power supply voltage, that is, the input signal terminal, the gate of the sixth transistor is connected to the source stage, and the source stage of the sixth transistor is connected to the gate of the seventh transistor; The source of the seventh transistor is grounded.

The voltage detection circuit part is composed of an eighth transistor and a ninth transistor, the source stage of the eighth transistor is connected to the power supply voltage, that is, the input signal terminal, and the gate of the eighth transistor is connected to the output terminal of the CTAT bias circuit; The drain of the transistor and the drain of the ninth transistor are connected to form the overall output signal end of the circuit, and the overall output signal end of the circuit is connected to the gate of the seventh transistor in the positive feedback bias circuit; the gate of the ninth transistor is connected to the positive feedback The gates of the sixth transistor in the bias circuit are connected to form a positive feedback loop, and the source stage of the ninth transistor is grounded.

Beneficial effect: Compared with the existing technology, the present invention has the following advantages:

The CTAT reference circuit provides a bias for the upper detection tube of the voltage detection circuit, thereby reducing the influence of temperature on the detection voltage value and realizing a low temperature coefficient of the detection voltage. The lower detection tube of the voltage detection circuit is biased by the positive feedback bias circuit, and when the detection voltage is reached, the current of the pull-down network is reduced through the feedback network, thereby accelerating the establishment of the trigger signal at the output end.

Description of drawings

1 is a circuit topology diagram of the present invention;

FIG. 2 is a graph showing the relationship between the input voltage and the output voltage of the low temperature coefficient fast voltage detection circuit realized by the present invention at different temperatures (-20°C-80°C).

3 is a partial enlarged view of the relationship between the input voltage and the output voltage of the low temperature coefficient fast voltage detection circuit realized by the present invention at different temperatures (-20°C-80°C).

FIG. 4 is the relationship curve between the detection voltage V _detect and the temperature of the low temperature coefficient fast voltage detection circuit realized by the present invention.

FIG. 5 is the transient characteristic curve of the low temperature coefficient fast voltage detection circuit realized by the present invention.

There are: first transistor M1, second transistor M2, third transistor M3, fourth transistor M4, fifth transistor M5, sixth transistor M6, seventh transistor M7, eighth transistor M8, ninth transistor M9; power supply The voltage is the input signal terminal V _in , the output terminal V _bias of the CTAT bias circuit, and the overall output signal terminal V _out of the circuit.

Detailed ways

The present invention will be further described below with reference to the accompanying drawings.

The low temperature coefficient fast voltage detection circuit of the present invention is composed of a CTAT bias circuit, a positive feedback bias circuit and a voltage detection circuit.

The power supply voltage and input signal of the circuit are V _in , and the overall output signal of the circuit is V _out .

The voltage detection circuit part consists of the cascaded eighth transistor M8 and the ninth transistor M9, and the CTAT bias circuit part consists of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, and the fifth transistor M5. , the positive feedback bias circuit is composed of the sixth transistor M6 and the seventh transistor M7, wherein the first transistor M1, the second transistor M2 and the eighth transistor M8 are PMOS, the third transistor M3, the fourth transistor M4 and the fifth transistor M5 , the sixth transistor M6, the seventh transistor M7, and the ninth transistor M9 are NMOS, wherein the fifth transistor M5 is a thick-gate NMOS transistor with a higher threshold voltage.

The _CTAT bias circuit is composed of a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a fifth transistor M5. The gate of a transistor M1 is connected to the drain of the first transistor M1 and the gate of the second transistor M2 respectively, the drain of the first transistor M1 is connected to the drain of the third transistor M3; the source of the second transistor M2 is connected to The power supply voltage is the input signal terminal V _in , the drain of the second transistor M2 is connected to the drain of the fourth transistor M4 to form the output terminal V _bias of the CTAT bias circuit; the gate of the fourth transistor M4 is connected to the drain of the fourth transistor M4 and the gate of the fifth transistor M5, the source stage of the fourth transistor M4 is connected to the drain of the fifth transistor M5, and provides a bias for the gate of the third transistor M3, and is connected to the gate of the third transistor; The drains of the three transistors M5 and the third transistor M3 are grounded.

The positive feedback bias circuit is composed of a sixth transistor M6 and a seventh transistor M7. The drain of the sixth transistor M6 is connected to the supply voltage, that is, the input signal terminal V _in , the gate of the sixth transistor M6 is connected to the source, and the sixth transistor M6 is connected to the source stage. The source stage of M6 is connected to the gate of the seventh transistor M7; the source stage of the seventh transistor M7 is grounded. The voltage detection circuit part is composed of an eighth transistor M8 and a ninth transistor M9. The source stage of the eighth transistor M8 is connected to the power supply voltage, that is, the input signal terminal V _in , and the gate of the eighth transistor M8 is connected to the CTAT bias output V _bias , The drain of the eighth transistor M8 and the drain of the ninth transistor M9 are connected to form the output terminal V _out of the overall circuit, and at the same time the output terminal is connected to the gate of the seventh transistor M7 in the positive feedback bias circuit; The gate is connected to the gate of the sixth transistor M6 in the positive feedback bias circuit to form a positive feedback loop, and the source of the ninth transistor M9 is grounded.

The invention proposes that the CTAT reference circuit provides bias for the upper detection tube of the voltage detection circuit, thereby reducing the influence of temperature on the detection voltage value and realizing a low temperature coefficient of the detection voltage. The lower detection tube of the voltage detection circuit is biased by the positive feedback bias circuit, and when the detection voltage is reached, the current of the pull-down network is reduced through the feedback network, thereby accelerating the establishment of the trigger signal at the output end. The working principle is described in detail below in conjunction with the specific circuit and simulation results.

As shown in FIG. 1, in the structure proposed by the present invention, the voltage detection circuit is composed of a PMOS eighth transistor M8 and an NMOS ninth transistor M9 in cascade connection, and the gate of the eighth transistor M8 is connected to the output terminal V _bias of the CTAT bias circuit. The gate of the ninth transistor M9 is connected to the _Vx node of the positive feedback bias circuit. The detection voltage value V _detect is defined as the input power supply voltage that changes the voltage of the output terminal V _out of the voltage detection circuit from low to high, that is, the value of the input signal terminal V _in . At this time, the current of the pull-up network is the current I _M8 flowing through the eighth transistor M8. Equal to the current I _M9 of the pull-down network, the eighth transistor M8 and the ninth transistor M9 work in the sub-threshold region. Assuming that V _ds >100mV, according to the expression of the current in the sub-threshold region, Equation 1 can be obtained:

where μ ₈ , μ ₉ represent the mobility of the eighth transistor M8 and the ninth transistor M9 , C _ox represents the oxide capacitance per unit area, m ₈ , m ₉ represent the sub-threshold slope factor of the eighth transistor M8 and the ninth transistor M9 , V _T represents the thermal voltage, its value is proportional to the absolute temperature, (W/L) ₈ , (W/L) ₉ represents the aspect ratio of M8, M9, V _th8 , V _th9 represent the eighth transistor M8, the ninth The threshold voltage of the transistor M9, V _detect represents the detection voltage value, V _bias represents the bias voltage provided by the CTAT bias circuit output for the gate of the eighth transistor M8, and V _x represents the positive feedback bias circuit provided for the gate of the ninth transistor M9 the bias voltage.

Assuming that the sub-threshold slope factors and the threshold voltages of the eighth transistor M8 and the ninth transistor M9 are approximately equal, that is, m=m ₈ =m ₉ , V _th8 =V _th9 , the expression of the detection voltage value V _detect can be obtained by simplification as the formula 2:

与绝对温度成正比，通过调整V_bias和V_x来实现正负温度系数相抵消，可以实现V_detect的低温度系数。where a temperature-dependent term is included in the V _detect expression, where

It is proportional to the absolute temperature. By adjusting V _bias and V _x to realize the cancellation of the positive and negative temperature coefficients, a low temperature coefficient of V _detect can be achieved.

The positive feedback bias circuit is composed of the sixth transistor M6 and the seventh transistor M7. When V _in <V _detect , V _out is close to 0. At this time, the sixth transistor M6 and the seventh transistor M7 have V _gs =0, so V The voltage at point _x is divided by the sixth transistor M6 and the seventh transistor M7. By setting the width to length ratio of the sixth transistor M6 and the seventh transistor M7, the divided voltage value of the V _x point can be set. When V _in >V _detect , the voltage of V _out will gradually rise to V _in , so that the V _gs of the seventh transistor M7 increases, the potential of the V _x point decreases, and the V _gs of the ninth transistor M9 is reduced, so that the voltage The current of the pull-down network of the detection branch is reduced, the speed of the voltage rise of the output terminal V _out is accelerated, and the establishment of the trigger signal is accelerated.

The CTAT bias circuit is composed of a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a fifth transistor M5. The fourth transistor M4 and the fifth transistor M5 work in the sub-threshold region, wherein the fifth transistor M5 is a MOS transistor with a high threshold voltage. In order to make the circuit work at the lowest possible current, the bias current passes through the feedback path from the output voltage V _y to provide bias for the third transistor M3 to form a self-bias structure. The V _y point bias voltage is shown in Equation 3:

Wherein V _gs4 , V _gs5 represent the gate-source voltages of the fourth transistor M4 and the fifth transistor M5 respectively, V _th4 , V _th5 represent the threshold voltages of the fourth transistor M4 and the fifth transistor M5 respectively, m represents the sub-threshold slope factor, μ ₄ and μ ₅ respectively represent the mobility of the fourth transistor M4 and the fifth transistor M5, and (W/L) ₄ and (W/L) ₅ respectively represent the width to length ratio of the fourth transistor M4 and the fifth transistor M5.

The first transistor M1 and the second transistor M2 form a current mirror, copy the current determined by the self-bias to the branch of the second transistor M2, and the bias output voltage V _bias is the gate of the fourth transistor M4 and the fifth transistor M5 voltage, as shown in Equation 4:

Wherein I _M5 represents the current flowing through the fifth transistor M5. The threshold voltage V _th5 of the fifth transistor M5 decreases as the temperature increases, which is a negative temperature coefficient. In the second term of formula 4, a positive temperature coefficient or a negative temperature coefficient can be achieved by adjusting the width-length ratio of the fifth transistor M5. In this application, the required CTAT bias voltage can be obtained by adjusting the aspect ratio of the fifth transistor M5. The temperature coefficient of the temperature-related term in the expression of the detection voltage V _detect is cancelled out to achieve a low temperature coefficient of the detection voltage. The CTAT bias circuit works in the sub-threshold region and can work normally at low voltages.

Fig. 2 is the relation curve between the input voltage and the output voltage of the low temperature coefficient fast voltage detection circuit realized by the present invention at different temperatures (-20°C-80°C). The voltage varies little with temperature.

3 is a partial enlarged view of the relationship between the input voltage and the output voltage of the low temperature coefficient fast voltage detection circuit realized by the present invention at different temperatures (-20°C-80°C). Between 546.5mV-548.5mV.

FIG. 4 is the relationship curve between the detection voltage V _detect and the temperature of the low temperature coefficient fast voltage detection circuit realized by the present invention, and the temperature coefficient of the detection voltage realized by the present invention is 0.016mV/°C.

Fig. 5 is the transient characteristic curve of the low temperature coefficient fast voltage detection circuit realized by the present invention, when the detection voltage V _detect is 547.5mV, and the power supply voltage, that is, the input signal terminal V _in is 550mV, the output voltage V _out rises after 0.2ms to V _in .

The above descriptions are only the preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, but any equivalent modifications or changes made by those of ordinary skill in the art based on the contents disclosed in the present invention should be included in the within the scope of protection described in the claims.

Claims (7)

1. A low temperature coefficient fast voltage detection circuit, characterized in that the voltage detection circuit comprises a CTAT bias circuit, a positive feedback bias circuit and a voltage detection circuit; the power supply voltage is the input signal terminal (V _in ), and the overall output signal of the circuit terminal (V _out ); the output terminal (V _bias ) of the CTAT bias circuit is connected to the input terminal of the voltage detection circuit, and the output terminal of the voltage detection circuit is the overall output signal terminal (V _out ) of the circuit and the input terminal of the positive feedback bias circuit connected. 2. A low temperature coefficient fast voltage detection circuit according to claim 1, wherein the CTAT bias circuit is partially composed of a first transistor (M1), a second transistor (M2), a third transistor ( M3), the fourth transistor (M4), the fifth transistor (M5); the positive feedback bias circuit is composed of the sixth transistor (M6) and the seventh transistor (M7); the voltage detection circuit part is composed of the cascaded eighth transistor (M8) and a ninth transistor (M9). 3. A low temperature coefficient fast voltage detection circuit according to claim 1, wherein the first transistor (M1), the second transistor (M2), and the eighth transistor (M8) are PMOS transistors, The third transistor (M3), the fourth transistor (M4), the fifth transistor (M5), the sixth transistor (M6), the seventh transistor (M7), and the ninth transistor (M9) are NMOS transistors. 4 . The low temperature coefficient fast voltage detection circuit according to claim 3 , wherein the fifth transistor ( M5 ) is a thick gate NMOS transistor with a higher threshold voltage. 5 . 5. A low temperature coefficient fast voltage detection circuit according to claim 2, characterized in that, in the CTAT bias circuit, the source of the first transistor (M1) is connected to the power supply voltage, that is, the input signal terminal (V _in ), the gate of the first transistor (M1) is connected to the drain of the first transistor (M1) and the gate of the second transistor (M2) respectively, and the drain of the first transistor (M1) is connected to the third transistor (M3) The drain of the second transistor (M2) is connected to the power supply voltage, that is, the input signal terminal (V _in ), and the drain of the second transistor (M2) is connected to the drain of the fourth transistor (M4) to form CTAT bias The output terminal (V _bias ) of the circuit; the gate of the fourth transistor (M4) is connected to the drain of the fourth transistor (M4) and the gate of the fifth transistor (M5), and the source of the fourth transistor (M4) is connected to The drain of the fifth transistor (M5) is connected to the gate of the third transistor (M3) to provide bias for the gate of the third transistor (M3). Drain is grounded. 6. A low temperature coefficient fast voltage detection circuit according to claim 2, characterized in that, in the positive feedback bias circuit, the drain of the sixth transistor (M6) is connected to the power supply voltage, that is, the input signal terminal (V _in ), the gate of the sixth transistor (M6) is connected to the source, the source of the sixth transistor (M6) is connected to the gate of the seventh transistor (M7), and the source of the seventh transistor (M7) is grounded. 7. A low temperature coefficient fast voltage detection circuit according to claim 2, wherein the voltage detection circuit part is composed of an eighth transistor (M8) and a ninth transistor (M9), and the eighth transistor ( The source stage of M8) is connected to the power supply voltage, that is, the input signal terminal (V _in ), the gate of the eighth transistor (M8) is connected to the output terminal (V _bias ) of the CTAT bias circuit, the drain of the eighth transistor (M8) and the The drain of the ninth transistor (M9) is connected to form the overall output signal terminal (V _out ) of the circuit, and the overall output signal terminal (V _out ) of the circuit is connected to the gate of the seventh transistor (M7) in the positive feedback bias circuit; The gate of the ninth transistor (M9) is connected to the gate of the sixth transistor (M6) in the positive feedback bias circuit to form a positive feedback loop, and the source of the ninth transistor (M9) is grounded.

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