CN111866930B

CN111866930B - Radio frequency signal detection method and system based on machine learning

Info

Publication number: CN111866930B
Application number: CN202010707218.6A
Authority: CN
Inventors: 彭瑶; 李荔垚; 王俊; 徐鹏; 方鹏飞; 陈晓江; 赵宇航; 房鼎益
Original assignee: Northwest University
Current assignee: Northwest University
Priority date: 2020-07-21
Filing date: 2020-07-21
Publication date: 2022-02-25
Anticipated expiration: 2040-07-21
Also published as: CN111866930A

Abstract

The invention relates to a radio frequency signal detection method and a radio frequency signal detection system based on machine learning. The specific system implementation comprises that an antenna and a matching unit receive a signal to be detected, an input signal is subjected to analog-to-digital and serial-to-parallel conversion, and the input signal is judged by a neural network and then is output after parallel-to-serial conversion. The neural network with specific application is manufactured by pre-analyzing specific scenes, so that the size of the neural network is reduced, the minimum topology capable of working is found by reducing the weight of the neural network, the radio frequency signal to be detected can be detected under the condition of low signal-to-noise ratio with lower hardware power consumption, and the farthest detection distance can reach hundreds of meters at present.

Description

Radio frequency signal detection method and system based on machine learning

Technical Field

The invention belongs to the technical field of radio frequency detection, and particularly relates to a radio frequency signal detection method and system based on Machine Learning (ML).

Background

Existing backscatter techniques lack sensitive packet detection mechanisms, such as transmitting data stimulated by an ambient LoRa signal. To achieve this goal, it needs to detect the ambient LoRa signal from other signals in the same ISM band and then synchronize with the LoRa chirp for fine-grained signal modulation, but conventional signal detection techniques all have their inherent drawbacks.

The traditional signal detection technology mainly has three categories, namely energy detection, matched filtering detection and cyclostationary feature detection.

The energy detection is a detection method based on signal energy, and is characterized by simplicity and no need of any prior knowledge. The general detection process is to integrate by time slot after passing through a band-pass filter, and then compare the integrated value with a preset threshold value to judge whether a signal exists. This method, although easy to implement, has a number of drawbacks. 1. The detection effect is greatly influenced by environmental noise; 2. the energy detection mode cannot distinguish different types of signals; 3. energy detection is not detectable for spread spectrum signals.

The matched filtering mode is to maximize the input signal-to-noise ratio by adding a matched filter with priori knowledge, thereby improving the detection effect and reducing the detection time. The method has the main defects that the priori knowledge of the signal to be detected needs to be acquired in a certain time, meanwhile, the influence of the priori knowledge is large, once the priori knowledge is inaccurate, the detection performance becomes very poor, and the matched filtering algorithm is complex and high in power consumption, so that the method is not suitable for a low-power-consumption system.

Cyclostationary feature detection uses the periodicity of a signal to determine whether the signal is present, and detects the presence of the signal by periodic statistics or spectral features. Cyclostationary feature detection has relatively strong detection accuracy, but has high computational complexity and overlong sensing time, so the cyclostationary feature detection is not frequently used.

With the development of artificial intelligence and deep learning in recent years, signal detection systems based on deep learning and feature extraction are also gradually emerging. The signal detection system based on deep learning obtains a predicted value through extracting instantaneous characteristic information of a signal, high-order cumulant of the signal, circulation stability characteristic of the signal and the like through a trained deep neural network model, and then compares the predicted value with a reference value to detect the signal. The method is mainly characterized by high detection precision and better model capable of identifying more kinds of signals. But the main disadvantage is the need to acquire more transient or stationary periodic features as inputs to the neural network; when the neural network model is not well trained, the detection effect may also be degraded.

In summary, the existing methods mainly have the following three problems: 1. the detection effect is poor; 2. the calculation complexity is high; 3. more a priori knowledge needs to be extracted. These problems result in existing signal detection modules typically having more hardware module units, resulting in higher power consumption overhead.

Disclosure of Invention

In view of the above disadvantages of the prior art, the present invention provides a method and a system for detecting a radio frequency signal based on Machine Learning (ML), which, in view of the problems of the prior art, implement a relatively accurate signal detection function with fewer hardware modules.

Another objective of the present invention is to provide a method and a system for detecting radio frequency signals based on machine learning, in which the voltage characteristics of the signals to be detected are used as the input of a deep neural network, no additional device is required to obtain transient characteristics and stationary periodic characteristics, and the data processing is simple and easy to implement.

The invention further aims to provide a radio frequency signal detection method and system based on machine learning, and the method and system perform model optimization on the trained model through pruning, activating substitution and other modes, so that the size of the neural network model is further reduced, and the detection efficiency is improved.

The invention further aims to provide a radio frequency signal detection method and system based on machine learning, the method and system can be used for manufacturing a neural network for specific application by pre-analyzing specific scenes, so that the size of the neural network is reduced, and the minimum topology capable of working of the neural network is searched by reducing the weight of the neural network, so that the hardware power consumption is reduced.

The invention is realized by the following steps:

a radio frequency signal detection method based on machine learning comprises the following steps:

step 1: determining the communication environment of a signal to be detected, collecting the frequency band, the bandwidth, the modulation mode, the type of a transmitter and a receiver, the state information of a communication channel and the noise condition of the detected signal, and manufacturing a neural network training set;

step 2: constructing a neural network architecture, training a minimized neural network model by using a PC (personal computer) offline, training the specific neural network model for a specific application scene, pruning the number of units in the system from a dense network, and continuously optimizing the neural network model until a minimized topological structure and minimized and simplest computing units are obtained, so that the balance of a minimized network structure and a maximized detection effect is achieved;

and step 3: adjusting the weight and the bias of the neural network parameters according to the performance of the neural network, and saving the activation step under the condition of not influencing the network function;

and 4, step 4: and converting the trained weight and bias into a verilog format grammar, and embedding the verilog format grammar into a radio frequency signal detection hardware system for radio frequency signal detection.

In step 2, the step of training the minimized neural network model offline by using the PC to obtain the minimized network structure includes: selection of a neural network model, selection of input data, selection of an activation model, minimization of input data size, minimization of neural network topology.

Further, the selection of the neural network model is a DNN neural network structure, and the DNN neural network is composed of an input layer, a hidden layer and an output layer;

the input data selection comprises that input data uses a voltage value received by an ADC (analog to digital converter), a hidden layer is a certain number of neurons, each neuron performs multiplication accumulation of weight and output, the output of each layer is used as the input of the next layer after nonlinear operation of an activation model until the output is transmitted to an output layer, and the output is used as the final data output;

the activation model selects data in a ReLU format to reduce the overhead of an embedded system for realizing nonlinear operation;

so that the amount of input data is minimal: because the accuracy of the network model is positively correlated with the size of input data, an input data sorting list from small to large is designed, the input is selected as the maximum value of the sorting list in the first training, the feasibility of the network is tested, and after the test is feasible, the neural network is tested by using a dichotomy until the minimum neural network input is found;

minimizing the neural network topology: presetting a list of hidden layer numbers, a list of neuron numbers and a list of blocksize sizes; when the method is used, the model is trained from the minimum value in the list, each parameter is trained for more than 20 times, the effect of the neural network is tested after the network is trained for each time, and the model is the minimized neural network model until the model meeting the test standard appears.

In step 3, the technical process of adjusting the weight and the bias of the neural network parameters according to the performance of the neural network includes: the decimal storage in the weight is removed by integrally expanding and rounding the weight, so that the difficulty of decimal storage and decimal calculation in an embedded system is reduced; modifying the weight according to the reserved calculation bit width and calculation precision in the embedded system, and converting the weight into a numerical value which can be expressed in the embedded system; the output of the neural network is limited to a specific range through the modification of the bias, so that the judgment difficulty of the embedded system is reduced.

A machine learning based radio frequency signal detection system, comprising:

the antenna and impedance matching unit consists of a source antenna and an impedance matching module and is used for receiving an analog signal in the air, amplifying the analog signal in a low-voltage power supply mode by using a low-power consumption transistor and then transmitting the amplified signal to an ADC (analog-to-digital converter) circuit at the rear end;

the source antenna of the ADC circuit receives an analog signal in the air, the ADC performs sampling and analog-to-digital conversion, and the analog signal is transmitted to the back-end circuit in a digital string mode;

and the neural network detection module consists of an FPGA and a matched circuit and is used for processing and analyzing the data sampled by the ADC.

Further, the antenna and impedance matching unit includes: the source antenna is an antenna which utilizes a 915MHz frequency band to receive LoRa signals and RFID signals, and the impedance matching module is an LC impedance matching circuit designed according to frequency so as to ensure that more sending signals are received and a back-end circuit can detect the signals. However, the method of the present invention is not only suitable for 915MHz, but also can cover other RF frequency bands; not only suitable for LoRa and RFID signals, but also for NBIoT, Sigfox, ZigBee, Bluetooth, WiFi and LTE and 5G signal clusters. But the size of the sample pool of the signals to be acquired, the number of layers of the network and the volume of the computing unit are determined by specific applications.

Further, the ADC circuit comprises a driver, a filter circuit and an analog-to-digital converter, RF signals received by the antenna and the impedance matching module pass through the impedance matching circuit, pass through the filter circuit and are amplified by the extremely low power consumption device, and then the signals are transmitted to the analog-to-digital converter to output 12-bit effective data.

The neural network detection module comprises an FPGA neural network, and the FPGA neural network comprises: a data input portion, a serial-to-parallel converter, a normalization portion, a first layer of neurons, an activation portion, a second layer of neurons, and a parallel-to-serial converter.

Furthermore, the data input part is composed of an ADC and a cascade D trigger group, the ADC is used for converting the collected analog signals into digital signals, and the D triggers are in a cascade mode to buffer data among different clock domains so as to eliminate a metastable state in data transmission;

the serial-parallel converter converts a plurality of serial signals into 1 set of parallel signals; the normalization part normalizes the small signal voltage value and enhances the signal intensity;

the first layer of neurons is used for calculating the data output by the normalization part;

the activation part selects data in a ReLU format, and when the output of the first layer neuron is negative, the output is changed into 0, and when the output of the neuron is positive, the original value is kept unchanged;

the second layer of neurons is used for inputting weights during resetting, multiplying the calculation results of the first layer of neurons by the weights and finally adding the calculation results to the bias;

and the parallel-serial converter is used for converting the multi-bit data output by the secondary neuron into serial data and outputting the serial data.

The invention has the beneficial effects that:

1. only the voltage characteristic of the signal to be detected is used as the input of the deep neural network, and no extra equipment is needed for acquiring the transient characteristic and the stable period characteristic;

2. model optimization is carried out on the trained model through pruning, activating substitution and other modes, so that the size of the neural network model is further reduced;

3. the neural network with specific application is manufactured by pre-analyzing specific scenes, the size of the neural network is effectively reduced, and the minimum topology capable of working is searched by reducing the weight of the neural network, so that the power consumption of hardware is reduced.

Drawings

Fig. 1 is a hardware block diagram of a radio frequency signal detection system implemented by the present invention.

Fig. 2 is a circuit diagram of an ADC implemented by the present invention.

Fig. 3 is a diagram of the ADS7042 pin in the ADC circuit.

FIG. 4 is a diagram of CLK, CS and data output.

Fig. 5 is a graph of output data when no signal is applied to an ADC implemented by the present invention.

Fig. 6 is a data diagram of the ADC output in the case of no power discharge implemented by the present invention.

Fig. 7 is a graph of ADC output data under the condition of low-voltage power supply amplification of a semiconductor device with extremely low power consumption realized by the invention.

Fig. 8 is a data plot of the ADC output for the case of input RFID implemented by the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The invention realizes a radio frequency signal detection system based on machine learning, which mainly comprises:

the antenna and impedance matching unit consists of a source antenna and an impedance matching module and is used for receiving analog signals in the air and transmitting the analog signals as input to an ADC (analog-to-digital converter) circuit at the rear end; the source antenna usually comprises an antenna array formed by a plurality of antennas, and the impedance matching module obtains smith artwork through ADS simulation and performs impedance matching according to the result. The antenna and impedance matching unit includes: the source antenna is an antenna which receives LoRa signals and RFID signals by using a 915M frequency band, and the impedance matching module is an impedance matching circuit designed according to frequency so as to ensure that more sending signals are received and a back-end circuit can detect the signals.

Fig. 1 is a hardware configuration of the rf signal detection system of the present invention, which includes the aforementioned antenna and ADC circuit part, and converts the signal into a 12-bit effective digital signal, and inputs the signal to the FPGA neural network, and the part of the neural network includes: the system comprises a data input part, a serial-to-parallel converter, normalization, a first layer of neurons, an activation function, a second layer of neurons and a parallel-to-serial converter.

The source antenna of the ADC circuit receives an analog signal in the air, the ADC performs sampling and analog-to-digital conversion, and the analog signal is transmitted to the back-end circuit in a digital string mode; the ADC circuit includes a driver, a high-pass filter circuit and an analog-to-digital converter, and fig. 2 is a structure diagram of the ADC circuit, and first receives an external LoRa or RFID signal by using an antenna, and at the same time, transmits the signal to a driver OPA835 after passing through an LC impedance matching circuit, and finally transmits the signal to an ADS7042 by passing through the high-pass filter circuit, and outputs 12-bit valid data.

Referring to fig. 3, fig. 3 is a diagram of an ADS7042 pin, where ADS7042 is a 12-bit, 1MSPS, analog-to-digital converter (ADC). The device supports a wide analog input voltage range (1.65V to 3.6V) and includes a Successive Approximation Register (SAR) ADC based on capacitance and having a built-in sample-and-hold circuit. A Serial Peripheral Interface (SPI) compatible serial port is controlled by CS and SCLK signals. The input signal is sampled on the falling edge of CS and SCLK is used for conversion and serial data output. The device supports a wide range of digital power supplies (1.65V to 3.6V), can be directly connected to various types of host controllers and conforms to the nominal DVDD range (1.65V to 1.95V) of the JESD8-7A standard.

Fig. 4 is a diagram of relationship between CLK, CS and data output, in order to satisfy the requirement of 1M data sampling rate, the present invention sets reference voltage AVDD equal to 3V, DVDD equal to 3V, CLK equal to 16M clock, CS signal is 1M signal, AIMP switches in input signal, AINM and GND are both grounded, and the output of final data is observed. Wherein each 16 clock signals corresponds to a cycle of the CS signal, and data acquisition begins on the falling edge of the CS signal. At the beginning of data output, there will be 00 of two bits, representing the beginning of data output, and the next 12 bits are the result of output. Generation of the CS signal: and counting by using the CLK, wherein each sixteen clock periods correspond to the period of one CS signal, the CS signal is set to be low in the first 13 clock periods, and the CS signal is set to be high in 14-16 clock periods, and the steps are repeated in a circulating mode to finally obtain the CS signal.

The data input part consists of an ADC (analog to digital converter) and a D trigger group, wherein the ADC is used for converting collected analog signals into digital signals, and the D trigger is used for carrying out metastable state elimination in a cascading mode;

the serial-parallel converter converts a plurality of serial signals output by the ADC into 1 group of parallel signals;

the normalization part amplifies the small signal voltage value to a larger voltage value through normalization;

and the parallel-serial converter is used for converting the 45-bit data output by the secondary neuron into serial data and outputting the serial data.

Specifically, the method comprises the following steps:

1) data input part

The data input part mainly comprises an ADC and 2D triggers, wherein the ADC is used for converting collected analog signals into digital signals, and the 2D triggers carry out metastable state elimination and data buffering in a cascading mode.

2) Serial-to-parallel converter

Since the ADC starts sampling when the cs signal is at a low level, each clk cycle outputs a bit signal, and 12 bits of signals are output through 12 clock cycles to form 1 group of signals, which are provided to subsequent neurons for calculation, and thus 12 serial signals need to be converted into 1 group of parallel signals (12 bits) by the serial-to-parallel conversion module.

3) Normalization portion

Because the acquired voltage value is far lower than the reference voltage, in order to fully utilize the ADC digit, a normalization method is provided to normalize the small-range voltage value to the large-range voltage value.

The normalization method comprises the following steps: for example, it is autonomously specified that max is 10000000000(1.65V) and min is 0. Assuming that the data is 000000001000 (only 1 bit of 12-bit data is 1), the data is compared with the maximum value:

000000001000 (data collected by ADC)

100000000000(max value)

Careful comparison reveals that 1 in the data 000000001000 collected by the ADC occurs at the fourth bit, and 1 in the MAX value (001000000000) occurs at the 10 th bit, with 8 bits between two 1's, so that the data sampled by the ADC differs from the maximum value (MAX) by a factor of 2^8 (two data values differ by two for each bit).

Since 100000000000 is defined to correspond to 1 in the real number range, 12-bit data after conversion is 111111111111 at the maximum. 000000001000 differs from the max value by 256 times (2^8 ^ 256), and the inference can be derived to 000000001000 for 1/256 for the range of real numbers. And finally, comparing the acquired data with the maximum value to obtain a normalized result of 000000010000, thus completing the normalization of the ADC data.

Similarly, assuming that the data collected by the ADC is 000001010110, since there is more than one bit "1" in the data, the data needs to be split, that is:

000001010110＝000001000000+000000010000+000000000100+000000000010

and finally, converting each split data according to the flow, and summing the converted 12-bit data to obtain the finally normalized data.

4) First layer neurons

The primary neuron module is mainly used for calculating the data output after normalization, each weight is assigned when the data is reset, and then calculation is started when the input is not equal to 0111111111111 (0111111111111 is a default output value of normalization after the serial-parallel converter is reset, and when the input is not equal to the default output value, the serial-parallel converter outputs the first data). After each calculation, the count is automatically increased by one, and when the count is counted for 512 times, the calculation result is output.

Originally, the result register should be cleared by 0 every 512 data calculations, but this would use 1 clk cycle, so that the data input in this cycle is ignored, and therefore, currently, after the count is completed 512 times, the count is no longer cleared by 0, but the calculation is continued on the last calculation result. After the calculation is finished each time, the output result is sequentially transmitted to two registers of temp1 and temp2, and due to the adoption of a non-blocking assignment mode, the data in temp2 cannot be updated immediately after the output result is assigned to temp1, so that the output result after 512 times of the previous calculation is still kept in temp2, and therefore, the true result of the current calculation is obtained by subtracting temp1 from temp2, and the set offset is added to obtain the final output result of the neuron.

Because the normalized result cannot be directly multiplied by the weight value, the input needs to be correspondingly transformed. The transformation of the input in this part is converted into the transformation of the weight value (for example, when 000000000001 is input, the real calculation should be (1 x 3.3/4096) w, and the multiplication commutative law is changed into 1 x (w x 3.3/4096)), so that the input is not processed by adding hardware, the weight value w is directly converted on a computer and then replaces the current weight value, and the converted weight value is small and inconvenient to store, so that the converted result is multiplied by 1000000000.

5) Activating part

The module corresponds to an activation function used by a PC end training neural network, the current activation function selects a relu function, when the output of a first layer of neurons is negative, the output is changed into 0, and when the output of the neurons is positive, the original value is kept unchanged.

6) Second layer neurons

The overall calculation process of the second layer of neurons is the same as that of the first layer of neurons, weights are input during resetting, the calculation results of the first layer of neurons are multiplied by the weights, and finally the weights are added with the bias.

7) Parallel-serial converter

The parallel-serial converter mainly has the function of converting 45-bit data output by the secondary neuron into serial data for output, and is convenient for people to use a port to connect with an oscilloscope for observation. When the input is not 0 after the parallel-serial converter receives the output from the second-level neuron, 45-bit data is output in sequence from low to high, and the count is performed by using a counter. When the count is full of 45 (that is, 45 bits are all output), since the serial-parallel converter inputs 512 data, the neuron has an output value, so that the count continues to be performed after the counter counts to 45 and the parallel-serial converter output is set to 0, and the counter is cleared until the count is full of 512 to start parallel-serial conversion of new data.

The detection method realized by the invention comprises the following steps:

step 1, researching the communication environment of the signal to be detected. Including, but not limited to, the frequency band, bandwidth, modulation scheme, transmitter/receiver model, communication channel state information, noise conditions, etc. of the detected signal.

And 2, training a specific minimized neural network aiming at specific application, wherein the main purpose of the step is to train a specific neural network model aiming at a specific application scene and continuously optimize the neural network model until a minimized topological structure is obtained.

Selecting a neural network model, input data design and activation steps: considering that operations such as convolution and the like on an embedded system have large storage and power consumption expenses, a trained neural network model is preferably a simple DNN (deep neural network) structure, the DNN neural network consists of an input layer, a hidden layer and an output layer, wherein in order to reduce the number of preprocessing modules, voltage values received by an ADC (analog to digital converter) and a certain number of neurons in the hidden layer are used for input data, each neuron performs multiplication and accumulation of weight values and outputs, the output of each layer is used as the input of the next layer after nonlinear operation of an activation function, and the output of the output layer is used as output data. In order to reduce the implementation difficulty of embedded development, the method selects ReLU in the activation step so as to reduce the overhead of the embedded system for realizing nonlinear operation.

Minimizing neural network topology: presetting a list of hidden layer numbers, a list of neuron numbers and a list of blocksize sizes. When the method is used, the model is trained from the minimum value in the list, each parameter is trained for at least 20 times, the effect of the neural network is tested after the network is trained for each time, and the model is the minimized neural network model until the model meeting the test standard (the test standard is that the precision ratio and the recall ratio of the neural network on a test set reach more than 99%) appears.

Input data size is minimized: since the accuracy of the network model has a positive correlation with the size of the input data, a dichotomy can be adopted to find an optimal solution. The main process is as follows: 1. designing a small-to-large input data sorting list, training for the first time, selecting the input as the maximum value of the sorting list, and testing the feasibility of the network. After the test is feasible, the neural network is tested using dichotomy until the smallest neural network input is found.

And 3, manually adjusting parameters (weight and bias) of the neural network, thereby saving an activation step under the condition of not influencing the network function. And manually modifying the trained model. Some of these thresholds and weights are adjusted so that the network can be successfully used without the need for an activation step. The specific adjustment principle is as follows: a: the off-line training model is usually a value of a 64-bit system, and the embedded system does not usually have such a large number space, so that decimal storage in the weight is removed by integrally expanding and rounding the weight, and the difficulty of decimal storage and decimal calculation in the embedded system is reduced. B: and modifying the weight according to the reserved calculation bit width and calculation precision in the embedded system, and converting the weight into a numerical value which can be expressed in the embedded system. C. The output of the neural network is limited to a specific range through the modification of the bias, so that the judgment difficulty of the embedded system is reduced.

And 4, finally converting the trained weight and bias into verilog codes, and writing the verilog codes into an embedded system for signal detection.

Specific experimental effects

On the basis of the examples, experiments are carried out, and the specific steps of the experiments are as follows: in the 915Mhz band, the main signals present are LoRa and RFID, as well as noise.

Step 1, receiving training data, preprocessing the data and constructing a training set. One LORA transmitting node, a plurality of connecting wires, a plurality of attenuators, one USRP and one desktop computer are used. The LORA transmitting node, the attenuator and the USRP are connected in series, and LORA data under different attenuations are collected to serve as pure LORA data. And opening the node before each experiment, and receiving data after the data to be sent is stable after 5 minutes. And (4) receiving 50s of data in each group, and eliminating the data in the first 20s for extracting the data received under the stable state of the channel without using the data. When receiving data, the experimental variable is the attenuation between the node and the USRP, 10,20,30 and 40dB of attenuation are added respectively, and each attenuation receives 5 groups of original data.

According to the same deployment, the LORA node is replaced with an RFID device and an antenna, and RFID data and noise data are received.

The collected LORA data is processed as follows:

and I, intercepting two continuous up chirp in the Preamble as a data sample, and intercepting every two data samples from the position 1, wherein 9 data samples are intercepted by each LORA packet.

And II, carrying out loading wave processing on the extracted up chirp data.

The specific method comprises the following steps: firstly, the received USRP data is subjected to upsampling treatment, the sampling rate is increased from 6M to 2.5G, then, a carrier wave with the center frequency of 915MHz is generated, operation is carried out on the carrier wave and the upsampled data, and finally, whether the carrier wave is loaded successfully or not is judged by using FFT.

And III, performing down-sampling on the data added with the carrier wave, wherein the sampling rate is 1M, and the sampling data is 512 data points.

The transmission duration of each chirp is as follows:

the number of sampling points per chirp is then:

therefore, the number of sampling points of the two chirp is 512

And IV, normalizing the down-sampled data to the interval of [ -1,1 ].

And V, labeling the data. After all data files are collected, the signals are classified according to attenuation difference, labels are set to construct a training set, for example LORA is set to [1,0] RFID and noise is set to [0,1]

Step 2, a three-layer DNN classification model was then designed by the tenarsflow-based keras framework: the input layer is voltage value data with the length of 64, the hidden layer has three neurons, and each neuron has 64 weights and one offset; the hidden layer is connected with the output layer through a ReLu activation function; the output layer is two neurons, each neuron has three weights and one offset, and the output layer and the final output are connected through a ReLu activation function. During training, a group of LoRa signals are input each time, the output value is enabled to be close to [1,0] by adjusting network parameters (weight and bias), and the output value is enabled to be close to [0,1] by adjusting parameters each time a group of RFID signals are input. After 30 cycles, an initial neural network model was obtained under the callout of keras.

Step 3, weight revision and network pruning: by the output judgment, the neural network output value can be judged by using only the first neuron element of the output layer. Thereby deleting the output layer second neuron. And finally, adjusting the bias to ensure that the output of the neural network can be distinguished only by judging positive and negative positions.

And 4, converting the weight, the bias and the implementation process of the neural network into verilog codes and burning the verilog codes into the FPGA board. The FPGA mainly comprises 7 parts which are respectively as follows: data input, serial-to-parallel conversion, normalization, a first layer of neurons, an activation function, a second layer of neurons, and a parallel-to-serial converter; (1) the data input section: the digital signal processing device mainly comprises an ADC and 2D triggers, wherein the ADC is used for converting an analog signal obtained after s into a digital signal, and the 2D triggers are cascaded to buffer data in a 'two-row' mode. (2) A serial-to-parallel converter: because the ADC outputs a signal every clk cycle when the CS signal is low, and 12-bit signals are output through 12 clock cycles to form 1 group of signals, which are supplied to subsequent neurons for calculation, the serial-to-parallel conversion module is required to convert the 12 serial signals into 1 group of 12-bit parallel signals. (3) Normalization: the basic principle is to decompose a group of data into the sum of a plurality of 12-bit data, each 12-bit data only contains one bit of 1, compare the 12-bit data with the maximum value at the same time, and finally reduce a plurality of comparison results and accumulate the comparison results together to be used as the result of normalization of each group of data. (4) First layer of neurons: the first-level neuron module is mainly used for calculating the data output after normalization, each weight is assigned when the data is reset, the count is automatically increased by one after each calculation, and when the count is counted for 521 times, the calculation result is output. 5. The signals are transmitted into the ADC through the antenna for sampling to obtain 12-bit serial data, and the 12-bit serial data are transmitted into the FPGA through the serial port for weight calculation to obtain a final result.

First, ADC verification experiment (1M sampling rate setting)

In order to verify whether the data output by the ADC is correct or not, the results of the ADC output with different input voltages are collected and calculated, and although the calculated results have errors with the voltages measured by a multimeter, the errors can be accepted. Specific results are shown in table 1. (theoretical reference voltage applied is 3.3V, and actual multimeter test reference voltage is 3.52V)

The output results of the ADC with an input voltage value of 0.61V are shown in the following table (the first two bits 00 are removed).

TABLE 1

And (4) conclusion: the actual voltage of 0.61V is added and the actual data output is 0.57V.

The ADC output results for an input voltage value of 0.88V are shown in Table 2 (the first two bits 00 are removed).

TABLE 2

And (4) conclusion: the actual voltage added is 0.88V, while the actual data output is 0.817V.

The ADC output results for an input voltage value of 1.67V are shown in Table 3 (the first two digits 00 are removed).

TABLE 3

And (4) conclusion: the actual voltage added is 1.67V, while the actual data output is 1.523V.

The ADC output results for an input voltage value of 2.44V are shown in Table 4 (the first two bits 00 are removed).

TABLE 4

And (4) conclusion: the actual voltage added is 2.44V, while the actual data output is 2.42V.

The ADC output results for the input lora signal are shown in table 5 (the first two bits 00 are removed).

TABLE 5

And (4) conclusion: the lora signal actually added is 0.09V, while the actual data output is around 0.0825V.

In summary, the data output from the ADC is approximately close to the actual input voltage, although it has some error. The ADC can be verified to be capable of collecting data to work normally.

The method is used for testing whether the output of the FPGA board is correct or not, and the board can correctly detect 99% of lora signals through model detection.

Second, ADC detection and hardware neural network simulation test experiment

In order to verify that the hardware neural network can identify the Lora and the RFID signals by acquiring the data information of the Lora and the RFID through the ADC in the actual environment, the following experiment is performed.

Experimental tools: 915M antenna, Lora node, ADC circuit board, PLORA module, 3.3V power, oscilloscope, power amplifier, RFID reader, computer.

The experimental method comprises the following steps:

the air floor noise was first tested. The antenna is directly connected with the oscilloscope, the waveforms of the electromagnetic waves in the air in the oscilloscope are collected, and a group of waveforms are collected.

And testing the data output of the ADC circuit when no signal is added. The ADC circuit board is connected with the Plor module, data output by the ADC are tested by an oscilloscope, and three paths of waveforms are received. Clk, 16M clock signal; and secondly, starting sampling by a test signal and a chip selection signal at the cs falling edge. And thirdly, outputting data by the ADC.

The method comprises the steps of sending a Lora signal by using a Lora node, well connecting an ADC circuit with a plora module (the plora module provides clk and cs signals), enabling the distance between the Lora node and an ADC receiving antenna to be 5cm, and testing output data of the ADC module by using an oscilloscope. Clk, 16M clock signal; and secondly, starting sampling by a test signal and a chip selection signal at the cs falling edge. And thirdly, outputting data by the ADC, and receiving three groups of waveforms, wherein each group at least comprises 512 groups of data.

And (3) sending an RFID signal by using an RFID reader, well connecting the ADC circuit with the plora module (the plora module provides clk and cs signals), enabling the distance between the RFID antenna and the ADC receiving antenna to be 5cm, and testing the output data of the ADC module by using an oscilloscope. Clk, 16M clock signal; and secondly, starting sampling by a test signal and a chip selection signal at the cs falling edge. And thirdly, outputting data by the ADC, and receiving three groups of waveforms, wherein each group at least comprises 512 groups of data.

The data collected by the oscilloscope (the five groups of data) are processed by matiab, and each group of data is output at 6144 points (one group, namely 512 12-bit data), so as to obtain table 6.

TABLE 6 ADC output results without signal addition

And (4) conclusion: the actual voltage added is 2.44V, while the actual data output is 2.42V. The data output by the ADC is approximately close, although it has some error with the actual input voltage. The ADC can be verified to be capable of collecting data to work normally.

TABLE 7 ADC output results of input lora signals

And (4) conclusion: the lora signal actually added is 0.09V, and the actual data output is around 0.0825V. The test result is within the error tolerance range, and the LoRa signal can be judged in table 7.

Simulation experiment:

(1) when no signal is applied to the ADC, the data output from the ADC, as shown in fig. 5, is negative in network output after passing through the network. The selected row in the (not Lora, logical-in-line) diagram is the sign bit.

(2) Under the condition of no power amplifier, Lora signals are input, and as shown in figure 6, after the Lora signals pass through the network, the output result is positive, and the Lora signals accord with the logic of the network. The selected row in the figure is the sign bit.

(3) However, after the 20db power amplifier is added to the Lora node, as shown in fig. 7, the network output result is negative: the selected row in the diagram is the sign bit (not logically coincident).

(4) In the case of an incoming RFID, as shown in fig. 8, the result is negative across the network: the selected row in the diagram (which corresponds to the logic of the network) is the sign bit.

According to the experimental simulation result: through the hardware neural network, the LoRa and the RFID signal can be verified, namely the output result of the LoRa signal through the neural network is positive, and the output result of the RFID signal is negative. Through the experiments, the feasibility of the hardware network is verified.

In conclusion, the beneficial effects of the invention are as follows:

1. only the voltage characteristic of the signal to be detected is used as the input of the deep neural network, and no additional equipment is needed for acquiring the transient characteristic and the stable period characteristic.

2. Model optimization is carried out on the trained model through pruning, activating replacing and other modes, and therefore the size of the neural network model is further reduced.

The present invention is not limited to the above preferred embodiments, and any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A radio frequency signal detection method based on machine learning comprises the following steps:

step 2: constructing a neural network architecture, training a minimized neural network model by using a PC (personal computer) offline, training the neural network model for an application scene, pruning the number of units in the system from a dense network, and continuously optimizing the neural network model until a minimized topological structure is obtained, so that the balance between the minimized topological structure and the maximized detection effect is achieved;

the step of training the minimized neural network model offline by using the PC to obtain the minimized topological structure comprises the following steps: selecting a neural network model, selecting input data, selecting an activation model, minimizing the size of the input data and minimizing the topology of the neural network;

designing a three-layer deep learning neural network structure DNN classification model by a keras framework based on tenserflow: the input layer is voltage value data with the length of 64, the hidden layer has three neurons, and each neuron has 64 weights and one offset; the hidden layer is connected with the output layer through a ReLu activation function; the output layer is two neurons, each neuron has three weights and one offset, and the output layer is connected with the final output through a ReLu activation function; during training, inputting a group of LoRa signals every time, enabling the output value to be close to [1,0] by adjusting network parameters, inputting a group of RFID signals every time, and adjusting parameters to enable the output value to be close to [0,1 ];

and step 3: weight revision and network pruning: through output judgment, the output value of the neural network can be judged only by using the first neuron of the output layer, so that the second neuron of the output layer is deleted; adjusting the weight and the bias of the neural network parameters according to the performance of the neural network, and saving the activation step under the condition of not influencing the network function;

the technical process of adjusting the weight and the bias of the neural network parameters according to the performance of the neural network comprises the following steps: the decimal storage in the weight is removed by integrally expanding and rounding the weight, so that the difficulty of decimal storage and decimal calculation in an embedded system is reduced; modifying the weight according to the reserved calculation bit width and calculation precision in the embedded system, and converting the weight into a numerical value which can be expressed in the embedded system; the output of the neural network is limited to a specific range by modifying the bias, so that the judgment difficulty of the embedded system is reduced;

and 4, step 4: converting the weight, the bias and the implementation process of the neural network into verilog codes and burning the verilog codes into an FPGA;

the FPGA mainly comprises 7 parts which are respectively as follows: data input, serial-to-parallel conversion, normalization, a first layer of neurons, an activation function, a second layer of neurons, and a parallel-to-serial converter; (1) the data input section: the digital-to-analog converter ADC is used for converting an analog signal obtained after s into a digital signal, and the 2D triggers are cascaded to buffer data in a 'two-row' mode; (2) a serial-to-parallel converter: when the CS signal is at a low level, the analog-to-digital converter ADC outputs a signal in each clk period, and 12-bit signals are output in 12 clock periods to form 1 group of signals, which are provided to subsequent neurons for calculation, so that the serial-to-parallel conversion module is required to convert the 12 serial signals into 1 group of 12-bit parallel signals; (3) normalization: the basic principle is that a group of data is decomposed into the sum of a plurality of 12-bit data, each 12-bit data only contains one bit of 1, the 12-bit data are compared with the maximum value at the same time, and finally, a plurality of comparison results are reduced and accumulated together to be used as the result of normalization of each group of data; (4) first layer of neurons: the first-level neuron module is mainly used for calculating the data output after normalization, each weight is assigned when the data is reset, the count is automatically increased by one after each calculation, and when the count of the count is 521 times, the calculation result is output; (5) transmitting the signal into an analog-to-digital converter (ADC) through an antenna for sampling to obtain 12-bit serial data, transmitting the 12-bit serial data into a Field Programmable Gate Array (FPGA) through a serial port for weight calculation to obtain a final result; the selection of the neural network model is a deep learning neural network structure DNN, and the deep learning neural network structure DNN consists of an input layer, a hidden layer and an output layer;

the input data selection comprises that input data uses a voltage value received by an ADC circuit, a hidden layer is a certain number of neurons, each neuron performs weight and output multiplication accumulation, the output of each layer is used as the input of the next layer after the nonlinear operation of an activation model is carried out, and the output of an output layer is used as output data;

input data size is minimized: designing a sorted list of input data from small to large by utilizing the positive correlation between the accuracy of a network model and the size of the input data, training for the first time and selecting the input as the maximum value of the sorted list, testing the feasibility of the network, and testing the neural network by using a dichotomy method after the test is feasible until the minimum neural network input is found;

minimizing the neural network topology: presetting a list of hidden layer numbers, a list of neuron numbers and a list of blocksize sizes; when the method is used, the model is trained from the minimum value in the list, each parameter is trained for tens of times, the effect of the neural network is tested after the network is trained for each time, and the model is the minimized neural network model until the model meeting the test standard appears.