CN111858178B - Method, device and equipment for judging power supply starting type and readable medium - Google Patents
Method, device and equipment for judging power supply starting type and readable medium Download PDFInfo
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Abstract
The invention discloses a method for judging the starting type of a power supply, which comprises the following steps: acquiring a starting signal of a power supply and judging whether the starting type is a first type behavior or a second type behavior based on the starting signal; if the first type of behavior exists, the judgment result is sent to a register; if the second type of behavior is detected, temporarily storing the judgment result in the FLASH, reading the judgment result when the FLASH is powered on again and sending the judgment result to the register; and polling the register through the I2C to obtain a judgment result, generating a starting log based on the judgment result, and clearing the information in the register. The invention also discloses a device for judging the power supply starting type, computer equipment and a readable storage medium. The invention judges the switch starting type through CPLD/FPGA logic and records the switch starting type in the register, and the BMC/CPU polls and accesses the register information through I2C and generates a corresponding log, thereby facilitating the monitoring of the running state of the switch, analyzing and positioning the fault problem and being beneficial to the field recovery of the switch when the fault occurs.
Description
Technical Field
The invention relates to the technical field of cloud computing, in particular to a method, a device, equipment and a readable medium for judging a power supply starting type.
Background
In the switch system, the CPLD/FPGA chip is used for controlling the power-on and power-off sequence control, communication control, key detection, fan rotating speed control, SFP lighting control, serial port switching, port control during upgrading and the like of the whole switch, and the BMC/CPU is used for indicating the state, state detection, firmware upgrading, remote control, log collection and the like of the switch. Throughout the lifetime of the switch: the method relates to Cold restart, cold Reboot, hot Reboot, system shutdown, first insertion of AC power lines and all PSU missing types, and reliable and accurate display of BMC/CPU has important significance for research, development, debugging, problem positioning and customer interaction.
For the Cold restart Cold Reboot, the hot restart Warm Reboot, the system shutdown and the first AC power line insertion behavior of the switch, the system power of the switch cannot be lost, and meanwhile, the startup types often need a plurality of trigger condition judgment, so that the overhead of upper layer judgment is often very large, and meanwhile, the BMC/CPU running frequency is relatively low, and the change edges of some signals cannot be captured.
For all PSU losses, the entire switch system will not have power to supply, and the BMC/CPU will not be able to obtain this information either.
Disclosure of Invention
In view of this, an object of the embodiments of the present invention is to provide a method, an apparatus, a device, and a readable medium for determining a power supply start type, where a CPLD/FPGA logic is used to determine a switch start type and record the switch start type in a register, and a BMC/CPU polls and accesses the register information and generates a corresponding log through an I2C, so as to facilitate monitoring of an operation state of the switch, analysis and location of a fault problem, and facilitate field recovery of the switch when the fault occurs.
Based on the above object, an aspect of the embodiments of the present invention provides a method for determining a power supply startup type, including the following steps: acquiring a starting signal of a power supply and judging whether the starting type is a first type behavior or a second type behavior based on the starting signal; if the first type of behavior exists, the judgment result is sent to a register; if the second type of behavior is detected, temporarily storing the judgment result in the FLASH, and reading the judgment result and sending the judgment result to the register when the FLASH is powered on again; and polling the register through the I2C to obtain a judgment result, generating a starting log based on the judgment result, and clearing the information in the register.
In some embodiments, obtaining an activation signal for the power source and determining the activation type as the first type of behavior or the second type of behavior based on the activation signal includes: acquiring a power supply signal, a shutdown signal and a reset signal; judging whether the power supply signal has a falling edge or not; if the power supply signal does not have a falling edge, judging that the starting type is a first type of behavior; and if the power supply signal has a falling edge, judging that the starting type is the second type of behavior, and further judging that the second type of behavior is all PSU loss behaviors.
In some embodiments, if the power signal has not a falling edge, determining that the first type of behavior includes: if the power signal generates a rising edge, judging that the starting type is a power line first-time insertion starting behavior; if the power supply signal does not have a falling edge and does not have a rising edge, the shutdown signal is further judged.
In some embodiments, further determining the shutdown signal comprises: judging whether the shutdown signal has a falling edge or not; if the shutdown signal does not have a falling edge, further judging whether the reset signal has a falling edge; if the reset signal does not have a falling edge, judging that the restart does not occur; and if the reset signal has a falling edge, judging that the starting type is the hot restarting behavior.
In some embodiments, further comprising: if the shutdown signal has a falling edge, acquiring the shutdown signal again after a preset time, and judging whether the shutdown signal has a rising edge again; if the shutdown signal is judged again not to have a rising edge, judging that the starting type is a system shutdown behavior; and if the rising edge of the shutdown signal is judged again, judging that the starting type is the cold restart behavior.
In some embodiments, temporarily storing the determination result in FLASH includes: the CPLD writes the judgment result into the built-in FLASH; or the FPGA writes the judgment result into the plug-in FLASH.
In some embodiments, clearing information in the register includes: if the first type of behavior exists, clearing the information of the register through I2C; if the second type of behavior is the behavior, the information of the register is cleared through the I2C and a command is issued to clear the FLASH.
In another aspect of the embodiments of the present invention, a device for determining a power supply start type is further provided, including: the judging module is configured to acquire a starting signal of the power supply and judge whether the starting type is a first type behavior or a second type behavior based on the starting signal; the register module is used for sending the judgment result to the register if the first type of behavior is obtained; if the second type of behavior is judged to be the second type of behavior, the second type of behavior is further configured to temporarily store the judgment result in the FLASH, and when the power is on again, the judgment result is read and sent to the register; and the recording module is configured to poll the register through the I2C to acquire a judgment result, generate a start log based on the judgment result and clear information in the register.
In some embodiments, the determining module is further configured to: acquiring a power supply signal, a shutdown signal and a reset signal; judging whether the power supply signal has a falling edge or not; if the power supply signal does not have a falling edge, judging that the starting type is a first type of behavior; and if the power supply signal has a falling edge, judging that the starting type is the second type of behavior, and further judging that the second type of behavior is all PSU loss behaviors.
In some embodiments, the determining module is further configured to: if the power signal generates a rising edge, judging that the starting type is a power line first-time insertion starting behavior; if the power supply signal does not have a falling edge and does not have a rising edge, the shutdown signal is further judged.
In some embodiments, the determining module is further configured to: judging whether the shutdown signal has a falling edge or not; if the shutdown signal does not have a falling edge, further judging whether the reset signal has a falling edge; if the reset signal does not generate a falling edge, judging that the restart does not occur; and if the reset signal has a falling edge, judging that the starting type is a hot restart behavior.
In some embodiments, the determining module is further configured to: if the shutdown signal has a falling edge, acquiring the shutdown signal again after preset time and judging whether the shutdown signal has a rising edge again; if the shutdown signal is judged again not to have a rising edge, judging that the starting type is a system shutdown behavior; and if the rising edge of the shutdown signal is judged again, judging that the starting type is the cold restart behavior.
In some embodiments, the registering module is further configured to: the CPLD writes the judgment result into the built-in FLASH; or the FPGA writes the judgment result into the plug-in FLASH.
In some embodiments, the recording module is further configured to: if the first type of behavior exists, clearing the information of the register through I2C; if the second type of behavior is the behavior, the information of the register is cleared through the I2C and a command is issued to clear the FLASH.
In another aspect of the embodiments of the present invention, there is also provided a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method.
In another aspect of the embodiments of the present invention, a computer-readable storage medium is further provided, in which a computer program for implementing the above method steps is stored when the computer program is executed by a processor.
The invention has the following beneficial technical effects: the starting type of the switch is judged through the CPLD/FPGA logic and recorded in the register, and the BMC/CPU polls and accesses the register information through the I2C and generates a corresponding log, so that the running state of the switch is conveniently monitored, the fault problem is analyzed and positioned, and the field recovery of the switch during the fault is facilitated.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram illustrating an embodiment of a method for determining a power source start type according to the present invention;
FIG. 2 is a schematic diagram of an embodiment of a power-on type determining apparatus provided in the present invention;
FIG. 3 is a schematic diagram of an embodiment of a computer device provided by the present invention;
FIG. 4 is a schematic diagram of an embodiment of a computer-readable storage medium provided by the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are only used for convenience of expression and should not be construed as a limitation to the embodiments of the present invention, and no description is given in the following embodiments.
In view of the above object, a first aspect of the embodiments of the present invention proposes an embodiment of a method for determining a power supply startup type. Fig. 1 is a schematic diagram illustrating an embodiment of a method for determining a power supply startup type according to the present invention. As shown in fig. 1, the embodiment of the present invention includes the following steps:
s1, acquiring a starting signal of a power supply and judging whether the starting type is a first type behavior or a second type behavior based on the starting signal;
s2, if the first type of behavior exists, sending a judgment result to a register;
s3, if the second type of behavior is detected, temporarily storing the judgment result in the FLASH, and reading the judgment result and sending the judgment result to a register when the FLASH is powered on again; and
and S4, polling the register through the I2C to obtain a judgment result, generating a starting log based on the judgment result, and clearing the information in the register.
In the embodiment, the system comprises a CPLD/FPGA logic judgment register module and a BMC/CPU display control module, wherein the BMC/CPU and the CPLD/FPGA are communicated through an I2C.
CPLD (Complex Programmable Logic Device) is a Complex Programmable Logic Device, FPGA (Field Programmable Gate Array) is a Field Programmable GATE Array. The CPLD/FPGA is a semi-customized special integrated circuit, has the series advantages of flexible programming, quick response, high integration level and the like, and is more and more widely applied to the field of development, verification and control application in the prior period. For the switch, the flexible programming of the CPLD/FPGA means that the switch can be flexibly designed, realizes the complex logic judgment through the logic programming and provides a simple interface for the BMC/CPU. For the first type of behaviors, the power supply of the switch system cannot be lost, and the judgment result is directly sent to a register; for the second type of behaviors, the switch system has no power supply, and the CPLD/FPGA can acquire and store the information into an internal or external FLASH which is not lost when power is off by utilizing the voltage sustaining capability of an external capacitor.
The BMC (Baseboard Management Controller) is a Baseboard Management Controller, and the CPU (Central Processor Unit) is a Central processing Unit. For CPLD registers accessed by the BMC/CPU, interrupts cannot be designed, but only polling is performed. The BMC/CPU can judge the state of the switch by accessing the state of the CPLD/FPGA register through protocols such as I2C and the like, and records and displays the state in a log containing a timestamp. If the starting type is designed to be a pulse, the BMC/CPU can not intercept the information, so that the information needs to be designed to be in a level form through logic processing; meanwhile, the restart type may be triggered many times during the operation of the switch, so the BMC/CPU must put the CPLD/FPGA register in an invalid state after acquiring the restart information.
In this embodiment, the first type of behavior is determined by the power signal PSU _ PWROK, the shutdown signal SLP _ S4 and the reset signal PLT _ RST _ N, the determined result outputs a pulse signal and is placed in the register storage module, and the BMC/CPU polls the information through I2C to obtain the information and then outputs a corresponding log; and after the BMC/CPU obtains the starting information, the register information is cleared through the I2C. The boot-type switch system of the first type of activity must be powered and therefore this information can be stored in RAM that is lost upon a power failure.
The second kind of behaviors are judged through a power supply signal PSU _ PWROK, the power supply signal PSU _ PWROK is invalid when a falling edge occurs, and the CPLD/FPGA writes the information into the FLASH, wherein the CPLD can write into the built-in FLASH, and the FPGA can write into the plug-in FLASH; when the power is on again, the CPLD/FPGA triggers and reads the FLASH information and stores the information to the register storage module, the BMC/CPU acquires the information through the I2C, the acquired BMC/CPU outputs a log prompt and issues FLASH clearing information at the same time, and the CPLD/FPGA executes FLASH clearing action.
In some embodiments of the present invention, obtaining a start signal of a power supply and determining, based on the start signal, whether the start type is a first type of behavior or a second type of behavior includes: acquiring a power supply signal, a shutdown signal and a reset signal; judging whether the power supply signal has a falling edge or not; if the power supply signal does not have a falling edge, judging that the starting type is a first type behavior; and if the power supply signal has a falling edge, judging that the starting type is the second type of behavior, and further judging that the second type of behavior is all PSU loss behaviors.
In this embodiment, when a power signal falls, it is determined that the start type is a loss behavior of all PSUs, and at this time, the switch loses power supply, the CPLD/FPGA writes loss information into a FLASH that is not lost when power is turned on, and when power is turned on, the CPLD/FPGA reads FLASH information and writes the information into a RAM that is lost when power is turned off, which facilitates the BMC/CPU to obtain information. Specifically, the FLASH of the CPLD may be an internally integrated FLASH, and may use a UFM (User FLASH Memory) technology. The FLASH for the FPGA is an externally-hung FLASH.
In some embodiments of the present invention, if the power signal has not a falling edge, determining that the first type of behavior includes: if the power signal generates a rising edge, judging that the starting type is a power line first-time insertion starting behavior; if the power supply signal does not have a falling edge and does not have a rising edge, the shutdown signal is further judged.
In this embodiment, when the power signal is rising, and the start type is the first time of the AC power line power-on, the power signal PSU _ PWROK or logic rising edge is generated first, and then the power-off signal SLP _ S4 and the reset signal PLT _ RST _ N rising edge are sequentially generated.
In some embodiments of the present invention, further determining the shutdown signal comprises: judging whether the shutdown signal has a falling edge or not; if the shutdown signal does not have a falling edge, further judging whether the reset signal has a falling edge; if the reset signal does not have a falling edge, judging that the restart does not occur; and if the reset signal has a falling edge, judging that the starting type is the hot restarting behavior.
In this embodiment, the power signal does not have a falling edge and a rising edge, and meanwhile, the shutdown signal does not have a falling edge, and the reset signal does not have a falling edge, and it is determined that the restart has not occurred.
In this embodiment, the power signal does not have a falling edge and a rising edge, and meanwhile, the shutdown signal does not have a falling edge, and the reset signal has a falling edge, so that it is determined that the Warm restart Warm Reboot behavior occurs, and at this time, only the reset signal PLT _ RST _ N is low-pulsed, and during this process, no action occurs in the or logic of the shutdown signal SLP _ S4 and the power signal PSU _ PWROK.
In some embodiments of the invention, further comprising: if the shutdown signal has a falling edge, acquiring the shutdown signal again after preset time and judging whether the shutdown signal has a rising edge again; if the shutdown signal is judged to have no rising edge again, judging that the starting type is a system shutdown behavior; and if the rising edge of the shutdown signal is judged again, judging that the starting type is the cold restart behavior.
In this embodiment, the power signal does not have a falling edge and a rising edge, the shutdown signal has a falling edge, the reset signal does not have a rising edge after a period of time, and it is determined that the start type is the system shutdown behavior, at this time, the reset signal PLT _ RST _ N first generates a falling edge, then the shutdown signal SLP _ S4 generates a falling edge, the or logic of the power signal PSU _ PWROK does not generate any action, then there is no signal change of the reset signal PLT _ RST _ N or the shutdown signal SLP _ S4, and only when the startup action is re-executed, the related signals SLP _ S4 and the reset signal PLT _ RST _ N sequentially generate rising edges.
In this embodiment, the power signal does not have a falling edge and a rising edge, the shutdown signal has a falling edge, the reset signal has a rising edge after a period of time, and it is determined that the start type is Cold Reboot behavior, at this time, the reset signal PLT _ RST _ N first generates a falling edge, the shutdown signal SLP _ S4 generates a falling edge, the or logic of the power PSU _ PWROK does not generate any action, the shutdown signal SLP _ S4 generates a rising edge, and the reset signal PLT _ RST _ N generates a rising edge.
In some embodiments of the present invention, temporarily storing the determination result in FLASH includes: the CPLD writes the judgment result into the built-in FLASH; or the FPGA writes the judgment result into the plug-in FLASH.
In the embodiment, the switch loses power supply, the CPLD/FPGA writes the loss information into the FLASH which is not lost when the power is off, and when the switch is powered on, the CPLD/FPGA reads the FLASH information and writes the information into the RAM which is lost when the power is off, so that the BMC/CPU can conveniently obtain the information. Specifically, the FLASH of the CPLD may be an internally integrated FLASH, and may use a UFM (User FLASH Memory) technology. The FLASH for the FPGA is an externally-hung FLASH.
In some embodiments of the invention, clearing information in the register comprises: if the first type of behavior exists, clearing the information of the register through I2C; if the second type of behavior is the behavior, the information of the register is cleared through the I2C and a command is issued to clear the FLASH for recording the restart information again.
In this embodiment, the first type of behavior does not cause the switch to lose power, so the startup information can be directly written into the RAM; because the RAM needs to record the starting information for many times, the RAM of the CPLD/FPGA needs to be cleared when the BMC/CPU obtains the starting information.
In this embodiment, the second type of behavior may cause a power loss of the switch system, so that the startup information needs to be temporarily stored in the FLASH that is not lost due to power failure, and when the switch is started, the CPLD/FPGA acquires information from the FLASH and writes the information into the RAM; because the RAM and the FLASH need to record the starting information for many times, when the BMC/CPU obtains the starting information, the BMC/CPU clears the RAM, and meanwhile, the CPLD/FPGA needs to clear the corresponding indicating bit of the FLASH.
It should be noted that, the steps in the embodiments of the method for determining a power-on type may be mutually intersected, replaced, added, or deleted, and therefore, the method for determining a power-on type for which the reasonable permutation and combination are changed also belongs to the scope of the present invention, and the scope of the present invention should not be limited to the embodiments.
In view of the above object, a second aspect of the embodiments of the present invention provides a device for determining a power supply startup type. Fig. 2 is a schematic diagram illustrating an embodiment of the power supply startup type determining apparatus provided in the present invention. As shown in fig. 2, the embodiment of the present invention includes the following modules: the judging module S11 is configured to obtain a starting signal of the power supply and judge whether the starting type is a first type behavior or a second type behavior based on the starting signal; the register module S12 is configured to send the judgment result to a register if the first type of behavior is the first type of behavior; if the second type of behavior is the behavior of the first type, the method is further configured to temporarily store the judgment result in the FLASH, and read the judgment result and send the judgment result to the register when the power is on again; and the recording module S13 is configured to poll the register through the I2C to obtain a judgment result, generate a start log based on the judgment result, and clear information in the register.
In some embodiments of the present invention, the determining module S11 is further configured to: acquiring a power supply signal, a shutdown signal and a reset signal; judging whether the power supply signal has a falling edge or not; if the power supply signal does not have a falling edge, judging that the starting type is a first type behavior; and if the power supply signal is in a falling edge state, judging that the starting type is the second type of behavior, and further judging that the second type of behavior is all PSU loss behaviors.
In some embodiments of the present invention, the determining module S11 is further configured to: if the power signal generates a rising edge, judging that the starting type is a power line first-time insertion starting behavior; if the power supply signal does not have a falling edge and does not have a rising edge, the shutdown signal is further judged.
In some embodiments of the invention, the determining module S11 is further configured to: judging whether the shutdown signal has a falling edge or not; if the shutdown signal does not have the falling edge, further judging whether the reset signal has the falling edge; if the reset signal does not generate a falling edge, judging that the restart does not occur; and if the reset signal has a falling edge, judging that the starting type is a hot restart behavior.
In some embodiments of the invention, the determining module S11 is further configured to: if the shutdown signal has a falling edge, acquiring the shutdown signal again after a preset time, and judging whether the shutdown signal has a rising edge again; if the shutdown signal is judged to have no rising edge again, judging that the starting type is a system shutdown behavior; and if the rising edge of the shutdown signal is judged again, judging that the starting type is the cold restart behavior.
In some embodiments of the present invention, the register module S12 is further configured to: the CPLD writes the judgment result into the built-in FLASH; or the FPGA writes the judgment result into the plug-in FLASH.
In some embodiments of the invention, the recording module S13 is further configured to: if the first type of behavior exists, clearing the information of the register through I2C; if the second type of behavior is the behavior, the information of the register is cleared through the I2C and a command is issued to clear the FLASH.
Finally, it should be noted that, as those skilled in the art can understand, all or part of the processes in the methods of the above embodiments can be implemented by instructing relevant hardware through a computer program, and the program of the method for determining a power-on type can be stored in a computer-readable storage medium, and when executed, the program can include the processes of the embodiments of the methods as described above. The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
Furthermore, the methods disclosed according to embodiments of the invention may also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. Which when executed by a processor performs the above-described functions as defined in the method disclosed by an embodiment of the invention.
Further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the above embodiments of the present invention are merely for description, and do not represent the advantages or disadvantages of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant only to be exemplary, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (8)
1. A method for judging the starting type of a power supply is characterized by comprising the following steps:
acquiring a starting signal of a power supply based on a CPLD or an FPGA, wherein the starting signal comprises a power supply signal;
judging whether the power supply signal has a falling edge or not based on the CPLD or the FPGA, if the power supply signal has no falling edge, judging that the starting type is a first type of behavior, if the power supply signal has a falling edge, judging that the starting type is a second type of behavior, and further judging that the second type of behavior is all PSU loss behaviors;
if the first type of behavior exists, the judgment result is sent to a register based on the CPLD or the FPGA;
if the second type of behavior is detected, temporarily storing a judgment result in a FLASH based on the CPLD or the FPGA, and reading the judgment result and sending the judgment result to a register when the power is on again;
polling the register through I2C based on BMC or CPU to obtain the judgment result and generating a start log based on the judgment result;
and after a start log is generated based on the judgment result, if the start log is the first type of behavior, the information of the register is cleared through I2C based on the BMC or the CPU, and if the start log is the second type of behavior, the information of the register is cleared through I2C based on the BMC or the CPU, and a command is issued to clear the FLASH information.
2. The method for determining a power supply startup type according to claim 1, wherein the startup signal further comprises a shutdown signal;
if the power supply signal does not have a falling edge, determining that the first type of behavior comprises:
if the power signal is in the rising edge, judging that the starting type is the first power line plugging starting behavior;
and if the power supply signal does not have a falling edge and a rising edge, further judging the shutdown signal.
3. The method for determining a power supply startup type according to claim 2, wherein the startup signal further includes a reset signal;
further judging the shutdown signal comprises:
judging whether the shutdown signal has a falling edge or not;
if the shutdown signal does not have a falling edge, further judging whether the reset signal has a falling edge;
if the reset signal does not have a falling edge, judging that the restarting does not occur;
and if the reset signal has a falling edge, judging that the starting type is a hot restart behavior.
4. The method for determining the power supply startup type according to claim 3, further comprising:
if the shutdown signal has a falling edge, acquiring the shutdown signal again after a preset time and judging whether the shutdown signal has a rising edge again;
if the shutdown signal is judged to have no rising edge again, judging that the starting type is a system shutdown behavior;
and if the shutdown signal is judged to be raised again, judging that the starting type is a cold restart behavior.
5. The method for determining a power supply activation type according to claim 1, wherein temporarily storing the determination result in a FLASH includes:
the CPLD writes the judgment result into the built-in FLASH; or
And the FPGA writes the judgment result into the plug-in FLASH.
6. A device for determining a power-on type, comprising:
the judging module is configured to obtain a starting signal of the power supply based on the CPLD or the FPGA, wherein the starting signal comprises a power supply signal;
the judging module is further configured to judge whether the power signal has a falling edge based on the CPLD or the FPGA, determine that the start type is a first type of behavior if the power signal has no falling edge, determine that the start type is a second type of behavior if the power signal has a falling edge, and further determine that the second type of behavior is a loss behavior of all PSUs;
the register module is configured to send a judgment result to a register based on the CPLD or the FPGA if the first type of behavior is detected;
if the second type of behavior is existed, the register module is further configured to temporarily store the judgment result in a FLASH based on the CPLD or the FPGA, and read the judgment result and send the judgment result to a register when the power is on again;
the recording module is configured to poll the register through I2C based on BMC or CPU to obtain the judgment result and generate a start log based on the judgment result;
and the recording module is also configured to, after generating a start log based on the judgment result, clear the information of the register through the I2C based on the BMC or the CPU if the start log is the first type of behavior, and clear the information of the register through the I2C based on the BMC or the CPU and issue a command to clear the information of the FLASH if the start log is the second type of behavior.
7. A computer device, comprising:
at least one processor; and
a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of any one of the methods 1-5.
8. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 5.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108304299A (en) * | 2018-03-02 | 2018-07-20 | 郑州云海信息技术有限公司 | Server power-up state monitors system and method, computer storage and equipment |
| CN109683696A (en) * | 2018-12-25 | 2019-04-26 | 浪潮电子信息产业股份有限公司 | Fault of server power supply detection system, method, apparatus, equipment and medium |
| CN110515802A (en) * | 2019-08-23 | 2019-11-29 | 苏州浪潮智能科技有限公司 | A kind of monitoring method, system and the associated component of server booting failure |
-
2020
- 2020-07-24 CN CN202010724719.5A patent/CN111858178B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108304299A (en) * | 2018-03-02 | 2018-07-20 | 郑州云海信息技术有限公司 | Server power-up state monitors system and method, computer storage and equipment |
| CN109683696A (en) * | 2018-12-25 | 2019-04-26 | 浪潮电子信息产业股份有限公司 | Fault of server power supply detection system, method, apparatus, equipment and medium |
| CN110515802A (en) * | 2019-08-23 | 2019-11-29 | 苏州浪潮智能科技有限公司 | A kind of monitoring method, system and the associated component of server booting failure |
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