CN111797031B - Method for recording power-on accumulated time of task machine by using EEPROM under condition of no battery - Google Patents
Method for recording power-on accumulated time of task machine by using EEPROM under condition of no battery Download PDFInfo
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- CN111797031B CN111797031B CN202010552930.3A CN202010552930A CN111797031B CN 111797031 B CN111797031 B CN 111797031B CN 202010552930 A CN202010552930 A CN 202010552930A CN 111797031 B CN111797031 B CN 111797031B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3065—Monitoring arrangements determined by the means or processing involved in reporting the monitored data
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
A method for recording the power-on accumulated time of a task machine by using an EEPROM under the condition of no battery is provided, a set of recording system is arranged to finish the storage of the data, the recording system comprises a processor and an EEPROM, the processor is connected with the EEPROM, and a timer for finishing the timing function is arranged in the processor; the accumulated power-on time of the main controller is recorded through the EEPROM, so that the data can be kept when the equipment is powered down. The storage strategy is completed through Ping-Pong storage operation of the EEPROM, data in the EEPROM is refreshed every 5s, and the internal timer and the IIC interface of the processor are used for matching with the EEPROM to complete the data recording function, so that the peripheral circuit is effectively simplified, and the project cost is saved; and the Ping-Pong operation is adopted to store the power-on accumulated time, so that the power-off of the EEPROM can be ensured to successfully record the power-on accumulated time when the EEPROM is refreshed.
Description
Technical Field
The invention relates to the technical field of storage and memory, in particular to a method for recording power-on accumulated time of a task machine by using an EEPROM under the condition of no battery.
Background
With the development and innovation of technology, more and more on-board electronic device processors need to evaluate service life and failure rate. The traditional time recording device is used for completing time accumulation by carrying a small battery on a clock chip, however, the sprung core control processor circuit is generally small and exquisite, the battery and the clock chip circuit are not distributed in a large space, the service life of the battery is generally lower than that of the processor, and the service life of the controller cannot be recorded in a full period.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a method for recording the power-on accumulation time of a task machine by using an EEPROM under the condition of no battery so as to solve the problems in the background technology.
The technical problems solved by the invention are realized by adopting the following technical scheme:
a method for recording the power-on accumulated time of a task machine by using an EEPROM under the condition of no battery comprises the following specific steps:
1) In order to record the power-on accumulation time of the missile-borne controller, a set of recording system is arranged to finish the storage of the data, the recording system comprises a processor and an EEPROM, the processor is connected with the EEPROM through an internal IIC interface to finish the communication of the processor and the EEPROM, and a timer for finishing a timing function is arranged in the processor;
2) The power-on accumulation time of the main controller is recorded through the EEPROM, so that the data can be kept when the equipment is powered down, and in order to prevent the data from being updated to the EEPROM due to sudden power-off of the EEPROM in the process of executing writing operation, the power-on accumulation time data is stored by adopting two addresses, namely 0x0100 of a main equipment address 0x56 and 0x0100 of a slave equipment address 0x57, and the two addresses are mutually backed up so as to prevent the occurrence of data loss recorded in the EEPROM due to accidental power-off of one address;
3) According to the threshold analysis of the power-on accumulation time, one 32-bit data can meet the requirement (more than 136 years), so that the stored value of the power-on accumulation time is stored by one 32-bit data, but one address in the EEPROM can only store one 8-bit data, the 32-bit data is split into 4 8-bit data when stored, the 4-bit data is stored in the first 4 addresses from 0x0100, and in order to ensure the correctness of the data, the checksum of the first 4-bit data is stored in the 5 th address (checksum = byte 1+ byte 2+ byte 3+ byte 4, if the checksum exceeds the 8-bit threshold, the lower 8 bits are taken);
4) Operating the EEPROM for the first time, fully brushing 5 addresses from 0x0100 of the main device address 0x56 to 0x00, fully brushing 5 addresses from 0x0100 of the device address 0x57 to 0x00, and initially powering up the EEPROM for 0 and also for 0 as a checksum (no need for the subsequent operation);
5) And performing Ping-Pong operation storage by using the two addresses, firstly reading accumulated time data stored in the address of the master device and the address of the slave device, calculating the checksum of the master device and the address of the slave device, judging whether the checksum is correct or not, and updating the numerical value according to three conditions of the checksum judgment:
firstly, checking the checksum of two values of a master device address and a slave device address to be correct, comparing the values of the two addresses, taking the larger one of the two addresses as reference data, and updating the larger one of the two addresses into the two addresses;
secondly, the address value checksum of the master device is correct, and the address value checksum of the slave device is wrong, and the address value of the master device is used as reference data to be updated into two addresses;
thirdly, the address value checksum of the master device is wrong, and the address value checksum of the slave device is correct, and the address value of the slave device is used as reference data to be updated into two addresses;
6) After the processor normally operates, refreshing data in the EEPROM every 5s, after the first time of 5s interruption occurs, adding 5s on the basis of the reference time, and then brushing the data into the address of the main equipment; after the second time of 5s interruption occurs, the data in the main equipment address is read out, then the data is added for 5s on the basis of the data, and then the data is written into the slave equipment address, and so on, the ping-pong is written into the EEPROM, and further the task machine power-on accumulated time is recorded by using the EEPROM under the condition of no battery.
The beneficial effects are that: the invention uses the internal timer of the processor and the IIC interface to complete the data recording function by matching with the EEPROM, thereby effectively simplifying the peripheral circuit and saving the project cost; meanwhile, the Ping-Pong address is used for storing data, the phenomenon that the whole stored data is invalid due to power failure when the memory is refreshed and stored is avoided, and the stability of the data storage in the power-on accumulation time is enhanced.
Drawings
FIG. 1 is a schematic diagram showing the composition of a recording system according to a preferred embodiment of the present invention.
FIG. 2 is a schematic diagram of the Ping-Pong operation time in a preferred embodiment of the present invention.
FIG. 3 is a flowchart of a power-up accumulation time of a recording processor according to a preferred embodiment of the present invention.
Detailed Description
The invention is further described with reference to the following detailed drawings in order to make the technical means, the creation characteristics, the achievement of the purpose and the effect of the implementation of the invention easy to understand.
A method for recording the power-on accumulated time of a task machine by using an EEPROM under the condition of no battery comprises the following specific steps:
1) In order to record the power-on accumulation time of the missile-borne controller, a set of recording system is arranged to finish the storage of the data, the composition modules of the recording system are shown in figure 1, the recording system comprises a processor and an EEPROM, the processor is connected with the EEPROM through an internal IIC interface of the processor to finish the communication of the processor and the EEPROM (the EEPROM is M24M 01), and the timing function is finished through a timer arranged in the processor;
2) The power-on accumulation time of the main controller is recorded through the EEPROM, so that the data can be kept when the equipment is powered down, in order to avoid the situation that the data cannot be updated to the EEPROM due to sudden power-off of the EEPROM in the process of executing writing operation, the power-on accumulation time data is stored by adopting two addresses, namely 0x0100 of a main equipment address 0x56 and 0x0100 of a slave equipment address 0x57, and the two addresses are mutually backed up so as to prevent the occurrence of data loss recorded in the EEPROM due to accidental power-off of one address;
3) According to the threshold analysis of the power-on accumulation time, one 32-bit data can meet the requirement (more than 136 years), so that the stored value of the power-on accumulation time is stored by one 32-bit data, but one address in the EEPROM can only store one 8-bit data, the 32-bit data is required to be split into 4 8-bit data, the 4-bit data is stored in the first 4 addresses from 0x0100, and in order to ensure the correctness of the data, the checksum of the first 4-bit data is stored in the 5 th address (checksum = byte 1+ byte 2+ byte 3+ byte 4, and if the stored value exceeds the 8-bit threshold, the stored value takes the lower 8 bits);
4) Operating the EEPROM for the first time, fully brushing 5 addresses from 0x0100 of the main device address 0x56 to 0x00, fully brushing 5 addresses from 0x0100 of the device address 0x57 to 0x00, and initially powering up the EEPROM for 0 and also for 0 as a checksum (no need for the subsequent operation);
5) The storage flow of the Ping-Pong operation by using the two addresses is shown in fig. 3, and each time of power-on, the accumulated time data stored by the two addresses of the address A and the address B are read out firstly, the checksum is calculated, meanwhile, whether the checksum is correct or not is judged, and the numerical value is updated according to three conditions of checksum judgment:
firstly, checking the checksum of two values of an address A and an address B to be correct, comparing the sizes of the two address values, wherein the address A is more than the address B, updating the address A as reference data into the two addresses, the address A is less than the address B, and updating the address B as reference data into the two addresses;
secondly, the address A value checksum is correct, and the address B value checksum is wrong, and the address A value is used as reference data to be updated into two addresses;
thirdly, the address A value checksum is wrong, and the address B value checksum is correct, and the address B value is used as reference data to be updated into two addresses;
6) After the processor normally operates, refreshing data in the EEPROM every 5s, as shown in FIG. 2, after the first time of 5s interruption occurs, adding 5s on the basis of the reference time, and then brushing the data into the address A; after the second time of 5s interruption occurs, the data in the address A is read out firstly, then the data is added for 5s on the basis of the data and then is written into the address B in a brushing way, and the like, the ping-pong is used for writing the EEPROM in a brushing way, so that the electricity accumulation time of the task machine is recorded by using the EEPROM under the condition of no battery.
In this embodiment, the master address 0x56 is address a, and the slave address 0x57 is address B.
Claims (8)
1. A method for recording the power-on accumulated time of a task machine by using an EEPROM under the condition of no battery is characterized by comprising the following specific steps:
1) In order to record the power-on accumulation time of the missile-borne controller, a set of recording system is arranged to finish the storage of data, the recording system comprises a processor and an EEPROM, the processor is connected with the EEPROM, and a timer for finishing a timing function is arranged in the processor;
2) Recording the power-on accumulation time of the main controller through the EEPROM, and storing the power-on accumulation time data by adopting two addresses, wherein the two addresses are 0x0100 of a main device address 0x56 and 0x0100 of a slave device address 0x57, and the two addresses are mutually backed up in order to avoid that the data cannot be updated to the EEPROM due to sudden power-off of the EEPROM in the process of executing writing operation;
3) According to the threshold analysis of the power-on accumulation time, one 32-bit data can meet the requirement, so that the stored value of the power-on accumulation time is stored as one 32-bit data, but one address in the EEPROM can only store one 8-bit data, the 32-bit data is split into 4 8-bit data during storage, the 4-bit data is stored in the first 4 addresses from 0x0100, and in order to ensure the correctness of the data, the checksum of the first 4-byte data is stored in the 5 th address;
4) Firstly operating an EEPROM, and initializing the power-on accumulated time of the main equipment address and the auxiliary equipment address;
5) Performing Ping-Pong operation storage by using two addresses, firstly reading accumulated time data stored in a master device address and a slave device address, calculating a checksum of the master device address and the slave device address, judging whether the checksum is correct or not, and updating a numerical value according to a checksum judgment result;
6) After the processor operates normally, refreshing the data in the EEPROM every same time, after the interruption of the same time of the first time occurs, adding the same time on the basis of the reference time, and then refreshing the data to the address of the main equipment; after the same time interruption of the second timing occurs, the data in the main equipment address is read out, then the data is added with the same time on the basis of the data and then is written into the slave equipment address, and the like, the ping-pong is written into the EEPROM, and further the task machine power-on accumulated time is recorded by the EEPROM under the condition of no battery.
2. The method of claim 1, wherein in step 1), the processor is connected to the EEPROM via its internal IIC interface.
3. A method of recording the power-on accumulation time of a task machine using an EEPROM without battery as in claim 1 wherein in step 3) the checksum = byte 1+ byte 2+ byte 3+ byte 4.
4. The method of claim 1, wherein in step 3), the stored value of the power-on accumulation time exceeds an 8-bit threshold and takes the lower 8 bits.
5. The method for recording the power-on accumulated time of the task machine by using the EEPROM under the condition of no battery as claimed in claim 1, wherein in the step 4), the initialization process of the power-on accumulated time of the master device address and the slave device address is as follows: all of the 5 addresses from 0x0100 of the master address 0x56 are written to 0x00, all of the 5 addresses from 0x0100 of the device address 0x57 are written to 0x00, the initial power-on integration time is 0, and the checksum is also 0.
6. The method for recording the power-on accumulated time of the task machine by using the EEPROM under the condition of no battery as claimed in claim 1, wherein in the step 5), the numerical value is updated according to the checksum judgment result, specifically comprising the following steps:
firstly, checking the checksum of two values of a master device address and a slave device address to be correct, comparing the values of the two addresses, taking the larger one of the two addresses as reference data, and updating the larger one of the two addresses into the two addresses;
secondly, the address value checksum of the master device is correct, and the address value checksum of the slave device is wrong, and the address value of the master device is used as reference data to be updated into two addresses;
third, the master address value checksum is incorrect and the slave address value checksum is correct, then the slave address value is updated to the two addresses as reference data.
7. The method of claim 1, wherein in step 6), the same time is 4-6 s.
8. The method of recording the power-on accumulation time of a mission machine using an EEPROM without a battery as claimed in claim 7, wherein the same time is 5s.
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| CN107682088A (en) * | 2017-09-07 | 2018-02-09 | 安徽皖通邮电股份有限公司 | A kind of method of recording light module runtime |
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| ATE381061T1 (en) * | 2005-03-08 | 2007-12-15 | Bosch Gmbh Robert | METHOD AND APPARATUS FOR REWRITING A SECTOR USING BOOTLOADER SOFTWARE IN A SECTOR-ERASABLE NON-VOLATILE SEMICONDUCTOR MEMORY |
| KR101321472B1 (en) * | 2007-07-23 | 2013-10-25 | 삼성전자주식회사 | Nonvolatile memory device and promgramming method thereof |
| CN101318489B (en) * | 2008-05-07 | 2011-09-21 | 中国科学院电工研究所 | Vehicle mounted battery management system control method |
| WO2015103483A1 (en) * | 2014-01-03 | 2015-07-09 | Mc10, Inc. | Integrated devices for low power quantitative measurements |
| CN105159598B (en) * | 2015-06-30 | 2018-11-20 | 广州市邦沃电子科技有限公司 | A method of it is read in arbitrary equipment and uses total time |
| CN109490618B (en) * | 2018-09-30 | 2020-12-15 | 宁波三星智能电气有限公司 | Method for supplementing load curve of electric energy meter |
| CN111159057A (en) * | 2019-12-11 | 2020-05-15 | 江西洪都航空工业集团有限责任公司 | System and method for recording accumulated power-on times of task machine under battery-free condition |
| CN111124093A (en) * | 2019-12-17 | 2020-05-08 | 中科芯集成电路有限公司 | Time-adjustable power-down data storage circuit and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106708674A (en) * | 2016-11-18 | 2017-05-24 | 中国兵器装备集团自动化研究所 | Method for recording accumulated power-on time of circuit board |
| CN107682088A (en) * | 2017-09-07 | 2018-02-09 | 安徽皖通邮电股份有限公司 | A kind of method of recording light module runtime |
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