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CN111696928B - 半导体封装结构及其制造方法 - Google Patents

半导体封装结构及其制造方法 Download PDF

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Publication number
CN111696928B
CN111696928B CN201910196541.9A CN201910196541A CN111696928B CN 111696928 B CN111696928 B CN 111696928B CN 201910196541 A CN201910196541 A CN 201910196541A CN 111696928 B CN111696928 B CN 111696928B
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China
Prior art keywords
chip
conductor
temporary carrier
conductive layer
carrier plate
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CN201910196541.9A
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CN111696928A (zh
Inventor
倪庆羽
刘扬伟
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Qingdao New Core Technology Co ltd
Futaihua Industry Shenzhen Co Ltd
Original Assignee
Qingdao New Core Technology Co ltd
Futaihua Industry Shenzhen Co Ltd
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Priority to CN201910196541.9A priority Critical patent/CN111696928B/zh
Priority to US16/448,098 priority patent/US11569195B2/en
Publication of CN111696928A publication Critical patent/CN111696928A/zh
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Publication of CN111696928B publication Critical patent/CN111696928B/zh
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Abstract

一种半导体封装结构，包括至少一导电体、一导电层、至少一芯片及一封胶体，所述导电体设于所述导电层及所述芯片之间并将所述导电层与所述芯片电性连接，所述封胶体包覆所述芯片的所有外表面。本发明通过在暂时载板上设置导电层，同时将所述导电层与芯片通过具有一定高度的导电体电性连接，让芯片与导电层之间存在间隙，使得封胶体可以包覆所述芯片的所有外表面，有利于避免芯片破损的发生。

Description

半导体封装结构及其制造方法
技术领域
本发明涉及一种半导体封装结构及其制造方法。
背景技术
现有的半导体芯片封装过程中通常会使用暂时玻璃载板来支撑与定位半导体芯片，半导体芯片封装好后，再移除该暂时玻璃载板，但是移除暂时玻璃载板后会使得芯片的背面直接裸露在外，很容易造成半导体芯片从背面发生损伤。
发明内容
有鉴于此，有必要提供一种半导体封装结构及其制造方法，能够避免半导体芯片破损，从而解决上述问题。
一种半导体封装结构，包括至少一导电体、至少一导电层、一芯片及一封胶体，所述芯片与所述导电层相对且相距设置，所述导电体设于所述导电层及所述芯片之间并将所述导电层与所述芯片电性连接，所述封胶体包覆所述芯片的所有外表面。
进一步地，所述导电体的高度大于40μm。
进一步地，所述导电体包括一铜锡共晶层。
进一步地，所述封胶体形成于所述导电层与所述芯片朝向所述导电层的表面之间的除所述导电体外的间隙。
一种半导体封装结构制造方法，包括如下步骤：
提供一基板，所述基板包括多个单元区域。
于每一单元区域上形成一导电层以获得一第一暂时载板。
切割所述第一暂时载板以获得多个第二暂时载板，每一第二暂时载板包括至少一具有所述导电层的单元区域。
在每一第二暂时载板的导电层上焊接一芯片，所述焊接在所述芯片与所述导电层之间形成至少一导电体，所述导电体使所述芯片与所述导电层相距设置。
封装所述芯片以形成一封胶体，所述封胶体包覆所述芯片的所有外表面，得到包括所述封胶体、所述芯片、所述导电层以及所述导电体在内的中间体。
将所述中间体与所述第二暂时载板分离以获得所述半导体封装结构。
进一步地，所述导电层通过粘接、溅镀、电镀中的一种形成于所述基板。
进一步地，所述导电层与所述芯片焊接前，所述制造方法还包括：在所述导电层朝向所述芯片的表面设置至少一引脚，所述芯片于所述引脚对应的位置处设有至少一凸起，所述引脚与所述凸起通过回流焊的方式焊接形成所述导电体，所述导电体的高度大于40μm。
进一步地，所述引脚的材质选自铜或锡的中的一种，所述凸起的材质选自铜或锡中的另一种，焊接后，所述导电体上所述引脚与所述凸起接触的区域形成有铜锡共晶层。
进一步地，在切割所述第一暂时载板以获得多个第二暂时载板后，所述制造方法还包括：
将每一所述第二暂时载板的周边用一金属框架包裹，所述金属框架上设有若干个固定孔。
以及通过所述固定孔将具有所述金属框架中的所述第二暂时载板固定于一载物台上。
本发明提供的半导体封装结构通过在暂时载板上设置导电层，同时将所述导电层与芯片通过具有一定高度的导电体电性连接，让芯片与导电层之间存在间隙，使得封胶体可以包覆所述芯片的所有外表面，有利于避免芯片破损的发生。
附图说明
图1为本发明提供的半导体封装结构的截面示意图。
图2A为本发明提供的基板的截面示意图。
图2B为在图2A的基板上形成导电层后得到的第一暂时载板的截面示意图。
图2C为图2B所示的第一暂时载板的俯视图。
图2D为对图2B所述的第一暂时载板进行分割得到的第二暂时载板的俯视图。
图2E为在图2D所示的第二暂时载板上焊接芯片后的示意图。
主要元件符号说明
半导体封装结构 100
导电体 10
导电层 20
引脚 21
芯片 30
凸起 31
封胶体 40
基板 50
单元区域 51
第一暂时载板 60
第二暂时载板 70
金属框架 80
固定孔 81
如下具体实施方式将结合上述附图进一步说明本发明。
具体实施方式
下面将结合本发明实施方式中的附图，对本发明实施方式中的技术方案进行清楚、完整地描述，显然，所描述的实施方式仅仅是本发明一部分实施方式，而不是全部的实施方式。基于本发明中的实施方式，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施方式，都属于本发明保护的范围。
需要说明的是，当组件被称为“固定于”另一个组件，它可以直接在另一个组件上或者也可以存在居中的组件。当一个组件被认为是“连接”另一个组件，它可以是直接连接到另一个组件或者可能同时存在居中组件。当一个组件被认为是“设置于”另一个组件，它可以是直接设置在另一个组件上或者可能同时存在居中组件。本文所使用的术语“竖直的”、“水平的”以及类似的表述只是为了说明的目的。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施方式的目的，不是旨在于限制本发明。本文所使用的术语“和/或”包括一个或多个相关的所列项目的任意的和所有的组合。
请参见图1，一种半导体封装结构100，包括至少一导电体10、至少一导电层20、一芯片30及一封胶体40。所述芯片30与所述导电层20相距设置，所述导电体10设于所述导电层20及所述芯片30之间并将所述导电层20与所述芯片30电性连接，所述封胶体40包覆所述芯片30的所有外表面。
进一步地，所述导电体10的高度大于40μm。通过设置导电体10的高度大于40μm，使得所述芯片30远离所述导电层20，以便所述封胶体40形成于所述导电层20与所述芯片30朝向所述导电层20的一面与所述导电层20之间除所述导电体10之外的间隙。如此，避免芯片30的表面由于裸露在外而导致破损。
进一步地，所述导电体10包括一铜锡共晶层(图未示)，所述铜锡共晶层可降低形成所述导电体10的温度，同时增加所述导电体10微观结构的稳定性。
请一并参见图2A至图2E，一种半导体封装结构100的制造方法，包括如下步骤：
S1:如图2A所示，提供一基板50，所述基板50包括多个单元区域51(如图2C所示)。
S2：如2B、2C所示，在每一单元区域51上形成一导电层20以获得一第一暂时载板60。
S3：如图2D所示，切割所述第一暂时载板60以获得多个第二暂时载板70，每一第二暂时载板70包括至少一具有所述导电层20的单元区域51。
S4:如图2D所示，将所述第二暂时载板70的周边用一金属框架80包裹，所述金属框架80上设有若干个固定孔81，通过所述固定孔81将具有所述金属框架80的所述第二暂时载板70固定在一载物台(图未示)上；
S5:如图2E所示，在每一导电层20上焊接一芯片30，所述焊接用于在所述芯片30与所述导电层20之间形成一导电体10，所述导电体10使所述芯片30与所述导电层20相距设置。
S6:如图1所示，封装所述芯片30以形成一封胶体40，所述封胶体40包覆所述芯片30的所有外表面以形成包括所述封胶体40、所述芯片30、所述导电层20以及所述导电体10在内的中间体(图未标)，将所述中间体与固定于所述载物台上的所述第二暂时载板70的所述基板50分离(此时，所述金属框架80亦与所述中间体分离并留在所述基板50上)，切割，即获得所述半导体封装结构100。
其中，在S1中，每一所述单元区域51用于形成一个所述半导体封装结构100，其中，一个所述基板50内的所有所述单元区域51的面积之和小于所述基板50的面积，而且每一所述单元区域51的面积稍大于一个所述芯片30的面积。
进一步地，所述基板50的材质为任何一种绝缘的具有承载作用的材料，在本实施例中，所述基板50的材质为玻璃。在其他实施例中，所述基板50的材质还可以为聚酰亚胺(polyimide，PI)、聚对苯二甲酸乙二醇酯(Polyethylene Terephthalate，PET)、聚萘二甲酸乙二醇酯(Polyethylene Naphthalate，PEN)或其他树脂硬质材料。
在S2中，通过粘接的方法于所述基板50的每一所述单元区域51内形成所述导电层20，所述导电层20用于构成所述半导体封装结构100的一部分。所述导电层20可为一铜箔。在其他实施例中，形成所述导电层20的方法还可以是溅镀、电镀及蚀刻中的一种。
在其它实施例中，所述导电层20还可以为重配置电路层(RedistributionLayer)，所述导电层20可以是多层金属复合结构(例如，金、镍、铜等金属材质复合而成的至少一层的复合结构)。
在S3中，通过激光切割技术将所述第一暂时载板60切割成多个所述第二暂时载板70，在本实施方式中，所述第二暂时载板70可以包括多个单元区域51，通过将所述第一暂时载板60分割成多个所述第二暂时载板70，避免直接使用较大的第一暂时载板60制作所述半导体封装结构100，从而减低了由第一暂时载板60的破损造成全部半导体封装结构报废的风险。
在S5中，将所述导电层20与所述芯片30通过回流焊的方式焊接。进一步地，如图2B所示，所述导电层20与所述芯片30焊接前，先在所述导电层20朝向所述芯片30的一侧设置至少一引脚21，所述引脚21的材质可为铜。所述芯片30于所述引脚21对应的位置处设有至少一凸起31，所述凸起31可以为锡材质。所述引脚21与所述凸起31通过回流焊的方式焊接熔化并形成所述导电体10，所述导电体10在所述凸起31与所述引脚21相接处形成铜锡共晶层。所述导电体10的高度大于40μm。
在S6中，通过注塑成型的方式形成所述封胶体40，注塑成型的过程为：首先提供一模具(图未示)，该模具包括一模穴(图未示)及一注胶通道(图未示)，将包含有所述导电层20及所述芯片30的所述第二暂时载板70容置于所述模穴内；然后，通过该注胶通道向该模穴内注入胶体，使胶体覆盖所述芯片30并填充所述导电层20及所述芯片30之间的间隙，使得该胶体包覆多个所述导电体10及所述芯片30；接着，固化所述胶体，从而形成所述封胶体40；之后，将形成有所述封胶体40的所述半导体封装结构100从所述模穴中取出来。
本发明通过在暂时载板上设置导电层，同时将所述导电层与芯片通过具有一定高度的导电体电性连接，让芯片与导电层之间存在间隙，使得封胶体可以包覆所述芯片的所有外表面，有利于避免芯片破损的发生。
另外，本技术领域的普通技术人员应当认识到，以上的实施方式仅是用来说明本发明，而并非用作为对本发明的限定，只要在本发明的实质精神范围之内，对以上实施例所作的适当改变和变化都落在本发明要求保护的范围之内。

Claims (4)

1.一种半导体封装结构制造方法，其特征在于，包括如下步骤：
提供一基板，所述基板包括多个单元区域；
于每一单元区域上形成一导电层以获得一第一暂时载板；
切割所述第一暂时载板以获得多个第二暂时载板，每一第二暂时载板包括多个具有所述导电层的单元区域；
将每一所述第二暂时载板的周边用一金属框架包裹，所述金属框架上设有若干个固定孔；
通过所述固定孔将具有所述金属框架中的所述第二暂时载板固定于一载物台上；
在每一第二暂时载板的导电层上焊接一芯片，所述焊接在所述芯片与所述导电层之间形成至少一导电体，所述导电体的高度大于40μm，所述导电体使所述芯片与所述导电层相距设置；
封装所述芯片以形成一封胶体，所述封胶体包覆所述芯片的所有外表面，得到包括所述封胶体、所述芯片、所述导电层以及所述导电体在内的中间体；
将所述中间体与所述第二暂时载板分离以获得所述半导体封装结构。
2.如权利要求1所述的制造方法，其特征在于，所述导电层通过粘接、溅镀、电镀中的一种形成于所述基板。
3.如权利要求1所述的制造方法，其特征在于，所述导电层与所述芯片焊接前，所述制造方法还包括：在所述导电层朝向所述芯片的表面设置至少一引脚，所述芯片于所述引脚对应的位置处设有至少一凸起，所述引脚与所述凸起通过回流焊的方式焊接形成所述导电体。
4.如权利要求3所述的制造方法，其特征在于，所述引脚的材质选自铜或锡的中的一种，所述凸起的材质选自铜或锡中的另一种，焊接后，所述导电体上所述引脚与所述凸起接触的区域形成有铜锡共晶层。
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