CN111681961A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN111681961A CN111681961A CN202010734076.2A CN202010734076A CN111681961A CN 111681961 A CN111681961 A CN 111681961A CN 202010734076 A CN202010734076 A CN 202010734076A CN 111681961 A CN111681961 A CN 111681961A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 137
- 238000000034 method Methods 0.000 title claims abstract description 90
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 91
- 229910052751 metal Inorganic materials 0.000 claims abstract description 84
- 239000002184 metal Substances 0.000 claims abstract description 84
- 238000005530 etching Methods 0.000 claims abstract description 49
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- 229910021332 silicide Inorganic materials 0.000 claims abstract description 41
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- 238000001312 dry etching Methods 0.000 claims abstract description 13
- 239000007789 gas Substances 0.000 claims description 36
- 150000004767 nitrides Chemical class 0.000 claims description 15
- 238000000137 annealing Methods 0.000 claims description 13
- 238000005468 ion implantation Methods 0.000 claims description 13
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
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- 229910052715 tantalum Inorganic materials 0.000 claims description 7
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 7
- 239000010936 titanium Substances 0.000 claims description 7
- 229910052719 titanium Inorganic materials 0.000 claims description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
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- 229910001873 dinitrogen Inorganic materials 0.000 claims description 4
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- 238000011065 in-situ storage Methods 0.000 claims description 4
- 125000006850 spacer group Chemical group 0.000 claims description 4
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 4
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- 229910002090 carbon oxide Inorganic materials 0.000 claims description 3
- 239000011737 fluorine Substances 0.000 claims description 3
- 229910052731 fluorine Inorganic materials 0.000 claims description 3
- WPBNNNQJVZRUHP-UHFFFAOYSA-L manganese(2+);methyl n-[[2-(methoxycarbonylcarbamothioylamino)phenyl]carbamothioyl]carbamate;n-[2-(sulfidocarbothioylamino)ethyl]carbamodithioate Chemical compound [Mn+2].[S-]C(=S)NCCNC([S-])=S.COC(=O)NC(=S)NC1=CC=CC=C1NC(=S)NC(=O)OC WPBNNNQJVZRUHP-UHFFFAOYSA-L 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
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- 230000007547 defect Effects 0.000 abstract description 6
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- 238000005229 chemical vapour deposition Methods 0.000 description 3
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- 229910052757 nitrogen Inorganic materials 0.000 description 3
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
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- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
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- 238000012876 topography Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- RPAJSBKBKSSMLJ-DFWYDOINSA-N (2s)-2-aminopentanedioic acid;hydrochloride Chemical class Cl.OC(=O)[C@@H](N)CCC(O)=O RPAJSBKBKSSMLJ-DFWYDOINSA-N 0.000 description 1
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
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- 238000009792 diffusion process Methods 0.000 description 1
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- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
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- 229910021424 microcrystalline silicon Inorganic materials 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
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- 239000001272 nitrous oxide Substances 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a manufacturing method of a semiconductor device, which is characterized in that a side wall material layer is formed on the surface of a semiconductor substrate and the top surface and the side surface of a grid structure; then, etching the side wall material layer by adopting a dry etching process until the top surface of the grid structure and the surface of the semiconductor substrate are exposed so as to form a side wall structure on the side surface of the grid structure; and then, forming metal silicide on the exposed surface of the semiconductor substrate and the top surface of the gate structure. The side wall material layer is etched through the dry etching process and stops on the top surface of the grid structure and the surface of the semiconductor substrate, so that the side wall material layer can be prevented from remaining on the semiconductor substrate, and the surface appearance of the metal silicide can be smooth when the metal silicide is formed subsequently. Therefore, the concave-convex defect of the surface of the metal silicide can be avoided, and the uniformity of the surface of the metal silicide is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a semiconductor device.
Background
In the manufacturing process of semiconductor devices, it is now required to form metal silicide in specific areas for reducing contact resistance. The conventional manufacturing process flow of the semiconductor device generally includes: firstly, providing a semiconductor substrate, wherein a grid electrode is formed on the semiconductor substrate; then, depositing a side wall material layer on the semiconductor substrate and the grid; then, etching the side wall material layer to form a grid side wall; and then, performing a wet etching process to remove the residual side wall material layer on the semiconductor substrate and the grid electrode.
However, in the above manufacturing process of the semiconductor device, when a wet etching process is performed, the etching solution used is less (if the etching solution or the etching amount is too much, the topography of the gate sidewall is damaged, and when source and drain ion implantation is performed subsequently, the ion implantation may break down the gate sidewall, thereby shortening the conductive channel), so that the etching effect cannot be achieved, a sidewall material layer may remain on the surface of the semiconductor substrate and the surface of the gate, and when a metal silicide is formed subsequently on the remaining sidewall material layer, a concave-convex defect on the surface of the metal silicide may be caused, that is, the surface uniformity of the metal silicide may be affected, thereby affecting the contact between the metal silicide and the source region, the drain region and the gate structure, and further causing failures such as short circuit or open circuit of the semiconductor device.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor device, which aims to solve the problem of concave-convex defects on the surface of a metal silicide so as to improve the surface uniformity of the metal silicide.
In order to solve the above technical problem, the present invention provides a method for manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate, wherein a grid structure is formed on the semiconductor substrate;
forming side wall material layers on the surface of the semiconductor substrate and the top surface and the side surfaces of the grid structure;
etching the side wall material layer by adopting a dry etching process until the top surface of the grid structure and the surface of the semiconductor substrate are exposed so as to form a side wall structure on the side surface of the grid structure;
and forming metal silicide on the exposed surface of the semiconductor substrate and the top surface of the gate structure.
Optionally, in the manufacturing method of the semiconductor device, the side wall material layer includes a first oxide layer, a nitride layer, and a second oxide layer, which are sequentially stacked, and the first oxide layer covers the surface of the semiconductor substrate and the top surface and the side surface of the gate structure.
Optionally, in the manufacturing method of the semiconductor device, the method for dry etching the spacer material layer includes:
etching the first oxide layer by using a first etching gas until the surface of the nitride layer is exposed;
and etching the nitride layer and the second oxide layer by using a second etching gas until the top surface of the grid structure and the surface of the semiconductor substrate are exposed.
Optionally, in the manufacturing method of the semiconductor device, the flow rates of the first etching gas and the second etching gas are both 5sccm to 600 sccm; the first etching gas is one or more of nitrogen gas, fluorine gas and carbon oxide gas; the second etching gas is a mixed gas of one or more of hydrogen gas, oxygen gas and carbon fluoride gas.
Optionally, in the manufacturing method of the semiconductor device, after the forming of the sidewall structure and before the forming of the metal silicide, the manufacturing method of the semiconductor device further includes:
performing ion implantation on the exposed semiconductor to form a source region and a drain region, wherein the source region and the drain region are respectively positioned at two sides of the grid structure; and the number of the first and second groups,
and repairing the surface of the semiconductor substrate after the ion implantation process is performed.
Optionally, in the method for manufacturing a semiconductor device, the repair process includes at least one of an annealing process, an oxidation process, and an oxynitridation process.
Optionally, in the manufacturing method of the semiconductor device, the method for forming the metal silicide includes:
forming metal layers on the exposed top surface of the gate structure, the semiconductor substrate and the surfaces of the side wall structures;
performing an annealing process on the semiconductor substrate to react the metal in the metal layer with the silicon in the gate structure and the semiconductor substrate and form a metal silicide;
and performing a cleaning process on the semiconductor substrate to remove the unreacted metal layer on the top surface of the gate structure, the semiconductor substrate and the surface of the side wall structure.
Optionally, in the manufacturing method of the semiconductor device, a material of the metal layer is at least one of titanium, zirconium, tantalum, tungsten, manganese, nickel, and yttrium.
Optionally, in the method for manufacturing a semiconductor device, before forming the metal layer, the method for manufacturing a semiconductor device further includes forming an adhesion layer, where the adhesion layer covers the exposed surface of the semiconductor substrate, and after forming the metal layer, the metal layer covers the adhesion layer.
Optionally, in the method for manufacturing a semiconductor device, the adhesion layer includes at least one of a titanium layer, a titanium nitride layer, a tantalum layer, and a tantalum nitride layer.
In the manufacturing method of the semiconductor device provided by the invention, side wall material layers are formed on the surface of the semiconductor substrate and the top surface and the side surface of the grid structure; then, etching the side wall material layer by adopting a dry etching process until the top surface of the grid structure and the surface of the semiconductor substrate are exposed so as to form a side wall structure on the side surface of the grid structure; and then, forming metal silicide on the exposed surface of the semiconductor substrate and the top surface of the gate structure. And etching the side wall material layer by the dry etching process, and stopping on the top surface of the gate structure and the surface of the semiconductor substrate, so that the side wall material layer can be prevented from remaining on the semiconductor substrate, and the surface of the metal silicide can be smooth in appearance when the metal silicide is formed subsequently. Therefore, the concave-convex defect of the surface of the metal silicide can be avoided, and the uniformity of the surface of the metal silicide is improved. Furthermore, as the side wall material layer is etched by adopting the dry etching process, compared with the prior art, the appearance of the side wall structure cannot be damaged.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 2 to 6 are schematic structural diagrams formed in a method of manufacturing a semiconductor device according to an embodiment of the present invention;
wherein the reference numerals are as follows:
100-a semiconductor substrate; 110-a gate structure; 120-side wall material layer; 130-side wall structure; 140-a source region; 150-a drain region; 160-a metal layer; 170-metal silicide.
Detailed Description
The following describes a method for manufacturing a semiconductor device according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a semiconductor device according to an embodiment of the invention. As shown in fig. 1, the method of manufacturing the semiconductor device includes:
step S1: providing a semiconductor substrate, wherein a grid structure is formed on the semiconductor substrate;
step S2: forming side wall material layers on the surface of the semiconductor substrate and the top surface and the side surfaces of the grid structure;
step S3: etching the side wall material layer by a dry method until the top surface of the grid structure and the surface of the semiconductor substrate are exposed so as to form a side wall structure on the side surface of the grid structure;
step S4: and forming metal silicide on the exposed surface of the semiconductor substrate and the top surface of the gate structure.
Fig. 2 to fig. 6 are schematic structural diagrams formed in the method for manufacturing a semiconductor device according to an embodiment of the present invention. Next, the above steps will be described in more detail with reference to fig. 2 to 6.
As shown in fig. 2, first, step S1 is performed to provide a semiconductor substrate 100, wherein the semiconductor substrate 100 has a gate structure 110 formed thereon. Shallow trench isolation structures (not shown) are formed in the semiconductor substrate 100. In addition, the surface of the semiconductor substrate 100 has exposed silicon regions, which may be a source region 140 and a drain region 150 formed in the semiconductor substrate 100 and used as semiconductor devices, and the silicon regions may be single crystal silicon, amorphous silicon, polycrystalline silicon, or microcrystalline silicon.
The gate structure 110 includes a gate dielectric layer and a gate located on the gate dielectric layer, the gate dielectric layer is silicon oxide and/or silicon nitride, and may also be high-K dielectrics such as aluminum oxide and hafnium oxide, or includes a combination of the high-K dielectrics and silicon oxide or silicon nitride; the gate may be a polysilicon gate, and in other embodiments of the present invention, the gate may be a metal gate.
Then, as shown in fig. 3, step S2 is performed to form a sidewall material layer 120 on the surface of the semiconductor substrate 100 and the top and side surfaces of the gate structure 110. Specifically, the sidewall material layer 120 includes a first oxide layer, a nitride layer, and a second oxide layer stacked in sequence, where the first oxide layer covers the surface of the semiconductor substrate 100 and the top surface and the side surfaces of the gate structure 110. The first oxide layer and the second oxide layer may be, for example, silicon dioxide layers, and the nitride layer may be a silicon nitride layer. More specifically, the sidewall material layer 120 may be formed by one or more of a plasma chemical vapor deposition process, an atomic layer deposition process, a low pressure chemical vapor deposition process, and an atmospheric pressure chemical vapor deposition process. In this embodiment, the sidewall material layer 120 is preferably formed by a low-pressure vapor deposition process and an atomic layer deposition process, so that the first sidewall material layer 120 has a better thickness uniformity. For example, the first oxide layer and the second oxide layer may be formed using a Tetraethylorthosilicate (TEOS) low pressure vapor deposition (LPCVD) process, and the nitride layer may be formed using an atomic layer deposition process.
In addition, after the sidewall material layer 120 is formed, rapid annealing may be performed on the semiconductor substrate 100 to improve the compactness of the sidewall material layer. In this embodiment, the process temperature for forming the sidewall material layer 120 may be 200 ℃ to 900 ℃, the annealing temperature may be 500 ℃ to 1300 ℃, the annealing time may be 30s to 100s, and the annealing temperature in this embodiment is 1150 ℃.
Next, as shown in fig. 4, step S3 is performed, and the sidewall material layer 120 is etched by using a dry etching process until the top surface of the gate structure 110 and the surface of the semiconductor substrate 100 are exposed, so as to form a sidewall structure 130 on the side surface of the gate structure 110. That is, the sidewall structure 130 includes at least a portion of the sidewall material layer 120. The dry etching process may be, for example, an anisotropic plasma etching process or a reactive ion etching process.
Specifically, the method for etching the sidewall material layer 120 includes: etching the first oxide layer by using a first etching gas until the surface of the nitride layer is exposed (namely the surface of the nitride layer positioned on the top surface of the grid structure and the surface of the semiconductor substrate is exposed), and immediately etching and stopping on the surface of the nitride layer; and etching the nitride layer and the second oxide layer by using a second etching gas until the top surface of the gate structure 110 and the surface of the semiconductor substrate 100 are exposed, namely etching and stopping on the top surface of the gate structure 110 and the surface of the semiconductor substrate 100. Therefore, the sidewall material layer 120 on the top surface of the gate structure 110 and the surface of the semiconductor substrate 100 can be completely removed, so as to avoid the residue of the sidewall material layer 120, thereby avoiding affecting the uniformity of the subsequently formed metal silicide 170. In addition, since the sidewall material layer 120 is etched by a dry method, when the nitride layer and the second oxide layer are etched, the shape of the etched first nitride layer can be prevented from being damaged, so that the subsequently formed sidewall structure 130 has a better shape, and breakdown of a subsequent ion implantation process can be avoided.
Wherein the flow rates of the first etching gas and the second etching gas are both 5sccm to 600 sccm. If the gas flow of the first etching gas and the second etching gas is too small, the etching is easily too slow, the etching time is increased, and if the gas flow is too large, the stability and uniformity of the etching rate are easily deteriorated. Therefore, in this embodiment, the gas flow rates of the first etching gas and the second etching gas are preferably set to be 5sccm to 600 sccm. The first etching gas is at least one of nitrogen gas, fluorine gas and carbon oxide gasOne, e.g. C4F8Or CO, etc.; the second etching gas is at least one of hydrogen gas, oxygen gas and carbon fluoride gas, for example, CF4Or CHF3。
Next, as shown in fig. 5, an ion implantation process is performed on the exposed semiconductor to form a source region 140 and a drain region 150, where the source region 140 and the drain region 150 are respectively located at two sides of the gate structure 110. Further, after the ion implantation process is performed, ions implanted by the ion implantation process may be activated through an annealing process, so that the ions implanted by the ion implantation process are diffused into the semiconductor substrate 100 below the gate structure 110, and meanwhile, lattice damage caused by the ion implantation process to the surface of the semiconductor substrate 100 is repaired, thereby forming the source region 140 or the drain region 150. Then, a repair process is performed on the surface of the semiconductor substrate 100 after the ion implantation process is performed. The repair process is mainly to repair the dry etching damage of the surface of the semiconductor substrate 100. Specifically, the dry etching damage is mainly that, in the process of etching the sidewall material layer 120, in order to ensure that the top surface of the gate structure 110 and the sidewall material layer 120 on the surface of the semiconductor substrate 100 are completely removed, a certain amount of over-etching is required, so that the surface of the semiconductor substrate 100 is damaged in the etching process, that is, a recess is formed. Thus, the damage of the surface of the semiconductor substrate 100 can be repaired using the repair process.
Further, the repair process includes at least one of a thermal oxidation process, an in-situ steam production process, and a nitrogen oxidation process. Specifically, the thermal oxidation process may be performed on the semiconductor substrate 100 by an oxidation furnace or a rapid thermal annealing chamber under an oxygen gas at 600 ℃ to 1100 ℃; the in-situ steam generation (ISSG) process is a process of introducing hydrogen and oxygen into a rapid thermal annealing chamber, synthesizing water vapor in situ on the surface of the semiconductor substrate 100, and then combining the water vapor with silicon and the like on the surface of the semiconductor substrate 100 to form an oxide; the rapid thermal nitrogen oxidation process adopts a process gas nitrous oxide, and the process temperature is 800-1300 ℃. For example, 1000 c, for an annealing time of 20s to 160s, for example, 70s, to repair the surface of the semiconductor substrate 100. The repairing process of this embodiment preferably employs a thermal oxidation process.
Next, as shown in fig. 6, step S4 is performed to form a metal silicide 170 on the exposed surface of the semiconductor substrate 100 and the top surface of the gate structure 110. Specifically, the method for forming the metal silicide 170 includes: forming a metal layer 160 on the exposed top surface of the gate structure 110, the semiconductor substrate 100 and the surface of the sidewall structure 130; annealing the semiconductor substrate 100 to react the metal in the metal layer 160 with the silicon in the gate structure 110 and the semiconductor substrate 100 and form a metal silicide 170; and performing a cleaning process on the semiconductor substrate 100 to remove the unreacted metal layer 160 on the top surface of the gate structure 110, the semiconductor substrate 100, and the surface of the sidewall structure 130. Since, in step S3, the sidewall material layer 120 on the top surface of the gate structure 110 and the surface of the semiconductor substrate 100 is completely removed, the metal layer 160 with a relatively flat surface can be formed on the top surface of the gate structure 110 and the surface of the semiconductor substrate 100, so that a metal silicide with a relatively flat surface can be formed in a subsequent process.
Specifically, the metal layer 160 may be formed by a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, an Atomic Layer Deposition (ALD) process, or the like, and the material of the metal layer 160 may be at least one of titanium, zirconium, tantalum, tungsten, manganese, nickel, and yttrium. The metal layer 160 of the present embodiment is preferably an alloy of two or more metals. Finally, preferably, before forming the metal layer 160, an adhesion layer may be formed, the adhesion layer covers the exposed surface of the semiconductor substrate 100, and after forming the metal layer 160, the metal layer 160 covers the adhesion layer. The adhesion layer may enhance adhesion of the subsequently deposited metal layer 160 to the surface of the semiconductor substrate 100 (here, the source region 140 and the drain region 150), increase flatness of the surface of the metal layer 160, and may serve to limit diffusion of metal in the subsequently deposited metal layer 160 to places other than the source region 140 and the drain region 150. The adhesion layer includes at least one of a titanium layer, a titanium nitride layer, a tantalum layer, and a tantalum nitride layer. That is, the adhesion layer may be any one of a titanium layer, a titanium nitride layer, a tantalum layer and a tantalum nitride layer, or a multi-layer stacked composite structure.
Next, the semiconductor substrate 100 may be annealed using a low temperature rapid annealing process to react the metal in the metal layer 160 with the gate structure 110 and the silicon in the semiconductor substrate 100 (i.e., silicon in the silicon region of the semiconductor substrate) and form a metal silicide 170. In this embodiment, the annealing treatment is preferably performed using a gas containing hydrogen or nitrogen. Thereby eliminating trace oxygen in the annealing environment and preventing the metal in the metal layer 160 from being oxidized, further avoiding or reducing the surface defects of the metal silicide 170, and increasing the flatness of the surface topography of the metal silicide 170, thereby further improving the surface uniformity of the metal silicide 170.
It should be noted that, in other embodiments of the present invention, since the gate of the gate structure 110 is not a silicon gate made of polysilicon, monocrystalline silicon, amorphous silicon, or the like, for example, a metal gate, the metal silicide 170 formed in the subsequent step S4 is not formed on the surface of the gate structure 110.
Next, a cleaning process is performed on the semiconductor substrate 100 to remove the unreacted metal layer 160 on the top surface of the gate structure 110, the semiconductor substrate 100, and the surface of the sidewall structure 130. Here, the metal layer 160 that is not reacted on the surface of the sidewall structure 130 is mainly removed. The semiconductor substrate 100 may be cleaned by a wet cleaning solution, for example, a mixed solution of one or more of sulfuric acid, hydrogen peroxide, phosphoric acid, strong acid and hydrogen oxidizing agent, or the semiconductor substrate 100 may be cleaned by a heated cleaning solution after the cleaning solution is heated to a high temperature of 100 ℃, so as to increase a cleaning rate and rapidly remove the unreacted metal layer 160. Here, the cleaning time may be more than 20s to completely remove the unreacted metal layer 160 and prevent the residue thereof.
In summary, in the manufacturing method of the semiconductor device provided by the invention, the side wall material layer is etched by adopting a dry method, so that the side wall material layer can be prevented from remaining on the semiconductor substrate, and the surface of the metal silicide can be smooth in appearance when the metal silicide is formed subsequently. Therefore, the concave-convex defect of the surface of the metal silicide can be avoided, and the uniformity of the surface of the metal silicide is improved. Furthermore, as the side wall material layer is etched by adopting the dry etching process, compared with the prior art, the appearance of the side wall is not damaged.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A method for manufacturing a semiconductor device, comprising:
providing a semiconductor substrate, wherein a grid structure is formed on the semiconductor substrate;
forming side wall material layers on the surface of the semiconductor substrate and the top surface and the side surfaces of the grid structure;
etching the side wall material layer by adopting a dry etching process until the top surface of the grid structure and the surface of the semiconductor substrate are exposed so as to form a side wall structure on the side surface of the grid structure;
and forming metal silicide on the exposed surface of the semiconductor substrate and the top surface of the gate structure.
2. The method for manufacturing the semiconductor device according to claim 1, wherein the spacer material layer comprises a first oxide layer, a nitride layer and a second oxide layer which are sequentially stacked, and the first oxide layer covers the surface of the semiconductor substrate and the top surface and the side surfaces of the gate structure.
3. The method for manufacturing the semiconductor device according to claim 2, wherein the method for etching the spacer material layer comprises:
etching the first oxide layer by using a first etching gas until the surface of the nitride layer is exposed;
and etching the nitride layer and the second oxide layer by using a second etching gas until the top surface of the grid structure and the surface of the semiconductor substrate are exposed.
4. The manufacturing method of a semiconductor device according to claim 3, wherein the flow rates of the first etching gas and the second etching gas are each 5sccm to 600 sccm; wherein the first etching gas is at least one of nitrogen gas, fluorine gas and carbon oxide gas; the second etching gas is at least one of nitrogen gas, oxygen gas and carbon fluoride gas.
5. The method of manufacturing a semiconductor device according to claim 1, wherein after forming the sidewall spacer structure and before forming the metal silicide, the method of manufacturing a semiconductor device further comprises:
performing an ion implantation process on the exposed semiconductor to form a source region and a drain region, wherein the source region and the drain region are respectively positioned at two sides of the gate structure; and the number of the first and second groups,
and repairing the surface of the semiconductor substrate after the ion implantation process is performed.
6. The method for manufacturing a semiconductor device according to claim 5, wherein the repair process includes at least one of a thermal oxidation process, an in-situ steam production process, and an oxynitride process.
7. The method for manufacturing a semiconductor device according to claim 1, wherein the method for forming the metal silicide comprises:
forming metal layers on the exposed top surface of the gate structure, the semiconductor substrate and the surfaces of the side wall structures;
annealing the semiconductor substrate to enable the metal in the metal layer to react with the silicon in the grid structure and the semiconductor substrate and form metal silicide;
and performing a cleaning process on the semiconductor substrate to remove the unreacted metal layer on the top surface of the gate structure, the semiconductor substrate and the surface of the side wall structure.
8. The method for manufacturing a semiconductor device according to claim 7, wherein a material of the metal layer is at least one of titanium, zirconium, tantalum, tungsten, manganese, nickel, and yttrium.
9. The method for manufacturing a semiconductor device according to claim 7, wherein before forming the metal layer, the method for manufacturing a semiconductor device further comprises forming an adhesion layer covering the exposed surface of the semiconductor substrate, and after forming the metal layer, the metal layer covers the adhesion layer.
10. The method for manufacturing a semiconductor device according to claim 7, wherein the adhesion layer comprises at least one of a titanium layer, a titanium nitride layer, a tantalum layer, and a tantalum nitride layer.
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