CN111653228A

CN111653228A - Driving method of shift register unit, gate driving circuit and display device

Info

Publication number: CN111653228A
Application number: CN202010552249.9A
Authority: CN
Inventors: 张永强; 徐敬义; 丁爱宇; 刘雨生; 霍培荣; 刘弘; 刘鹏; 李波; 韩帅; 肖振宏
Original assignee: BOE Technology Group Co Ltd; Ordos Yuansheng Optoelectronics Co Ltd
Current assignee: BOE Technology Group Co Ltd; Ordos Yuansheng Optoelectronics Co Ltd
Priority date: 2020-06-17
Filing date: 2020-06-17
Publication date: 2020-09-11

Abstract

The invention provides a driving method of a shift register unit, wherein the shift register unit comprises the following steps: the circuit comprises an input sub-circuit, an output sub-circuit, a reset sub-circuit, a first pull-down sub-circuit and a pull-down control sub-circuit; the driving method of the shift register unit comprises the following steps: in the charging stage, an effective level signal is provided for the input end or the reset end of the shift register unit, an ineffective level signal is provided for the second clock signal end, so that the pull-up control node is charged, and the second clock signal end is disconnected with the pull-down node; in the output stage, providing an invalid level signal for the second clock signal end and providing an effective level signal for the first clock signal end; in the reset stage, an effective level signal is provided for the second clock signal end, and an effective level signal is provided for the reset end or the input end of the shift register unit; and in the noise reduction stage, providing an invalid level signal to the second clock signal terminal to disconnect the second clock signal terminal from the pull-down node. The invention can reduce the power consumption of the shift register unit.

Description

Driving method of shift register unit, gate driving circuit and display device

Technical Field

The invention relates to the technical field of display, in particular to a driving method of a shift register unit, a grid driving circuit and a display device.

Background

At present, a shift register unit usually employs clock signal terminals, and the two clock signal terminals alternately provide effective level signals, wherein a level signal of one clock signal terminal is transmitted to an output terminal of the shift register unit, and a level signal of the other clock signal terminal is transmitted to a pull-down node for charging the pull-down node, thereby resetting the pull-up control node.

In order to prevent the pull-down node from interfering with the output of the shift register unit, when the pull-up control node is at an effective level, the pull-down circuit can conduct the pull-down node and the low-level voltage end, so that the pull-down node is pulled down. However, since the two clock signal terminals alternately provide the effective level signal, when the shift register unit is in the charging stage, the pull-up control node and the clock signal terminal for charging the pull-down node both provide the effective level, and at this time, the clock signal terminal charges the pull-down node, and the pull-down node is conducted with the low level voltage terminal, so that the clock signal terminal for charging the pull-down node and the low level voltage terminal form a dc path, which causes an electrical loss.

Disclosure of Invention

The present invention provides a driving method of a shift register unit, a gate driving circuit and a display device, which are at least for solving one of the technical problems in the prior art.

In order to achieve the above object, the present invention provides a driving method of a shift register unit, the shift register unit including: the circuit comprises an input sub-circuit, an output sub-circuit, a reset sub-circuit, a first pull-down sub-circuit and a pull-down control sub-circuit; the input sub-circuit is connected with the input end of the shift registering unit and the pull-up control node, the output sub-circuit is connected with the pull-up control node, the output end of the shift registering unit and the first clock signal end, the reset sub-circuit is connected with the reset end and the pull-up control node, the first pull-down sub-circuit is connected with the pull-up control node, the pull-down node and the first power end, and the pull-down control sub-circuit is connected with the second clock signal end and the pull-down node; the driving method of the shift register unit comprises the following steps:

in a charging stage, providing an effective level signal to the input end or the reset end of the shift register unit, and providing an ineffective level signal to the second clock signal end, so that the input sub-circuit or the reset sub-circuit charges the pull-up control node, and the pull-down control sub-circuit disconnects the second clock signal end from the pull-down node;

in the output stage, an invalid level signal is provided for the second clock signal end, an effective level signal is provided for the first clock signal end, and the output sub-circuit outputs the effective level signal of the first clock signal end to the output end of the shift register unit;

in a reset stage, providing an effective level signal to the second clock signal terminal, and providing an effective level signal to the reset terminal or the input terminal of the shift register unit, so that the pull-down control sub-circuit conducts the second clock signal terminal and the pull-down node, and the reset sub-circuit or the input sub-circuit resets the pull-up control node;

and in a noise reduction stage, providing an invalid level signal to the second clock signal end so that the pull-down control sub-circuit disconnects the second clock signal end from the pull-down node.

Optionally, the input sub-circuit is further connected to a second power supply terminal, the reset sub-circuit is further connected to a third power supply terminal, the shift register unit has a first scanning state and a second scanning state,

the driving method of the shift register unit further comprises the following steps:

in the first scanning state, supplying an active level signal to the second power supply terminal and an inactive level signal to the third power supply terminal;

in the second scanning state, an inactive level signal is supplied to the second power supply terminal, and an active level signal is supplied to the third power supply terminal.

Optionally, the shift registering unit further includes a touch reset sub-circuit, the touch reset sub-circuit is connected to a touch reset terminal, the first power terminal, and the output terminal of the shift registering unit, and the driving method further includes:

and in a touch detection stage, providing an effective level signal to the touch reset terminal so that the touch reset sub-circuit resets the output end of the shift register unit.

Optionally, the shift register unit further includes a gating sub-circuit, the gating sub-circuit is connected between the output sub-circuit and the pull-up control node, and is connected to a gating control terminal, and the driving method further includes:

and in a touch detection stage, providing an invalid level signal to the gating control end so that the gating sub-circuit disconnects the output sub-circuit from the pull-up control node.

The invention also provides a gate driving circuit, which comprises a driving module and at least one shift register, wherein the shift register comprises a plurality of cascaded shift register units, the shift register units are the shift register units, the driving module is provided with a plurality of clock signal output ends, and the first clock signal end and the second clock signal end of each shift register unit are both connected with one of the clock signal output ends;

the drive module is configured to: for any one of the shift register units, in a charging stage of the shift register unit, providing an invalid level signal to the second clock signal terminal; in the output stage of the shift register unit, providing an invalid level signal to the second clock signal end and providing an effective level signal to the first clock signal end; providing an effective level signal to the second clock signal terminal in a reset stage of the shift register unit; and in the noise reduction stage of the shift register unit, providing an invalid level signal to the second clock signal terminal.

Optionally, the drive module is further configured to: and in a frame starting stage, providing a frame starting signal to the input end of the first shift register unit or the reset end of the last shift register unit.

Optionally, the drive module is further configured to:

providing an active level signal to the second power supply terminal of each of the shift register units and an inactive level signal to the third power supply terminal of each of the shift register units when each of the shift register units is in the first scan state;

and when each of the shift register units is in the second scanning state, providing an invalid level signal to the second power supply terminal of each of the shift register units, and providing an valid level signal to the third power supply terminal of each of the shift register units.

Optionally, the shift register units are divided into a plurality of groups, each group includes four cascaded shift register units, and the clock signal output ends of the driving module include: a first clock signal output end, a second clock signal output end, a third clock signal output end and a fourth clock signal output end, wherein the first clock signal output end, the second clock signal output end, the third clock signal output end and the fourth clock signal output end sequentially output effective level signals;

for a group of the shift register units, a first clock signal end of a first-stage shift register unit is connected with a first clock signal output end, a second clock signal end of the first-stage shift register unit is connected with a second clock signal output end, a first clock signal end of a second-stage shift register unit is connected with a second clock signal output end, a second clock signal end of the second-stage shift register unit is connected with a third clock signal output end, a first clock signal end of a third-stage shift register unit is connected with a third clock signal output end, a second clock signal end of the third-stage shift register unit is connected with a fourth clock signal output end, a first clock signal end of a fourth-stage shift register unit is connected with a fourth clock signal output end, and a second clock signal end of the fourth-stage shift register unit is connected with the first clock signal output end.

Optionally, the shift register units are divided into a plurality of groups, each group includes four cascaded shift register units, and the clock signal output ends of the driving module include: a first clock signal output end, a second clock signal output end, a third clock signal output end and a fourth clock signal output end, wherein the fourth clock signal output end, the third clock signal output end, the second clock signal output end and the first clock signal output end sequentially output effective level signals;

for a group of the shift register units, a first clock signal end of a first-stage shift register unit is connected with a first clock signal output end, a second clock signal end of the first-stage shift register unit is connected with a fourth clock signal output end, a first clock signal end of a second-stage shift register unit is connected with a second clock signal output end, a second clock signal end of the second-stage shift register unit is connected with the first clock signal output end, a first clock signal end of a third-stage shift register unit is connected with a third clock signal output end, a second clock signal end of the third-stage shift register unit is connected with a second clock signal output end, a first clock signal end of a fourth-stage shift register unit is connected with the fourth clock signal output end, and a second clock signal end of the fourth-stage shift register unit is connected with the third clock signal output end.

The present invention also provides a display device, comprising: the gate driving circuit is described above.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:

FIG. 1 is a diagram illustrating a shift register unit according to the related art;

FIG. 2 is a timing diagram of a shift register unit according to the related art;

FIG. 3 is a diagram illustrating a shift register unit according to an embodiment of the present invention;

FIG. 4 is a timing diagram of a shift register unit according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a gate driving circuit according to an embodiment of the invention;

FIG. 6 is a schematic structural diagram of a shift register according to an embodiment of the present invention;

FIG. 7 is a timing diagram of a gate driving circuit according to an embodiment of the present invention;

fig. 8 is a second schematic structural diagram of a gate driving circuit according to an embodiment of the invention.

Detailed Description

The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.

Unless otherwise defined, technical or scientific terms used in the embodiments of the present invention should have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. The use of "first," "second," and similar terms in the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. Likewise, the word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

Fig. 1 is a schematic structural diagram of a shift register unit in the related art, and fig. 2 is a timing diagram of the shift register unit in the related art, and referring to fig. 1 and fig. 2, the shift register unit in the related art includes an input sub-circuit 11, an output sub-circuit 12, a reset sub-circuit 13, a first pull-down sub-circuit 14, a second pull-down sub-circuit 16, and a pull-down control sub-circuit 15. Wherein the input sub-circuit 11 is configured to: in the charging phase t1, the pull-up control node PU _ CN is charged in response to the control of the INPUT terminal INPUT of the shift register unit. Output sub-circuit 12 is configured to: at the OUTPUT stage t2, the signal of the clock signal terminal CK is transmitted to the OUTPUT terminal OUTPUT of the shift register unit in response to the control of the pull-up control node PU _ CN. The reset sub-circuit 13 is configured to: in the reset phase t3, the pull-up control node PU _ CN is reset in response to control of the reset terminal REST. The first pull-down sub-circuit 14 is configured to: in the reset stage t3 and the noise reduction stage t4, the pull-up control node PU _ CN and the OUTPUT terminal OUTPUT of the shift register unit are pulled down in response to the control of the pull-down node PD. The pull-down control sub-circuit 15 is configured to: in the output stage t2 and the noise reduction stage t4, the second clock signal terminal CKB is disconnected from the pull-down node PD in response to the control of the second clock signal terminal CKB, and in the charge stage t1 and the reset stage t3, the second clock signal terminal CKB is connected to the pull-down node in response to the control of the second clock signal terminal CKB. The second pull-down subcircuit 16 is configured to: in the charging stage t1, the pull-down node PD is turned on with the first power source terminal VGL in response to the control of the pull-up control node PU _ CN, where the first power source terminal VGL may be a low voltage power source terminal to pull down the pull-down node PD, and in the OUTPUT stage t2, the pull-down node is turned on with the first power source terminal VGL in response to the control of the pull-up control node PU _ CN and the OUTPUT terminal OUTPUT of the shift registering unit to pull down the pull-down node PD.

However, in the charging phase, since the pull-down node PD is charged by the second clock signal terminal CKB, the second pull-down sub-circuit 16 connects the pull-down node PD with the first power source terminal VGL, and at this time, the potential of the pull-down node PD increases first and then decreases (as shown in a position a in fig. 2), so that the second clock signal terminal CKB is connected with the first power source terminal VGL, and the second clock signal terminal CKB and the first power source terminal VGL form a dc path, thereby causing an electrical loss.

In view of the above, an embodiment of the present invention provides a method for driving a shift register unit, and fig. 3 is a schematic structural diagram of the shift register unit according to the embodiment of the present invention, as shown in fig. 3, the shift register unit includes: an input sub-circuit 11, an output sub-circuit 12, a reset sub-circuit 13, a first pull-down sub-circuit 14 and a pull-down control sub-circuit 15. The INPUT sub-circuit 11 is connected to the INPUT terminal INPUT of the shift register unit and the pull-up control node PU _ CN, and the INPUT sub-circuit 11 is configured to: the pull-up control node PU _ CN is charged in response to the control of the INPUT terminal INPUT of the shift register unit. The OUTPUT sub-circuit 12 is connected to the pull-up control node PU _ CN, the OUTPUT terminal OUTPUT of the shift register unit, and the first clock signal terminal CK1, the OUTPUT sub-circuit 12 is configured to: the signal of the first clock signal terminal CK1 is transmitted to the OUTPUT terminal OUTPUT of the shift register unit in response to the control of the pull-up control node PU _ CN. The reset sub-circuit 13 is connected to the reset terminal REST and the pull-up control node PU _ CN, and the reset sub-circuit 13 is configured to: the pull-up control node PU _ CN is reset in response to control of the reset terminal REST. The first pull-down sub-circuit 14 is connected to the pull-up control node PU _ CN, the pull-down node PD, and a first power supply terminal VGL, which may be a low voltage power supply terminal, the first pull-down sub-circuit 14 being configured to: and responding to the control of the pull-down node PD, and denoising the pull-up control node PU _ CN and the OUTPUT end OUTPUT of the shift register unit. The pull-down control sub-circuit 15 is connected to the second clock signal terminal CK2 and the pull-down node PD, and the pull-down control sub-circuit 15 is configured to: the second clock signal terminal CK2 is turned on or off with the pull-down node PD in response to the control of the second clock signal terminal CK 2. In the embodiment of the present invention, the shift register unit further includes a second pull-down sub-circuit 16, the second pull-down sub-circuit 16 is connected to the pull-up control node PU _ CN, the pull-down node PD, and the first power supply terminal VGL, and the second pull-down sub-circuit 16 is configured to: the pull-down node PD is turned on or off from the first power source terminal VGL in response to the control of the pull-up control node PU _ CN.

Fig. 4 is a timing diagram of a shift register unit according to an embodiment of the present invention, and as shown in fig. 4, the driving method of the shift register unit includes:

in the charging period t1, an active level signal is provided to the INPUT terminal INPUT or the reset terminal REST of the shift register unit, and an inactive level signal is provided to the second clock signal terminal CK2, so that the INPUT sub-circuit 11 or the reset sub-circuit 13 charges the pull-up control node PU _ CN, and the pull-down control sub-circuit 15 disconnects the second clock signal terminal CK2 from the pull-down node. At this time, the potential of the pull-up control node PU _ CN rises, the first clock signal terminal CK1 OUTPUTs an invalid level signal, the OUTPUT sub-circuit 12 transmits the invalid level signal of the first clock signal terminal CK1 to the OUTPUT terminal OUTPUT of the shift register unit, and the second pull-down sub-circuit 16 responds to the valid level signal of the pull-up control node PU _ CN to turn on the pull-down node PD with the first power terminal VGL, thereby pulling down the pull-down node PD.

In the OUTPUT stage t2, an inactive level signal is provided to the second clock signal terminal CK2, and an active level signal is provided to the first clock signal terminal CK1, at this time, the first clock signal terminal CK1 OUTPUTs an active level signal, the potential of the PU _ CN node further rises, the OUTPUT sub-circuit 12 transmits the active level signal of the first clock signal terminal CK1 to the OUTPUT terminal OUTPUT of the shift register unit, and the second pull-down sub-circuit 16 turns on the pull-down node PD with the first power terminal VGL in response to the active level signal of the pull-up control node PU _ CN and the active signal of the OUTPUT terminal OUTPUT of the shift register unit, thereby pulling down the pull-down node PD.

In the reset phase t3, an active level signal is provided to the second clock signal terminal CK2, and an active level signal is provided to the reset terminal REST or the INPUT terminal INPUT of the shift register unit, so that the reset sub-circuit 13 or the INPUT sub-circuit 11 resets the pull-up control node PU _ CN, the pull-down control sub-circuit 15 conducts the second clock signal terminal CK2 with the pull-down node PD, at this time, the second clock signal terminal CK2 charges the pull-down node PD, and the first pull-down sub-circuit 14 conducts the OUTPUT terminal OUTPUT of the shift register unit with the first power terminal VGL in response to the active level signal of the pull-down node PD, thereby resetting the OUTPUT terminal OUTPUT of the shift register unit.

In the noise reduction period t4, an inactive level signal is supplied to the second clock signal terminal CK2 to cause the pull-down control sub-circuit 15 to disconnect the second clock signal terminal CK2 from the pull-down node PD. The first pull-down sub-circuit 14 responds to the active level signal of the pull-down node PD, and connects the pull-up control node PU _ CN and the OUTPUT terminal OUTPUT of the shift registering unit with the first power source terminal VGL, so as to reduce noise of the pull-up control node PU _ CN and the OUTPUT terminal OUTPUT of the shift registering unit.

In summary, with the driving method according to the embodiment of the invention, the second clock signal terminal CK2 and the pull-down node PD can be disconnected by the pull-down control sub-circuit 15 during the charging period t1, so as to avoid the second clock signal terminal CK2 charging the pull-down node PD, prevent the second clock signal terminal CK2 and the first power terminal VGL from being turned on, and reduce the power consumption of the shift register unit.

It should be noted that, in the embodiment of the present invention, when the INPUT terminal INPUT of the shift register unit is provided with the active level signal in the charging phase t1, the reset terminal REST is provided with the active level signal in the reset phase t 3; while the charging period t1 provides an active level signal to the reset REST, the reset period t3 provides an active level signal to the INPUT terminal INPUT of the shift register unit.

The specific structure of the shift register unit provided in the embodiment of the present invention is described in detail below with reference to fig. 3 and 4, and it should be noted that the transistor in the embodiment of the present invention may be a thin film transistor or a field effect transistor or other switching devices with the same characteristics. Transistors generally include three poles: the gate, source and drain, the source and drain in a transistor are symmetrical in structure, and the two may be interchanged as desired. In the embodiment of the invention, one of the first pole and the second pole is a source electrode, and the other is a drain electrode.

Further, the transistors may be classified into N-type transistors and P-type transistors according to transistor characteristics. In the invention, an "active level signal" refers to a voltage signal capable of controlling the turn-on of a corresponding transistor, and an "inactive level signal" refers to a voltage signal capable of controlling the turn-off of a corresponding transistor; therefore, when the transistor is an N-type transistor, the active level signal refers to a high level signal, and the inactive level signal refers to a low level signal; when the transistor is a P-type transistor, the active level signal is a low level signal, and the inactive level signal is a high level signal.

As shown in fig. 3, the INPUT sub-circuit 11 includes an INPUT transistor T1, a first pole of the INPUT transistor T1 is connected to the second power source terminal CN, a second pole of the INPUT transistor T1 is connected to the pull-up control node PU _ CN, and a gate of the INPUT transistor T1 is connected to the INPUT terminal INPUT of the shift register unit. The output sub-circuit 12 includes: a first capacitor C1 and an OUTPUT transistor T3, a first pole of the OUTPUT transistor T3 is connected to the first clock signal terminal CK1, a second pole of the OUTPUT transistor T3 is connected to the OUTPUT terminal OUTPUT of the shift register unit, a gate of the OUTPUT transistor T3 is connected to one end of the first capacitor C1 and the pull-up control node PU _ CN, and the other end of the first capacitor C1 is connected to the second pole of the OUTPUT transistor T3. The reset sub-circuit 13 includes: a reset transistor T2, a first pole of the reset transistor T2 is connected to the third power source terminal CNB, a second pole of the reset transistor T2 is connected to the pull-up control node PU _ CN, and a gate of the reset transistor T2 is connected to the reset terminal REST. The first pull-down sub-circuit 14 includes: a first pull-down transistor T4 and a second pull-down transistor T5, a first pole of the first pull-down transistor T4 is connected to the OUTPUT terminal OUTPUT of the shift register unit, a first pole of the second pull-down transistor T5 is connected to the pull-up control node PU _ CN, a second pole of the first pull-down transistor T4 and a second pole of the second pull-down transistor T5 are both connected to the first power source terminal VGL, and a gate of the first pull-down transistor T4 and a gate of the second pull-down transistor T5 are both connected to the pull-down node PD. The pull-down control sub-circuit 15 includes a pull-down control transistor T7, a first pole and a gate of the pull-down control transistor T7 are both connected to the second clock signal terminal CK2, and a second pole of the pull-down control transistor T7 is connected to the pull-down node PD. The second pull-down sub-circuit 16 includes: a third pull-down transistor T6 and a fourth pull-down transistor T8, a first pole of the third pull-down transistor T6 and a first pole of the fourth pull-down transistor T8 are both connected to the pull-down node PD, a second pole of the third pull-down transistor T6 and a second pole of the fourth pull-down transistor T8 are both connected to the first power supply terminal VGL, a gate of the third pull-down transistor T6 is connected to the pull-up control node PU _ CN, and a gate of the fourth pull-down transistor T8 is connected to the OUTPUT terminal OUTPUT of the shift register unit.

In some embodiments, the shift register unit has a first scan state and a second scan state, and the driving method of the shift register unit further includes: in the first scanning state, an active level signal is supplied to the second power source terminal CN and an inactive level signal is supplied to the third power source terminal CNB. In the second scanning state, the inactive level signal is supplied to the second power source terminal CN and the active level signal is supplied to the third power source terminal CNB.

In an embodiment of the present invention, the first scanning state may be a forward scanning state, and the second scanning state may be a reverse scanning state. When the shift register unit is in the first scanning state, in the charging phase T1, the INPUT transistor T1 of the shift register unit responds to the valid signal of the INPUT terminal INPUT, and turns on the second power supply terminal CN and the pull-up control node PU _ CN, and at this time, the second power supply terminal CN provides a valid level signal, thereby charging the pull-up control node PU _ CN; in the reset period T3, the reset transistor T2 turns on the third power source terminal CNB with the pull-up control node PU _ CN in response to the active signal of the reset terminal REST, at which time the third power source terminal CNB provides an inactive level signal, thereby resetting the pull-up control node PU _ CN. When the shift register unit is in the second scanning state, in the charging phase T1, the reset transistor T2 of the shift register unit responds to the valid signal of the reset terminal REST to turn on the third power terminal CNB and the pull-up control node PU _ CN, and at this time, the third power terminal CNB provides a valid level signal, so as to charge the pull-up control node PU _ CN; during the reset period T3, the INPUT transistor T1 turns on the second power source terminal CN with the pull-up control node PU _ CN in response to the active signal of the INPUT terminal INPUT, at which time the second power source terminal CN provides an inactive level signal, thereby resetting the pull-up control node PU _ CN.

In some embodiments, the shift register unit further includes a gate sub-circuit 17, the gate sub-circuit 17 is connected between the output sub-circuit 12 and the pull-up control node PU _ CN and is connected to the gate control terminal VGH, the gate sub-circuit 17 is configured to: the output sub circuit 12 is turned on or off with the pull-up control node PU _ CN in response to the control of the gate control terminal VGH. As shown in fig. 3, the gate sub-circuit 17 includes a gate transistor T9, a first pole of the gate transistor T9 is connected to the pull-up control node PU _ CN, a second pole of the gate transistor T9 is connected to one end of the first capacitor C1, that is, to the pull-up node PU, and a gate of the gate transistor T9 is connected to the gate control terminal VGH.

The driving method of the shift register unit provided by the embodiment of the invention further comprises the following steps: in the touch detection stage, an invalid level signal is provided to the gate control terminal VGH, so that the gate sub-circuit 17 disconnects the output sub-circuit 12 from the pull-up control node PU _ CN, thereby preventing the pull-up node PU from generating electric leakage in the touch detection stage. In the charging period t1, the output period t2, the reset period t3 and the noise reduction period t4, an active level signal is provided to the gate control terminal VGH, so that the gate sub-circuit 17 turns on the output sub-circuit 12 and the pull-up control node PU _ CN, thereby controlling the potential of the pull-up node PU.

In some embodiments, the shift register unit further includes a reset sub-circuit 18, the reset sub-circuit 18 is connected to the pull-up control node PU _ CN, the reset terminal T _ REST, and the first power source terminal VGL, and the reset sub-circuit is configured to: in response to the control of the reset terminal T _ REST, the pull-up control node PU _ CN is reset before the start of each frame. As shown in fig. 3, the reset sub-circuit 18 includes a reset transistor T10, a first pole of the reset transistor T10 is connected to the pull-up control node PU _ CN, a second pole of the reset transistor T10 is connected to the first power source terminal VGL, and a gate of the reset transistor T10 is connected to the reset terminal T _ REST.

In some embodiments, the shift register unit further includes a TOUCH reset sub-circuit 19, the TOUCH reset sub-circuit 19 is connected to the TOUCH reset terminal EN _ TOUCH, the first power terminal VGL and the OUTPUT terminal OUTPUT of the shift register unit, and the TOUCH reset sub-circuit 19 is configured to reset the OUTPUT terminal OUTPUT of the shift register unit in response to the control of the reset terminal EN _ TOUCH. As shown in fig. 3, the touch reset sub-circuit 19 includes: a first pole of the TOUCH reset transistor T11 is connected to the OUTPUT terminal OUTPUT of the shift register unit, a second pole of the TOUCH reset transistor T11 is connected to the first power source terminal VGL, and a gate of the TOUCH reset transistor T11 is connected to the TOUCH reset terminal EN _ TOUCH.

The driving method of the shift register unit provided by the embodiment of the invention further comprises the following steps: in the TOUCH detection stage, an active level signal is provided to the TOUCH reset terminal EN _ TOUCH, so that the TOUCH reset sub-circuit 19 resets the OUTPUT terminal OUTPUT of the shift register unit, thereby preventing the OUTPUT terminal OUTPUT of the shift register unit from interfering with TOUCH detection.

In some embodiments, the shift register unit further includes a second capacitor C2, one end of the second capacitor C2 is connected to the pull-down node PD, and the other end of the second capacitor C2 is connected to the first power source terminal VGL, so as to hold the voltage of the pull-down node PD and reduce noise.

Taking the shift register unit in the first scanning state as an example (that is, providing an active level signal to the second power supply terminal CN and providing an inactive level signal to the third power supply terminal CNB), the operation process of the shift register unit according to the embodiment of the present invention will be described with reference to fig. 4, specifically:

in the charging phase T1, the INPUT terminal INPUT of the shift register unit is supplied with an active level signal, the first clock signal terminal CK1 is supplied with an inactive level signal, and the second clock signal terminal CK2 is supplied with an inactive level signal, the INPUT transistor T1 turns on the second power terminal CN and the pull-up control node PU _ CN in response to the active level signal of the INPUT terminal INPUT of the shift register unit, thereby charging the pull-up control node PU _ CN, and the pull-down control transistor T7 turns off the second clock signal terminal CK2 and the pull-down node PD in response to the inactive level signal of the second clock signal terminal CK 2. The third pull-down transistor T6 turns on the first power terminal VGL and the pull-down node PD in response to the active level signal of the pull-up control node PU _ CN, thereby pulling down the pull-down node PD. The OUTPUT transistor T3 turns on the first clock signal terminal CK1 and the OUTPUT terminal OUTPUT of the shift register unit in response to the active level signal of the pull-up control node PU _ CN, thereby transmitting the inactive level signal of the first clock signal terminal CK1 to the OUTPUT terminal OUTPUT of the shift register unit.

At the OUTPUT stage T2, an inactive level signal is provided to the second clock signal terminal CK2, and an active level signal is provided to the first clock signal terminal CK1, at this time, the potential of the pull-up node PU _ CN node further rises due to the bootstrap action of the first capacitor C1, the OUTPUT transistor T3 is fully turned on, and the active level signal of the first clock signal terminal CK1 is transmitted to the OUTPUT terminal OUTPUT of the register unit, and the fourth pull-down transistor T8 turns on the pull-down node PD with the first power terminal VGL in response to the active level signal of the OUTPUT terminal OUTPUT of the shift register unit, thereby pulling down the pull-down node PD.

In the reset phase T3, the active level signal is provided to the second clock signal terminal CK2 and the active level signal is provided to the reset terminal REST, the reset transistor T2 responds to the active level signal of the reset terminal REST to turn on the third power terminal CNB and the pull-up control node PU _ CN, thereby resetting the pull-up control node PU _ CN, and the OUTPUT transistor T3 responds to the inactive level signal of the pull-up control node PU _ CN to turn off the first clock signal terminal CK1 and the OUTPUT terminal OUTPUT of the shift register unit. The pull-down control transistor T7 turns on the second clock signal terminal CK2 with the pull-down node PD in response to the active level signal of the second clock signal terminal CK2 to charge the pull-down node PD, and the first pull-down transistor T4 turns on the OUTPUT terminal OUTPUT of the shift registering unit with the first power source terminal VGL in response to the active level signal of the pull-down node PD to reset the OUTPUT terminal OUTPUT of the shift registering unit.

In the noise reduction stage T4, the disable level signal is provided to the second clock signal terminal CK2, the pull-down control transistor T7 responds to the disable level signal of the second clock signal terminal CK2 to disconnect the second clock signal terminal CK2 from the pull-down node PD, the first pull-down transistor T4 responds to the enable level signal of the pull-down node PD to connect the OUTPUT terminal OUTPUT of the shift register unit to the first power terminal VGL to reduce noise of the OUTPUT terminal OUTPUT of the shift register unit, and the second pull-down transistor T5 responds to the enable level signal of the pull-down node PD to connect the pull-up control node PU _ CN to the first power terminal VGL to reduce noise of the pull-up control node PU _ CN.

It should be noted that, during the charging phase T1, the pull-up control node PU _ CN is charged by the INPUT transistor T1 responding to the active level signal of the INPUT terminal INPUT, and the pull-up control node PU _ CN is conducted to the second power terminal CN, in other embodiments, during the charging phase T1, the first pole and the gate of the INPUT transistor T1 may be connected to the INPUT terminal INPUT of the register unit, so that the INPUT transistor T1 can transmit the active level signal of the INPUT terminal INPUT to the pull-up control node PU _ CN to charge the pull-up control node PU _ CN in response to the active level signal of the INPUT terminal INPUT of the register unit.

Fig. 5 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention, and as shown in fig. 5, the gate driving circuit includes a driving module and at least one shift register, where the shift register includes a plurality of cascaded shift register units, the shift register units are the shift register units described above, the driving module has a plurality of clock signal output ends, and a first clock signal end CK1 and a second clock signal end CK2 of each shift register unit are both connected to one of the clock signal output ends. The drive module is configured to: for any one shift register unit, during the charging phase of the shift register unit, an inactive level signal is provided to the second clock signal terminal CK 2. In the output stage of the shift register unit, the inactive level signal is supplied to the second clock signal terminal CK2, and the active level signal is supplied to the first clock signal terminal CK 1. In the reset phase of the shift register unit, an active level signal is supplied to the second clock signal terminal CK 2. During the noise reduction stage of the shift register unit, an inactive level signal is supplied to the second clock signal terminal CK 2.

In an embodiment of the present invention, the driving module further includes a reset output terminal RESTL, the reset output terminal RESTL is connected to the reset terminal T _ REST of each shift register unit, and the reset output terminal RESTL is configured to: before each frame starts, an effective level signal is provided to the reset terminals T _ REST of all the shift register units so as to reset the pull-up control nodes in the shift register units. The driving module has a plurality of clock signal output terminals, and the first clock signal terminal CK1 and the second clock signal terminal CK2 of each shift register unit are connected to one of the clock signal output terminals, for example, the plurality of clock signal output terminals include: the shift register unit comprises a first clock signal output terminal CLK1, a second clock signal output terminal CLK2, a third clock signal output terminal CLK3 and a fourth clock signal output terminal CLK4, wherein the first clock signal terminal CK1 of one shift register unit is connected with the first clock signal output terminal CLK1, the second clock signal terminal CK2 is connected with the second clock signal output terminal CLK2, the first clock signal terminal CK1 of the next shift register unit is connected with the second clock signal output terminal CLK2, the second clock signal terminal CK2 is connected with the third clock signal output terminal CLK3, and so on. When the four clock signal output terminals sequentially output valid signals, for each shift register unit, an invalid level signal may be provided to the second clock signal terminal CK2 during the charging period t1, so that the pull-down control sub-circuit 15 disconnects the second clock signal terminal CK2 from the pull-down node PD, and the second clock signal terminal CK2 is prevented from charging the pull-down node PD.

Therefore, the gate driving circuit according to the embodiment of the invention can prevent the conduction of the second clock signal terminal CK2 and the first power source terminal VGL in the charging period T1 of the shift register unit, thereby reducing the power consumption of the shift register unit GOA.

In an embodiment of the present invention, the OUTPUT terminal OUTPUT of the shift register unit may be configured to provide a driving signal to a gate line in a display area, the OUTPUT terminal OUTPUT of the shift register unit may be further connected to the INPUT terminal INPUT of a next shift register unit and the reset terminal REST of a previous shift register unit, and the driving module is further configured to: in the frame starting stage, a frame starting signal is provided to the INPUT end INPUT of the first shift register unit or the reset end REST of the last shift register unit, and at this time, the effective signal output by the previous shift register unit can be used as the frame starting signal of the next shift register unit or the previous shift register unit, so that the plurality of cascaded shift register units output effective level signals step by step along the forward direction or the reverse direction.

In some embodiments, the drive module is further configured to: when each shift register unit is in the first scanning state, an active level signal is supplied to the second power supply terminal CN of each shift register unit, and an inactive level signal is supplied to the third power supply terminal CNB of each shift register unit. When each of the shift register units is in the second scanning state, an inactive level signal is supplied to the second power source terminal CN of each of the shift register units, and an active level signal is supplied to the third power source terminal CNB of each of the shift register units.

Fig. 6 is a schematic structural diagram of a shift register according to an embodiment of the present invention, as shown in fig. 6, in the embodiment of the present invention, the first scan state may be a forward scan state, and the second scan state may be a reverse scan state, when the shift register unit is in the first scan state, in a charging phase T1, the INPUT transistor T1 of the shift register unit responds to an active signal of the INPUT terminal INPUT, and turns on the second power terminal CN and the pull-up control node PU _ CN, and at this time, the second power terminal CN provides an active level signal, so as to charge the pull-up control node PU _ CN; in the reset period T3, the reset transistor T2 turns on the third power source terminal CNB with the pull-up control node PU _ CN in response to the active signal of the reset terminal REST, at which time the third power source terminal CNB provides an inactive level signal, thereby resetting the pull-up control node PU _ CN. When the shift register unit is in the second scanning state, in the charging phase T1, the reset transistor T2 of the shift register unit responds to the valid signal of the reset terminal REST to turn on the third power terminal CNB and the pull-up control node PU _ CN, and at this time, the third power terminal CNB provides a valid level signal, so as to charge the pull-up control node PU _ CN; during the reset period T3, the INPUT transistor T1 turns on the second power source terminal CN with the pull-up control node PU _ CN in response to the active signal of the INPUT terminal INPUT, at which time the second power source terminal CN provides an inactive level signal, thereby resetting the pull-up control node PU _ CN.

As shown in fig. 5, in some embodiments, the shift register units are divided into a plurality of groups, each group includes four cascaded shift register units, and the clock signal output terminals of the driving module include: the first, second, third and fourth clock signal output terminals CLK1, CLK2, CLK3 and CLK4 output active level signals in sequence from the first, second, third and fourth clock signal output terminals CLK1, CLK2, CLK3 and CLK 4.

For a group of shift register units, the first clock signal terminal CK1 of the first stage shift register unit GOA1 is connected to the first clock signal output terminal CLK1, the second clock signal terminal CK2 of the first stage shift register unit GOA1 is connected to the second clock signal output terminal CLK2, the first clock signal terminal CK1 of the second stage shift register unit GOA2 is connected to the second clock signal output terminal CLK2, the second clock signal terminal CK2 of the second stage shift register unit GOA2 is connected to the third clock signal output terminal CLK3, the first clock signal terminal CK1 of the third stage shift register unit GOA3 is connected to the third clock signal output terminal CLK3, the second clock signal terminal CK2 of the third stage shift register unit GOA3 is connected to the fourth clock signal output terminal CLK4, the first clock signal terminal CK1 of the fourth stage shift register unit GOA4 is connected to the fourth clock signal output terminal CLK4, and the fourth stage shift register unit GOA 828653 is connected to the fourth stage shift register unit GOA 86 2.

Fig. 7 is a timing diagram of the gate driving circuit according to the embodiment of the invention, in which the pull-up control node PU _ CN in fig. 7 is the pull-up control node PU _ CN in the second shift register unit GOA2, and the pull-down node PD is the pull-down node PD in the second shift register unit GOA 2. The operation of the gate driving circuit according to the embodiment of the present invention will be explained with reference to fig. 7 by taking the shift register units in the first scanning state (i.e., providing the second power source terminal CN with an active level signal and providing the third power source terminal CNB with an inactive level signal), and each shift register unit corresponds to an odd-numbered row of gate lines in the display area. Specifically, the method comprises the following steps:

in the phase Ta, the first clock signal output terminal CLK1 outputs an active level signal, and the second, third and fourth clock signal output terminals CLK2, CLK3 and CLK4 all output an inactive level signal.

For the first-stage shift register unit GOA1, at this time, in the OUTPUT stage, the second clock signal terminal CK2 of the first-stage shift register unit GOA1 is connected to the second clock signal OUTPUT terminal CLK2, and the first clock signal terminal CK1 is connected to the first clock signal OUTPUT terminal CLK1, at this time, due to the bootstrapping effect of the first capacitor C1, the potential of the pull-up node PU _ CN further rises, the OUTPUT transistor T3 is fully turned on, and transmits the effective level signal of the first clock signal terminal CK1 to the OUTPUT terminal OUTPUT1 of the first-stage shift register unit GOA1, and the fourth pull-down transistor T8 turns on the pull-down node PD and the first power supply terminal VGL in response to the effective level signal of the OUTPUT terminal OUTPUT1 of the first-stage shift register unit GOA1, so as to pull down the pull-down node PD.

For the second stage shift register unit GOA2, in the charging phase, the valid level signal of the OUTPUT terminal OUTPUT1 of the first stage shift register unit GOA1 is transmitted to the INPUT terminal INPUT of the second stage shift register unit GOA2, the first clock signal terminal CK1 of the second stage shift register unit GOA2 is connected to the second clock signal OUTPUT terminal CLK2, the second clock signal terminal CK2 of the second stage shift register unit GOA2 is connected to the third clock signal OUTPUT terminal CLK3, the INPUT transistor T1 of the second stage shift register unit GOA2 is responsive to the valid level signal of the INPUT terminal INPUT of the second stage shift register unit GOA2 to turn on the second power terminal CN and the pull-up control node PU _ CN to charge the pull-up control node PU _ CN, and the pull-down control transistor T7 is responsive to the invalid level signal of the second clock signal terminal CK2 to disconnect the second clock signal terminal PD 2 from the pull-down control node PD 3683. The third pull-down transistor T6 turns on the first power terminal VGL and the pull-down node PD in response to the active level signal of the pull-up control node PU _ CN, thereby pulling down the pull-down node PD. The OUTPUT transistor T3 is responsive to the active level signal of the pull-up control node PU _ CN to turn on the first clock signal terminal CK1 and the OUTPUT terminal OUTPUT2 of the second stage shift register unit GOA2, so as to transmit the inactive level signal of the first clock signal terminal CK1 to the OUTPUT terminal OUTPUT2 of the second stage shift register unit GOA 2.

For the third stage GOA3, the disable signal of the second stage GOA2 is transmitted to the INPUT terminal INPUT of the third stage GOA3, the INPUT transistor T1 of the third stage GOA3 is turned off, and the OUTPUT terminal OUTPUT3 of the third stage GOA3 OUTPUTs an disable level signal.

For the fourth-stage shift register unit GOA4, the inactive level signal of the OUTPUT terminal OUTPUT3 of the third-stage shift register unit GOA3 is transmitted to the INPUT terminal INPUT of the fourth-stage shift register unit GOA4, the INPUT transistor T1 of the fourth-stage shift register unit GOA4 is turned off, and the OUTPUT terminal OUTPUT4 of the fourth-stage shift register unit GOA4 OUTPUTs the inactive level signal.

In the period Tb, the first, second, third and fourth clock signal outputs CLK1, CLK2, CLK3 and CLK4 all output an inactive level signal.

For the first stage shift register unit GOA1, between the OUTPUT stage and the reset stage, the voltage level of the pull-up node PU _ CN drops due to the inactive signal provided by the first clock terminal CK1, but the voltage level of the pull-up node PU _ CN still enables the OUTPUT transistor T3 to turn on, so that the inactive level signal of the first clock terminal CK1 is transmitted to the OUTPUT terminal OUTPUT1 of the first stage shift register unit GOA 1.

For the second stage shift register unit GOA2, at this time, between the charging stage and the OUTPUT stage, the invalid level signal of the OUTPUT terminal OUTPUT1 of the first stage shift register unit GOA1 is transmitted to the INPUT terminal INPUT of the second stage shift register unit GOA2, the INPUT transistor T1 of the second stage shift register unit GOA2 is turned off, and the third pull-down transistor T6 turns on the first power terminal VGL and the pull-down node PD in response to the valid level signal of the pull-up control node PU _ CN, thereby pulling down the pull-down node PD. The OUTPUT transistor T3 is responsive to the active level signal of the pull-up control node PU _ CN to turn on the first clock signal terminal CK1 and the OUTPUT terminal OUTPUT2 of the second stage shift register unit GOA2, so as to transmit the inactive level signal of the first clock signal terminal CK1 to the OUTPUT terminal OUTPUT2 of the second stage shift register unit GOA 2.

During the period Tc, the second clock signal output terminal CLK2 outputs an active level signal, and the first, third and fourth clock signal output terminals CLK1, CLK3 and CLK4 all output an inactive level signal.

For the first-stage shift register unit GOA1, in the reset stage, the valid level signal of the OUTPUT terminal OUTPUT2 of the second-stage shift register unit GOA2 is transmitted to the reset terminal REST of the first-stage shift register unit GOA1, and the reset transistor T2 of the first-stage shift register unit GOA1 responds to the valid level signal of the reset terminal REST, and connects the pull-up control node PU _ CN with the third power terminal CNB, so as to reset the pull-up control node PU _ CN. The pull-down control transistor T7 turns on the pull-down node PD with the second clock signal terminal CK2 in response to the active level signal of the second clock signal terminal CK2 to charge the pull-down node PD, and the first pull-down transistor T4 turns on the OUTPUT terminal OUTPUT1 of the first stage shift register unit GOA1 with the first power supply terminal VGL in response to the active level signal of the pull-down node PD to reset the OUTPUT terminal OUTPUT1 of the first stage shift register unit GOA 1.

For the second stage shift register unit GOA2, in the OUTPUT stage, the OUTPUT transistor T3 of the second stage shift register unit GOA2 is fully turned on, and transmits the active level signal of the second clock signal terminal CK2 to the OUTPUT terminal OUTPUT2 of the second stage shift register unit GOA2, and the fourth pull-down transistor T8 responds to the active level signal of the OUTPUT terminal OUTPUT2 of the second stage shift register unit GOA2 to turn on the pull-down node PD and the first power terminal VGL, so as to pull down the pull-down node PD.

For the third stage GOA3, during the charging phase, the valid level signal of the OUTPUT terminal OUTPUT2 of the second stage GOA2 is transmitted to the INPUT terminal INPUT of the third stage GOA3, the INPUT transistor T1 of the third stage GOA3 is responsive to the valid level signal of the INPUT terminal INPUT of the third stage GOA3 to turn on the second power terminal CN and the pull-up control node PU _ CN for charging the pull-up control node PU _ CN, and the pull-down control transistor T7 is responsive to the invalid level signal of the second clock signal terminal CK2 for disconnecting the second clock signal terminal CK2 and the pull-down node PD. The third pull-down transistor T6 turns on the first power terminal VGL and the pull-down node PD in response to the active level signal of the pull-up control node PU _ CN, thereby pulling down the pull-down node PD. The OUTPUT transistor T3 responds to the active level signal of the pull-up control node PU _ CN to turn on the first clock signal terminal CK1 and the OUTPUT terminal OUTPUT3 of the third stage shift register unit GOA3, so as to transmit the inactive level signal of the first clock signal terminal CK1 to the OUTPUT terminal OUTPUT3 of the third stage shift register unit GOA 3.

At the period Td, the first, second, third and fourth clock signal outputs CLK1, CLK2, CLK3 and CLK4 all output an inactive level signal.

For the first stage shift register unit GOA1, at this time, between the reset stage and the noise reduction stage, the pull-down control transistor T7 of the first stage shift register unit GOA1 responds to the inactive level signal of the second clock signal terminal CK2 to disconnect the second clock signal terminal CK2 from the pull-down node PD, the first pull-down transistor T4 responds to the active level signal of the pull-down node PD to connect the OUTPUT terminal OUTPUT1 of the first stage shift register unit GOA1 with the first power supply terminal VGL, so as to reduce the noise of the OUTPUT terminal OUTPUT1 of the first stage shift register unit GOA1, and the second pull-down transistor T5 responds to the active level signal of the pull-down node PD to connect the pull-up control node PU _ CN with the first power supply terminal VGL, so as to reduce the noise of the pull-up control node PU _ CN.

For the second stage shift register unit GOA2, which is between the OUTPUT stage and the reset stage, the voltage level of the pull-up node PU _ CN drops due to the inactive signal provided by the first clock terminal CK1, but the voltage level of the pull-up node PU _ CN still enables the OUTPUT transistor T3 to be turned on, so that the inactive level signal of the first clock terminal CK1 is transmitted to the OUTPUT terminal OUTPUT2 of the second stage shift register unit GOA 2.

For the third stage shift register unit GOA3, which is between the charging stage and the OUTPUT stage, the invalid level signal of the OUTPUT terminal OUTPUT2 of the second stage shift register unit GOA2 is transmitted to the INPUT terminal INPUT of the third stage shift register unit GOA3, the INPUT transistor T1 of the third stage shift register unit GOA3 is turned off, and the third pull-down transistor T6 turns on the first power terminal VGL and the pull-down node PD in response to the valid level signal of the pull-up control node PU _ CN, thereby pulling down the pull-down node PD. The OUTPUT transistor T3 responds to the active level signal of the pull-up control node PU _ CN to turn on the first clock signal terminal CK1 and the OUTPUT terminal OUTPUT3 of the third stage shift register unit GOA3, so as to transmit the inactive level signal of the first clock signal terminal CK1 to the OUTPUT terminal OUTPUT3 of the third stage shift register unit GOA 3.

At the stage Te, the third clock signal output terminal CLK3 outputs an active level signal, and the first, second, and fourth clock signal output terminals CLK1, CLK2, and CLK4 all output an inactive level signal.

For the first stage shift register unit GOA1, at this time, in the noise reduction stage, the pull-down control transistor T7 of the first stage shift register unit GOA1 responds to the inactive level signal of the second clock signal terminal CK2 to disconnect the second clock signal terminal CK2 from the pull-down node PD, the first pull-down transistor T4 responds to the active level signal of the pull-down node PD to connect the OUTPUT terminal OUTPUT1 of the first stage shift register unit GOA1 with the first power terminal VGL, so as to reduce the noise of the OUTPUT terminal OUTPUT1 of the first stage shift register unit GOA1, and the second pull-down transistor T5 responds to the active level signal of the pull-down node PD to connect the pull-up control node PU _ CN with the first power terminal VGL, so as to reduce the noise of the pull-up control node PU _ CN.

For the second-stage shift register unit GOA2, in the reset stage, the valid level signal of the OUTPUT terminal OUTPUT3 of the third-stage shift register unit GOA3 is transmitted to the reset terminal REST of the second-stage shift register unit GOA2, and the reset transistor T2 of the second-stage shift register unit GOA2 responds to the valid level signal of the reset terminal REST to connect the pull-up control node PU _ CN with the third power terminal CNB, so as to reset the pull-up control node PU _ CN. The pull-down control transistor T7 turns on the pull-down node PD with the second clock signal terminal CK2 in response to the active level signal of the second clock signal terminal CK2 to charge the pull-down node PD, and the first pull-down transistor T4 turns on the OUTPUT terminal OUTPUT2 of the second stage shift register unit GOA2 with the first power supply terminal VGL in response to the active level signal of the pull-down node PD to reset the OUTPUT terminal OUTPUT2 of the second stage shift register unit GOA 2.

For the third stage shift register unit GOA3, it is in the OUTPUT stage, at this time, the OUTPUT transistor T3 of the third stage shift register unit GOA3 is fully turned on, and transmits the active level signal of the second clock signal terminal CK2 to the OUTPUT terminal OUTPUT3 of the third stage shift register unit GOA3, and the fourth pull-down transistor T8 responds to the active level signal of the OUTPUT terminal OUTPUT3 of the third stage shift register unit GOA3 to turn on the pull-down node PD and the first power terminal VGL, thereby pulling down the pull-down node PD.

For the fourth stage shift register unit GOA4, during the charging phase, the active level signal of the OUTPUT terminal OUTPUT3 of the third stage shift register unit GOA3 is transmitted to the INPUT terminal INPUT of the fourth stage shift register unit GOA4, the INPUT transistor T1 of the fourth stage shift register unit GOA4 is responsive to the active level signal of the INPUT terminal INPUT of the fourth stage shift register unit GOA4 to turn on the second power terminal CN and the pull-up control node PU _ CN to charge the pull-up control node PU _ CN, and the pull-down control transistor T7 is responsive to the inactive level signal of the second clock signal terminal CK2 to turn off the second clock signal terminal CK2 and the pull-down node PD. The third pull-down transistor T6 turns on the first power terminal VGL and the pull-down node PD in response to the active level signal of the pull-up control node PU _ CN, thereby pulling down the pull-down node PD. The OUTPUT transistor T3 responds to the active level signal of the pull-up control node PU _ CN to turn on the first clock signal terminal CK1 and the OUTPUT terminal OUTPUT4 of the fourth stage shift register unit GOA4, so as to transmit the inactive level signal of the first clock signal terminal CK1 to the OUTPUT terminal OUTPUT4 of the fourth stage shift register unit GOA 4.

At the stage Tf, the first, second, third and fourth clock signal outputs CLK1, CLK2, CLK3 and CLK4 all output an inactive level signal.

For the first stage shift register unit GOA1, at this time, the first pull-down transistor T4 of the first stage shift register unit GOA1 responds to the active level signal of the pull-down node PD to turn on the OUTPUT terminal OUTPUT1 of the first stage shift register unit GOA1 and the first power supply terminal VGL, so as to reduce noise of the OUTPUT terminal OUTPUT1 of the first stage shift register unit GOA1, and the second pull-down transistor T5 responds to the active level signal of the pull-down node PD to turn on the pull-up control node PU _ CN and the first power supply terminal VGL, so as to reduce noise of the pull-up control node PU _ CN.

For the second stage shift register unit GOA2, which is between the reset stage and the noise reduction stage, the pull-down control transistor T7 of the second stage shift register unit GOA2 responds to the inactive level signal of the second clock signal terminal CK2 to disconnect the second clock signal terminal CK2 from the pull-down node PD, the first pull-down transistor T4 responds to the active level signal of the pull-down node PD to connect the OUTPUT terminal OUTPUT2 of the second stage shift register unit GOA2 to the first power terminal VGL, so as to reduce the noise of the OUTPUT terminal OUTPUT2 of the second stage shift register unit GOA2, and the second pull-down transistor T5 responds to the active level signal of the pull-down node PD to connect the pull-up control node PU _ CN to the first power terminal VGL, so as to reduce the noise of the pull-up control node PU _ CN.

For the third stage GOA3, between the OUTPUT stage and the reset stage, the level of the pull-up node PU _ CN is lowered due to the inactive signal provided by the first clock terminal CK1, but the level of the pull-up node PU _ CN still enables the OUTPUT transistor T3 to be turned on, so that the inactive level signal of the first clock terminal CK1 is transmitted to the OUTPUT terminal OUTPUT3 of the third stage GOA 3.

For the fourth stage shift register unit GOA4, at this time, between the charging stage and the OUTPUT stage, the inactive level signal of the OUTPUT terminal OUTPUT of the third stage shift register unit GOA2 is transmitted to the INPUT terminal INPUT of the fourth stage shift register unit GOA4, the INPUT transistor T1 of the fourth stage shift register unit GOA4 is turned off, and the third pull-down transistor T6 turns on the first power source terminal VGL and the pull-down node PD in response to the active level signal of the pull-up control node PU _ CN, thereby pulling down the pull-down node PD. The OUTPUT transistor T3 responds to the active level signal of the pull-up control node PU _ CN to turn on the first clock signal terminal CK1 and the OUTPUT terminal OUTPUT4 of the fourth stage shift register unit GOA4, so as to transmit the inactive level signal of the first clock signal terminal CK1 to the OUTPUT terminal OUTPUT4 of the fourth stage shift register unit GOA 4.

At the stage Tg, the fourth clock signal output terminal CLK4 outputs an active level signal, and the first, second, and third clock signal output terminals CLK1, CLK2, and CLK3 all output an inactive level signal.

For the second stage shift register unit GOA2, at this time, in the noise reduction stage, the pull-down control transistor T7 of the second stage shift register unit GOA2 responds to the inactive level signal of the second clock signal terminal CK2 to disconnect the second clock signal terminal CK2 from the pull-down node PD, the first pull-down transistor T4 responds to the active level signal of the pull-down node PD to connect the OUTPUT terminal OUTPUT2 of the second stage shift register unit GOA2 to the first power terminal VGL, so as to reduce the noise of the OUTPUT terminal OUTPUT2 of the second stage shift register unit GOA2, and the second pull-down transistor T5 responds to the active level signal of the pull-down node PD to connect the pull-up control node PU _ CN to the first power terminal VGL, so as to reduce the noise of the pull-up control node PU _ CN.

For the third stage shift register unit GOA3, in the reset stage, the valid level signal of the OUTPUT terminal OUTPUT4 of the fourth stage shift register unit GOA4 is transmitted to the reset terminal REST of the third stage shift register unit GOA3, and the reset transistor T2 of the third stage shift register unit GOA3 responds to the valid level signal of the reset terminal REST to connect the pull-up control node PU _ CN with the third power terminal CNB, so as to reset the pull-up control node PU _ CN. The pull-down control transistor T7 turns on the pull-down node PD with the second clock signal terminal CK2 in response to the active level signal of the second clock signal terminal CK2 to charge the pull-down node PD, and the first pull-down transistor T4 turns on the OUTPUT terminal OUTPUT3 of the third stage shift register unit GOA3 with the first power supply terminal VGL in response to the active level signal of the pull-down node PD to reset the OUTPUT terminal OUTPUT3 of the third stage shift register unit GOA 3.

For the fourth stage shift register unit GOA4, it is in the OUTPUT stage, at this time, the OUTPUT transistor T3 of the fourth stage shift register unit GOA4 is fully turned on, and transmits the active level signal of the second clock signal terminal CK2 to the OUTPUT terminal OUTPUT4 of the fourth stage shift register unit GOA4, and the fourth pull-down transistor T8 responds to the active level signal of the OUTPUT terminal OUTPUT4 of the fourth stage shift register unit GOA4, and turns on the pull-down node PD and the first power terminal VGL, thereby pulling down the pull-down node PD.

In the phase Th, the first, second, third and fourth clock signal output terminals CLK1, CLK2, CLK3 and CLK4 all output an inactive level signal.

For the second stage shift register unit GOA2, at this time, the first pull-down transistor T4 of the second stage shift register unit GOA2 responds to the active level signal of the pull-down node PD to turn on the OUTPUT terminal OUTPUT2 of the second stage shift register unit GOA2 and the first power supply terminal VGL, so as to reduce noise of the OUTPUT terminal OUTPUT2 of the second stage shift register unit GOA2, and the second pull-down transistor T5 responds to the active level signal of the pull-down node PD to turn on the pull-up control node PU _ CN and the first power supply terminal VGL, so as to reduce noise of the pull-up control node PU _ CN.

For the third level shift register unit GOA3, which is between the reset stage and the noise reduction stage, the pull-down control transistor T7 of the third level shift register unit GOA3 responds to the inactive level signal of the second clock signal terminal CK2 to disconnect the second clock signal terminal CK2 from the pull-down node PD, the first pull-down transistor T4 responds to the active level signal of the pull-down node PD to connect the OUTPUT terminal OUTPUT3 of the third level shift register unit GOA3 to the first power terminal VGL, so as to reduce the noise of the OUTPUT terminal OUTPUT3 of the third level shift register unit GOA3, and the second pull-down transistor T5 responds to the active level signal of the pull-down node PD to connect the pull-up control node PU _ CN to the first power terminal VGL, so as to reduce the noise of the pull-up control node PU _ CN.

For the fourth stage shift register unit GOA4, between the OUTPUT stage and the reset stage, the voltage level of the pull-up node PU _ CN drops due to the inactive signal provided by the first clock terminal CK1, but the voltage level of the pull-up node PU _ CN still enables the OUTPUT transistor T3 to turn on, so that the inactive level signal of the first clock terminal CK1 is transmitted to the OUTPUT terminal OUTPUT4 of the fourth stage shift register unit GOA 4.

In summary, the gate driving circuit according to the embodiment of the invention can prevent the second clock signal terminal CK2 and the first power terminal VGL in each shift register unit from forming a dc path in the first scanning state (i.e. the forward scanning state), thereby avoiding electrical loss. It is understood that, the gate driving circuit according to the embodiment of the present invention can also prevent the second clock signal terminal CK2 in each shift register unit from forming a dc path with the first power source terminal VGL in the second scanning state (i.e. the reverse scanning state), and fig. 8 is a second schematic structural diagram of the gate driving circuit according to the embodiment of the present invention, as shown in fig. 8, in some embodiments, the plurality of shift register units are divided into a plurality of groups, each group includes four cascaded shift register units, and the plurality of clock signal output terminals of the driving module include: the first, second, third and fourth clock signal output terminals CLK1, CLK2, CLK3 and CLK4, and the fourth, third, second and first clock signal output terminals CLK4, CLK3, CLK2 and CLK1 sequentially output active level signals.

For a group of shift register units, the first clock signal terminal CK1 of the first stage shift register unit GOA1 is connected to the first clock signal output terminal CLK1, the second clock signal terminal CK2 of the first stage shift register unit GOA1 is connected to the fourth clock signal output terminal CLK4, the first clock signal terminal CK1 of the second stage shift register unit GOA2 is connected to the second clock signal output terminal CLK2, the second clock signal terminal CK2 of the second stage shift register unit GOA2 is connected to the first clock signal output terminal CLK1, the first clock signal terminal CK1 of the third stage shift register unit GOA3 is connected to the third clock signal output terminal CLK3, the second clock signal terminal CK2 of the third stage shift register unit GOA3 is connected to the second clock signal output terminal CLK2, the first clock signal terminal CK1 of the fourth stage shift register unit GOA4 is connected to the fourth clock signal output terminal CLK4, and the fourth stage shift register unit GOA 828653 is connected to the fourth stage shift register unit GOA 86 2.

The timing sequence adopted by the gate driving circuit with the above structure may refer to the foregoing, and is not described herein again, it should be noted that when the shift register units are in the second scanning state, the gate driving circuit may prevent the second clock signal terminal CK2 in each shift register unit from forming a dc path with the first power supply terminal VGL at this time when the shift register units should provide an active level signal to the third power supply terminal CNB and provide an inactive level signal to the second power supply terminal CN.

By adopting the gate driving circuit of the embodiment of the invention, on the basis of not increasing the number of transistors, the problem that the second clock signal terminal CK2 and the first power supply terminal VGL form a direct current path is solved, and the power consumption can be effectively reduced.

An embodiment of the present invention further provides a display device, including: a gate drive circuit above. The display device further comprises a display substrate, wherein the display substrate is provided with a display area, the grid driving circuit is arranged on at least one side of the display area, and the grid driving circuit is connected with the grid lines in the display area and used for providing driving signals for the grid lines.

In some embodiments, the gate driving circuit includes two shift registers, wherein the shift register units in one shift register are connected to the odd-numbered gate lines in the display area in a one-to-one correspondence manner, and the shift register units in the other shift register are connected to the even-numbered gate lines in the display area in a one-to-one correspondence manner.

The display device may be: any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.

Claims

1. A driving method of a shift register unit, the shift register unit comprising: the circuit comprises an input sub-circuit, an output sub-circuit, a reset sub-circuit, a first pull-down sub-circuit and a pull-down control sub-circuit; the input sub-circuit is connected with the input end of the shift registering unit and the pull-up control node, the output sub-circuit is connected with the pull-up control node, the output end of the shift registering unit and the first clock signal end, the reset sub-circuit is connected with the reset end and the pull-up control node, the first pull-down sub-circuit is connected with the pull-up control node, the pull-down node and the first power end, and the pull-down control sub-circuit is connected with the second clock signal end and the pull-down node; the method for driving the shift register unit is characterized by comprising the following steps:

2. The method according to claim 1, wherein said input sub-circuit is further connected to a second power supply terminal, said reset sub-circuit is further connected to a third power supply terminal, said shift register cell has a first scanning state and a second scanning state,

3. The method according to claim 1, wherein the shift register unit further comprises a touch reset sub-circuit, the touch reset sub-circuit is connected to a touch reset terminal, the first power terminal and the output terminal of the shift register unit, and the method further comprises:

4. The method as claimed in claim 1, wherein the shift register unit further comprises a gate sub-circuit connected between the output sub-circuit and the pull-up control node and connected to a gate control terminal, the method further comprising:

5. A gate driving circuit, comprising a driving module and at least one shift register, wherein the shift register comprises a plurality of cascaded shift register units, the shift register unit is the shift register unit of any one of claims 1 to 4, the driving module has a plurality of clock signal output terminals, and the first clock signal terminal and the second clock signal terminal of each shift register unit are connected to one of the clock signal output terminals;

6. A gate drive circuit as claimed in claim 5, wherein the drive module is further configured to: and in a frame starting stage, providing a frame starting signal to the input end of the first shift register unit or the reset end of the last shift register unit.

7. A gate driver circuit as claimed in claim 5, wherein the shift register unit is as claimed in claim 2, and the driver module is further configured to:

8. The gate driving circuit of claim 5, wherein the plurality of shift register units are divided into a plurality of groups, each group includes four cascaded shift register units, and the plurality of clock signal output terminals of the driving module includes: a first clock signal output end, a second clock signal output end, a third clock signal output end and a fourth clock signal output end, wherein the first clock signal output end, the second clock signal output end, the third clock signal output end and the fourth clock signal output end sequentially output effective level signals;

9. The gate driving circuit of claim 5, wherein the plurality of shift register units are divided into a plurality of groups, each group includes four cascaded shift register units, and the plurality of clock signal output terminals of the driving module includes: a first clock signal output end, a second clock signal output end, a third clock signal output end and a fourth clock signal output end, wherein the fourth clock signal output end, the third clock signal output end, the second clock signal output end and the first clock signal output end sequentially output effective level signals;

10. A display device, comprising: a gate drive circuit as claimed in any one of claims 5 to 9.