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CN111602239B - Power semiconductor module - Google Patents

Power semiconductor module Download PDF

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Publication number
CN111602239B
CN111602239B CN201980008305.8A CN201980008305A CN111602239B CN 111602239 B CN111602239 B CN 111602239B CN 201980008305 A CN201980008305 A CN 201980008305A CN 111602239 B CN111602239 B CN 111602239B
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CN
China
Prior art keywords
heat dissipation
power semiconductor
dissipation substrate
semiconductor module
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201980008305.8A
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Chinese (zh)
Other versions
CN111602239A (en
Inventor
朴益圣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Amosense Co Ltd
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Amosense Co Ltd
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Publication date
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Publication of CN111602239A publication Critical patent/CN111602239A/en
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Publication of CN111602239B publication Critical patent/CN111602239B/en
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    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/181—Encapsulation

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Abstract

The invention relates to a power semiconductor module comprising: a first heat-dissipating substrate; a semiconductor chip; a lead plate; a PCB; and a heat spreader, the first heat spreading substrate, the semiconductor chip, the lead plate, the PCB, and the heat spreader being packaged in the case. Since the heat dissipation structure is doubly applied, the power semiconductor module may exhibit excellent heat dissipation performance as compared to the conventional art.

Description

功率半导体模块Power semiconductor module

技术领域Technical field

本发明涉及一种功率半导体模块。更具体地，本发明涉及一种具有改善的散热性能的功率半导体模块。The invention relates to a power semiconductor module. More specifically, the present invention relates to a power semiconductor module with improved heat dissipation performance.

背景技术Background technique

功率半导体模块是通过使功率半导体芯片作为封装件中的模块而被优化以进行功率转换或控制的半导体模块。特别地，绝缘栅双极型晶体管（IGBT）是一种类型的功率半导体，并且是用于高功率开关的半导体。A power semiconductor module is a semiconductor module optimized for power conversion or control by having a power semiconductor chip as a module in a package. In particular, an insulated gate bipolar transistor (IGBT) is a type of power semiconductor, and is a semiconductor used for high-power switching.

阻挡或允许电流流动的开关功能可通过其他部件或电路实现。然而，要求精确运作的产品需要运作速度快且功率损耗低的专用部件。The switching function of blocking or allowing the flow of current can be implemented by other components or circuits. However, products that require precise operation require specialized components that operate quickly and consume low power.

然而，作为开关半导体的晶体管具有较高的生产率，但是其电路构造复杂且运作速度慢。MOSFET的功耗低且运作速度快，但是成本较高。IGBT是只有晶体管与MOSFET的优点的结合。However, transistors as switching semiconductors have high productivity, but their circuit structure is complex and their operation speed is slow. MOSFET has low power consumption and fast operation, but the cost is high. IGBT is a combination of only transistor and the advantages of MOSFET.

包括IGBT模块等的功率半导体模块具有如下结构：在该结构中，衬底被放置在基板上并且半导体芯片被放置在衬底上。Power semiconductor modules including IGBT modules and the like have a structure in which a substrate is placed on a substrate and a semiconductor chip is placed on the substrate.

在此，半导体芯片通过与由铝材料制成的导线键合而电连接至衬底，此外，衬底具有通过导线键合而连接至PCB的结构。热阻对散热特性非常重要。关于每种材料的热阻（以W/m-K为单位），作为陶瓷衬底的AIN衬底的热阻为180W/m-K；Al2O3的热阻为21W/m-K；Si3N4的热阻为80W/m-K；作为金属的铜（Cu）的热阻为390W/m-K；焊料的热阻为35W/m-K至60W/m-K；半导体芯片的掺杂硅（掺杂Si）的热阻约为70W/m-K。因此，需要进一步研究以解决功率半导体模块的发热问题。Here, the semiconductor chip is electrically connected to the substrate by bonding with wires made of aluminum material, and further, the substrate has a structure connected to the PCB by wire bonding. Thermal resistance is very important for heat dissipation characteristics. Regarding the thermal resistance (in W/mK) of each material, the thermal resistance of the AIN substrate as a ceramic substrate is 180W/mK; the thermal resistance of Al 2 O 3 is 21 W/mK; the thermal resistance of Si 3 N 4 The thermal resistance of copper (Cu) as a metal is 390W/mK; the thermal resistance of solder is 35W/mK to 60W/mK; the thermal resistance of doped silicon (doped Si) of semiconductor chips is approximately 70W/mK. Therefore, further research is needed to solve the heating problem of power semiconductor modules.

图1和图2示出了常规的功率半导体模块。Figures 1 and 2 show conventional power semiconductor modules.

如图1所示，功率半导体模块100具有如下结构：在该结构中，IGBT 11A和二极管11B被附接在衬底10上；键合导线13连接IGBT 11A、二极管11B和控制IC 11C；被布置在旁边的PCB 12通过引线框15连接；并且这些元件被封装在壳体14中。As shown in FIG. 1 , the power semiconductor module 100 has a structure in which an IGBT 11A and a diode 11B are attached to a substrate 10 ; a bonding wire 13 connects the IGBT 11A, the diode 11B and a control IC 11C; and is arranged The PCB 12 on the side is connected through the lead frame 15; and these components are packaged in the housing 14.

另外，如图2所示，功率半导体模块200具有封装结构，在该封装结构中，基板23通过导热油脂22形成在散热器21上；基板23经由下部基板焊料24附接到衬底28上；IGBT 26A和二极管26B经由上部芯片焊料25附接到衬底28上；IGBT 26A和二极管26B通过引线框27连接。In addition, as shown in Figure 2, the power semiconductor module 200 has a packaging structure in which the substrate 23 is formed on the heat sink 21 through the thermal grease 22; the substrate 23 is attached to the substrate 28 via the lower substrate solder 24; IGBT 26A and diode 26B are attached to substrate 28 via upper chip solder 25 ; IGBT 26A and diode 26B are connected through leadframe 27 .

图1和图2的功率半导体模块使热量通过设置在基板下表面的下方的散热器等消散。然而，在这些结构中，热量仅沿一个方向消散，使得在将热量从功率半导体模块中消散方面存在限制。因此，需要进一步研究以改善散热结构。在专利文献1中，公开了一种常规的功率半导体模块。The power semiconductor module of FIGS. 1 and 2 dissipates heat through a heat sink or the like provided below the lower surface of the substrate. However, in these structures, heat is dissipated in only one direction, so that there are limitations in dissipating heat from the power semiconductor module. Therefore, further research is needed to improve the heat dissipation structure. In Patent Document 1, a conventional power semiconductor module is disclosed.

在该背景技术部分中公开的上述信息仅用于加强对本发明的背景技术的理解，因此，其可能包含不构成本领域普通技术人员已知的相关技术的信息。The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the related art that is already known to a person of ordinary skill in the art.

（专利文献1）公开号为10-2015-0089609的韩国专利申请公开(Patent document 1) Korean patent application publication number 10-2015-0089609

发明内容Contents of the invention

技术问题technical problem

因此，本发明是在考虑到上述问题的情况下做出的，并且本发明旨在提供一种具有改善的散热性能的功率半导体模块。Therefore, the present invention has been made in consideration of the above-mentioned problems, and aims to provide a power semiconductor module with improved heat dissipation performance.

技术方案Technical solutions

本发明提供了一种功率半导体模块，该功率半导体包括：第一散热衬底；半导体芯片，该半导体芯片被布置在第一散热衬底上，并且以倒装芯片的形式键合到第一散热衬底上；以及热界面材料层（TIM层），该热界面材料层被布置在半导体芯片上。The present invention provides a power semiconductor module, which includes: a first heat dissipation substrate; a semiconductor chip arranged on the first heat dissipation substrate and bonded to the first heat dissipation chip in the form of a flip chip on the substrate; and a thermal interface material layer (TIM layer) arranged on the semiconductor chip.

根据本发明的示例，PCB可以形成在TIM层上。According to examples of the present invention, a PCB may be formed on the TIM layer.

另外，第二散热衬底可以形成在PCB上，并且第二散热衬底可以是平板型、引脚型或鳍型的。In addition, the second heat dissipation substrate may be formed on the PCB, and the second heat dissipation substrate may be a flat plate type, a pin type, or a fin type.

根据本发明的另一示例，第二散热衬底的下部部分可以形成为穿透PCB并与TIM接触。According to another example of the present invention, the lower portion of the second heat dissipation substrate may be formed to penetrate the PCB and contact the TIM.

另外，第一铜层可以形成在TIM层的上侧，第二铜层可以形成在TIM层的下侧，并且第二散热衬底的下部部分可以在TIM层的上侧处与第一铜层接触。In addition, the first copper layer may be formed on an upper side of the TIM layer, the second copper layer may be formed on a lower side of the TIM layer, and the lower portion of the second heat dissipation substrate may be in contact with the first copper layer at the upper side of the TIM layer. touch.

根据本发明的另一示例，可以在半导体芯片上设置引线板，并且可以设置粘合剂层以附接引线板和PCB。According to another example of the present invention, a lead board may be provided on the semiconductor chip, and an adhesive layer may be provided to attach the lead board and the PCB.

另外，粘合剂层可以由各自具有1nm至5nm的直径的纳米颗粒组成，并且可以具有多孔结构。In addition, the adhesive layer may be composed of nanoparticles each having a diameter of 1 nm to 5 nm, and may have a porous structure.

根据本发明的另一示例，TIM层可以由选自氧化铝、氮化硅、氮化铝、氧化锌、二氧化钛以及二氧化硅中的任何一种制成。According to another example of the present invention, the TIM layer may be made of any one selected from aluminum oxide, silicon nitride, aluminum nitride, zinc oxide, titanium dioxide, and silicon dioxide.

根据本发明的另一示例，TIM层可以通过使选自氧化铝、氮化硅、氮化铝、氧化锌、二氧化钛和二氧化硅中的任何一种以颗粒的形式分散在聚合物中来形成。According to another example of the present invention, the TIM layer may be formed by dispersing any one selected from the group consisting of aluminum oxide, silicon nitride, aluminum nitride, zinc oxide, titanium dioxide, and silicon dioxide in the form of particles in a polymer. .

另外，聚合物可以是选自聚四氟乙烯（PTFE）、聚对苯二甲酸乙二酯（PET）、聚醚砜（PES）、聚酰亚胺（PI）、聚碳酸酯（PC）、聚氨酯（PU）、聚甲基丙烯酸甲酯（PMMA）以及聚萘二甲酸乙二醇酯（PEN）中的任何一种。In addition, the polymer may be selected from polytetrafluoroethylene (PTFE), polyethylene terephthalate (PET), polyethersulfone (PES), polyimide (PI), polycarbonate (PC), Any of polyurethane (PU), polymethyl methacrylate (PMMA), and polyethylene naphthalate (PEN).

根据本发明的另一示例，TIM层可以设置有通过选自钎焊、氧化、电镀和粘贴中的任何一种方法而形成在TIM层的相对表面上的铜层。According to another example of the present invention, the TIM layer may be provided with a copper layer formed on an opposite surface of the TIM layer by any one method selected from soldering, oxidation, electroplating, and pasting.

根据本发明的另一示例，半导体芯片可以使用选自铜（Cu）、银（Ag）、铝（Al）、镍（Ni）、锡（Sn）和钼（Mo）中的两种或两种以上的合金或任何一种来进行键合。According to another example of the present invention, the semiconductor chip may use two or two selected from copper (Cu), silver (Ag), aluminum (Al), nickel (Ni), tin (Sn) and molybdenum (Mo). Alloys or any of the above for bonding.

根据本发明的另一示例，半导体芯片可以包括绝缘栅双极型晶体管（IGBT）和二极管。According to another example of the present invention, a semiconductor chip may include an insulated gate bipolar transistor (IGBT) and a diode.

根据本发明的另一示例，可以提供用于使功率半导体模块密闭的壳体；第一散热衬底可以形成为与壳体的下部接触，并且第二散热衬底可以形成为与壳体的上部接触。According to another example of the present invention, a case for sealing the power semiconductor module may be provided; the first heat dissipation substrate may be formed in contact with a lower part of the case, and the second heat dissipation substrate may be formed in contact with an upper part of the case touch.

根据本发明的另一示例，可以提供用于使功率半导体模块密闭的壳体；在壳体的下部，第一散热衬底的一部分可以形成为穿透壳体并向外部突出，并且在壳体的上部，第二散热衬底的一部分可以形成为穿透壳体并向外部突出。According to another example of the present invention, a housing for sealing the power semiconductor module may be provided; at a lower part of the housing, a part of the first heat dissipation substrate may be formed to penetrate the housing and protrude to the outside, and in the lower part of the housing On the upper part, a part of the second heat dissipation substrate may be formed to penetrate the housing and protrude to the outside.

本发明提供了一种功率半导体模块，该功率半导体模块包括：第一散热衬底，该第一散热衬底为基板；具有多层结构的衬底，该具有多层结构的衬底形成在第一散热衬底上；半导体芯片，该半导体芯片被布置在具有多层结构的衬底上，并且通过键合到具有多层结构的衬底上而以倒装芯片的形式形成；引线板，该引线板被布置在半导体芯片上；形成在引线板上的热界面材料层（TIM层）；以及形成在TIM层上的第二散热衬底。The invention provides a power semiconductor module. The power semiconductor module includes: a first heat dissipation substrate, which is a substrate; a substrate with a multi-layer structure, the substrate with a multi-layer structure is formed on a first on a heat dissipation substrate; a semiconductor chip which is arranged on a substrate having a multi-layer structure and is formed in the form of a flip chip by bonding to the substrate having a multi-layer structure; a lead board, which A lead plate is arranged on the semiconductor chip; a thermal interface material layer (TIM layer) formed on the lead plate; and a second heat dissipation substrate formed on the TIM layer.

根据本发明的另一示例，第二散热衬底可以是平板型、引脚型或鳍型的。According to another example of the present invention, the second heat dissipation substrate may be a flat plate type, a pin type, or a fin type.

根据本发明的另一示例，可以在第二散热衬底上设置用于覆盖功率半导体模块的板型壳体，并且第二散热衬底的上部部分可以形成为与壳体的下表面接触。According to another example of the present invention, a plate-type case covering the power semiconductor module may be provided on the second heat dissipation substrate, and an upper portion of the second heat dissipation substrate may be formed in contact with a lower surface of the case.

根据本发明的另一示例，可以在第二散热衬底上设置用于覆盖功率半导体模块的板型壳体，并且第二散热衬底的一部分可以形成为穿透壳体。According to another example of the present invention, a plate-shaped case for covering the power semiconductor module may be provided on the second heat dissipation substrate, and a part of the second heat dissipation substrate may be formed to penetrate the case.

根据本发明的另一示例，半导体芯片可以包括绝缘栅双极型晶体管（IGBT）和二极管。According to another example of the present invention, a semiconductor chip may include an insulated gate bipolar transistor (IGBT) and a diode.

有利效果beneficial effect

在常规的功率半导体模块中，半导体芯片通过导线键合进行电连接，由于导线由铝材料制成，因此难以将散热装置设计成放置在半导体芯片的上方。In a conventional power semiconductor module, the semiconductor chips are electrically connected through wire bonding. Since the wires are made of aluminum material, it is difficult to design the heat sink to be placed above the semiconductor chip.

根据本发明的功率半导体模块，应用了引线板而不是由铝材料制成的导线，并且散热板被放置在半导体芯片的上方，从而通过竖直双向散热促进了优异的散热性能。According to the power semiconductor module of the present invention, a lead plate is applied instead of wires made of aluminum material, and the heat dissipation plate is placed above the semiconductor chip, thereby promoting excellent heat dissipation performance through vertical bidirectional heat dissipation.

另外，PCB被放置在半导体芯片的上方，从而减小了整个壳体的尺寸。In addition, the PCB is placed above the semiconductor chip, thereby reducing the size of the entire case.

附图说明Description of the drawings

图1和图2示出了常规的功率半导体模块。Figures 1 and 2 show conventional power semiconductor modules.

图3示出了根据本发明的功率半导体模块的实施例。Figure 3 shows an embodiment of a power semiconductor module according to the invention.

图4A、图4B和图4C示出了其中散热衬底被附接到壳体上的示意图的示例。4A, 4B, and 4C show examples of schematic diagrams in which a heat dissipation substrate is attached to a housing.

图5A、图5B和图5C示出了其中散热衬底被附接到壳体上的示意图的另一示例。5A, 5B, and 5C show another example of a schematic diagram in which a heat dissipation substrate is attached to a housing.

图6示出了根据本发明的功率半导体模块的另一实施例。Figure 6 shows another embodiment of a power semiconductor module according to the invention.

具体实施方式Detailed ways

为了充分理解本发明，应当参考本发明的运作优点、由本发明的实施例实现的目标、本文描述的说明了本发明的示例性实施例的附图和内容。For a full understanding of the present invention, reference should be made to its operational advantages, objectives achieved by embodiments of the invention, to the drawings and content described herein illustrating exemplary embodiments of the invention.

在描述本发明的示例性实施例时，将缩短或省略对使本发明的主题不清楚的已知技术的描述或重复描述。In describing exemplary embodiments of the present invention, descriptions of known technologies that make the subject matter of the present invention unclear will be shortened or omitted or repeated descriptions will be shortened or omitted.

在下文中，将参照图3至图6描述根据本发明的实施例的功率半导体模块。Hereinafter, a power semiconductor module according to an embodiment of the present invention will be described with reference to FIGS. 3 to 6 .

（第一实施例）(First Embodiment)

图3示出了根据本发明的第一实施例的功率半导体模块。Figure 3 shows a power semiconductor module according to a first embodiment of the invention.

本发明的功率半导体模块300可以包括：第一散热衬底32；半导体芯片33，该半导体芯片被布置在第一散热衬底32上并且以倒装芯片的形式键合到第一散热衬底32上；以及热界面材料层（TIM层）38，该热界面材料层被布置在半导体芯片33上。The power semiconductor module 300 of the present invention may include: a first heat dissipation substrate 32; a semiconductor chip 33 disposed on the first heat dissipation substrate 32 and bonded to the first heat dissipation substrate 32 in a flip chip form and a thermal interface material layer (TIM layer) 38 , which is arranged on the semiconductor chip 33 .

本发明的第一散热衬底32可被用作具有多层结构的衬底与基板（未示出）的结合。具有多层结构的衬底可以是诸如金属-陶瓷衬底、陶瓷-金属衬底、金属-陶瓷-金属衬底等的多层衬底，并且优选地是直接键合铜（DBC）衬底，该直接键合铜衬底是铜（Cu）-陶瓷-铜（Cu）叠层。The first heat dissipation substrate 32 of the present invention may be used as a substrate having a multi-layer structure in combination with a substrate (not shown). The substrate having a multilayer structure may be a multilayer substrate such as a metal-ceramic substrate, a ceramic-metal substrate, a metal-ceramic-metal substrate, and the like, and is preferably a direct bonded copper (DBC) substrate, The direct bonded copper substrate is a copper (Cu)-ceramic-copper (Cu) stack.

在基板被布置在具有多层结构的衬底的下方的情况下，具有多层结构的衬底可以以整体的方式设置在基板上，或者具有多层结构的衬底可以以经由键合层（例如焊接）键合到基板上的方式形成。在具有多层结构的衬底以整体的方式设置在基板上的情况下，基板与具有多层结构的衬底之间的焊料被移除，使散热性能得到改善。In the case where the substrate is disposed below the substrate having a multilayer structure, the substrate having the multilayer structure may be integrally provided on the substrate, or the substrate having the multilayer structure may be disposed via a bonding layer ( For example, welding) is bonded to the substrate. In the case where the substrate with the multi-layer structure is integrally disposed on the substrate, the solder between the substrate and the substrate with the multi-layer structure is removed, so that the heat dissipation performance is improved.

本发明的半导体芯片33可以被布置在第一散热衬底32上并且以倒装芯片的形式键合到第一散热衬底32上。焊接可用于将半导体芯片33附接到衬底上。当将半导体芯片33附接到电路衬底时，使用半导体芯片33的底表面处的电极图案并使该电极图案按原样熔融，而无需使用诸如金属引线的附加连接结构或诸如球栅阵列的中间介质，从而形成倒装芯片的形式。如上文所述，由于不使用引线，本发明有利于小尺寸制造和减轻重量，并且还有利于散热特性，原因是电极之间的距离非常小。特别地，由于半导体芯片33具有倒装芯片的形式，因此通过双向散热改善了散热性能，并且降低了掺杂硅的热阻，从而改善了芯片接合部的接触散热。The semiconductor chip 33 of the present invention may be disposed on the first heat dissipation substrate 32 and bonded to the first heat dissipation substrate 32 in a flip-chip manner. Soldering may be used to attach the semiconductor chip 33 to the substrate. When the semiconductor chip 33 is attached to the circuit substrate, the electrode pattern at the bottom surface of the semiconductor chip 33 is used and the electrode pattern is melted as it is without using an additional connection structure such as a metal lead or an intermediate such as a ball grid array. dielectric, thus forming a flip-chip form. As mentioned above, since no wires are used, the present invention facilitates small size manufacturing and weight reduction, and also facilitates heat dissipation characteristics since the distance between electrodes is very small. In particular, since the semiconductor chip 33 has the form of a flip chip, the heat dissipation performance is improved through bidirectional heat dissipation, and the thermal resistance of the doped silicon is reduced, thereby improving the contact heat dissipation of the chip joint.

本发明的半导体芯片33可以是二极管、IGBT元件等。可以使用选自铜（Cu）、银（Ag）、铝（Al）、镍（Ni）、锡（Sn）和钼（Mo）中的两种或两种以上的合金或者任何一种来实现键合，但不限于此。The semiconductor chip 33 of the present invention may be a diode, an IGBT element, or the like. The bond may be realized using two or more alloys or any one selected from copper (Cu), silver (Ag), aluminum (Al), nickel (Ni), tin (Sn) and molybdenum (Mo). combination, but not limited to this.

本发明的TIM层38可以形成在引线板34上，并且引线板34可以形成在半导体芯片33上。TIM层38可以由选自氧化铝、氮化硅、氮化铝、氧化锌、二氧化钛、二氧化硅中的任何一种制成。替代地，可以通过使选自氧化铝、氮化硅、氮化铝、氧化锌、二氧化钛和二氧化硅中的任何一种以颗粒的形式分散在聚合物中来形成TIM层38。选自聚四氟乙烯（PTFE）、聚对苯二甲酸乙二酯（PET）、聚醚砜（PES）、聚酰亚胺（PI）、聚碳酸酯（PC）、聚氨酯（PU）、聚甲基丙烯酸甲酯（PMMA）和聚萘二甲酸乙二醇酯（PEN）中的任何一种可用作聚合物，但不限于此。如上文所述，将无机膜颗粒分散在聚合物中使用，从而产生弹性。The TIM layer 38 of the present invention may be formed on the lead plate 34 , and the lead plate 34 may be formed on the semiconductor chip 33 . The TIM layer 38 may be made of any one selected from the group consisting of aluminum oxide, silicon nitride, aluminum nitride, zinc oxide, titanium dioxide, and silicon dioxide. Alternatively, the TIM layer 38 may be formed by dispersing any one selected from the group consisting of aluminum oxide, silicon nitride, aluminum nitride, zinc oxide, titanium dioxide, and silicon dioxide in the form of particles in a polymer. Selected from polytetrafluoroethylene (PTFE), polyethylene terephthalate (PET), polyethersulfone (PES), polyimide (PI), polycarbonate (PC), polyurethane (PU), poly Any one of methyl methacrylate (PMMA) and polyethylene naphthalate (PEN) can be used as the polymer, but is not limited thereto. As mentioned above, inorganic film particles are used dispersed in polymers to create elasticity.

关于TIM层38，可以通过选自钎焊、氧化、电镀和粘贴中的任何一种方法在TIM层38的相对表面上形成铜层。此外，可以在TIM层38的上侧形成第一铜层，并且可以在TIM层38的下侧形成第二铜层。第二散热衬底37的下部部分可以以与TIM层38的上侧处的第一铜层接触的方式形成。Regarding the TIM layer 38, a copper layer may be formed on the opposite surface of the TIM layer 38 by any method selected from soldering, oxidation, electroplating, and pasting. In addition, a first copper layer may be formed on the upper side of TIM layer 38 , and a second copper layer may be formed on the lower side of TIM layer 38 . The lower portion of the second heat dissipation substrate 37 may be formed in contact with the first copper layer at the upper side of the TIM layer 38 .

本发明的PCB 35可以形成在TIM层38上。如上文所述，由于PCB 35被设置在半导体芯片33的上方，因此与PCB被布置在半导体芯片一侧处的情况相比，设计了减小壳体39的尺寸的功率半导体模块。The PCB 35 of the present invention may be formed on the TIM layer 38. As described above, since the PCB 35 is disposed above the semiconductor chip 33, the power semiconductor module is designed in which the size of the housing 39 is reduced compared to the case where the PCB is disposed at one side of the semiconductor chip.

本发明的第二散热衬底37可以形成在PCB 35上。第二散热衬底37可以是平板型、引脚型或鳍型的。第二散热衬底37的下部部分形成为穿透PCB 35并且与TIM接触，从而有利于散热特性。The second heat dissipation substrate 37 of the present invention may be formed on the PCB 35. The second heat dissipation substrate 37 may be of flat plate type, pin type or fin type. The lower portion of the second heat dissipation substrate 37 is formed to penetrate the PCB 35 and contact the TIM, thereby facilitating heat dissipation characteristics.

根据本发明的功率半导体模块在下部位置处设置有第一散热衬底32并且在上部位置处设置有第二散热衬底37，从而通过散热结构的二重化促进了优异的散热性能。例如，通过第二散热衬底37从引线板34向上进行散热，并且通过第一散热衬底32从半导体芯片33向下进行散热。关于向下散热的性能，可以通过在基板的下方设置散热器来进行散热。The power semiconductor module according to the present invention is provided with the first heat dissipation substrate 32 at the lower position and the second heat dissipation substrate 37 at the upper position, thereby promoting excellent heat dissipation performance through duplication of the heat dissipation structure. For example, heat is dissipated upward from the lead plate 34 through the second heat dissipation substrate 37 , and heat is dissipated downward from the semiconductor chip 33 through the first heat dissipation substrate 32 . Regarding downward heat dissipation performance, heat dissipation can be achieved by placing a heat sink under the substrate.

本发明的引线板34可以被设置在半导体芯片33上。与使用导线相比，引线板34能够电连接半导体芯片33的元件以及高效地将从半导体芯片33产生的热量向上传输至第二散热衬底37。因此，半导体芯片33通过引线板34连接至第一散热衬底32而无需与导线键合，使得与由铝材料制成的导线相比，散热性能可以得到改善。选自铜（Cu）、银（Ag）和铝（Al）中的两种或两种以上的合金或任何一种可用作引线板34，但是就电特性和热传递而言，铜是最优选的。The lead plate 34 of the present invention may be provided on the semiconductor chip 33 . Compared with using wires, the lead plate 34 can electrically connect components of the semiconductor chip 33 and efficiently transmit heat generated from the semiconductor chip 33 upward to the second heat dissipation substrate 37 . Therefore, the semiconductor chip 33 is connected to the first heat dissipation substrate 32 through the lead plate 34 without bonding with wires, so that the heat dissipation performance can be improved compared to wires made of aluminum material. Two or more alloys or any one selected from copper (Cu), silver (Ag) and aluminum (Al) can be used as the lead plate 34, but copper is the most suitable in terms of electrical characteristics and heat transfer. preferred.

为了附接引线板34和PCB 35，可以设置粘合剂层36。PCB 35经由粘合剂层36设置在半导体芯片33的上方，并且PCB 35可以电连接至第一散热衬底32。To attach the lead board 34 and the PCB 35, an adhesive layer 36 may be provided. The PCB 35 is disposed over the semiconductor chip 33 via the adhesive layer 36 , and the PCB 35 may be electrically connected to the first heat dissipation substrate 32 .

散热材料可用作粘合剂层36。例如，可以使用热导率为0.001W/m-K至0.01W/m-K的绝热材料。优选地，使用热导率为0.003W/m-K至0.009W/m-K的绝热材料。更优选地，使用热导率为0.006W/m-K至0.08W/m-K的绝热材料。A heat dissipating material may be used as adhesive layer 36. For example, an insulating material having a thermal conductivity of 0.001 W/m-K to 0.01 W/m-K may be used. Preferably, an insulating material having a thermal conductivity of 0.003 W/m-K to 0.009 W/m-K is used. More preferably, an insulating material with a thermal conductivity of 0.006 W/m-K to 0.08 W/m-K is used.

聚合物可用作具有这种低热导率的粘合剂层36。替代地，可以使用由纳米尺寸的颗粒组成并且具有多孔结构的粘合剂层36。粘合剂层36可以由各自具有1nm至50nm的直径的纳米颗粒组成。优选地，粘合剂层36由各自具有10nm至40nm的直径的纳米颗粒组成。更优选地，使用由各自具有20nm至30nm的直径的纳米颗粒组成的粘合剂层36，并且该粘合剂层还具有多孔结构。例如，气凝胶可用作粘合剂层36。与聚合物相比，通过使用由这种纳米颗粒组成并具有多孔结构的粘合剂层36，可以将热导率降低至1/10至1/100。Polymers can be used as adhesive layer 36 with such low thermal conductivity. Alternatively, an adhesive layer 36 composed of nano-sized particles and having a porous structure may be used. The adhesive layer 36 may be composed of nanoparticles each having a diameter of 1 nm to 50 nm. Preferably, the adhesive layer 36 consists of nanoparticles each having a diameter of 10 nm to 40 nm. More preferably, an adhesive layer 36 composed of nanoparticles each having a diameter of 20 nm to 30 nm is used, and the adhesive layer also has a porous structure. For example, aerogel can be used as adhesive layer 36. By using the adhesive layer 36 composed of such nanoparticles and having a porous structure, the thermal conductivity can be reduced to 1/10 to 1/100 compared to polymers.

本发明的壳体39可以以封装第一散热衬底32、半导体芯片33、引线板34、PCB 35和第二散热衬底37并使封装件密闭的形式来构造。The case 39 of the present invention may be configured in a form to encapsulate the first heat dissipation substrate 32, the semiconductor chip 33, the lead board 34, the PCB 35 and the second heat dissipation substrate 37 and seal the package.

接下来，如图4A、图4B和图4C所示，将描述图3中示出的第一散热衬底32和第二散热衬底37可以形成为与壳体接触或穿过壳体的一部分突出。Next, as shown in FIGS. 4A, 4B, and 4C, it will be described that the first heat dissipation substrate 32 and the second heat dissipation substrate 37 shown in FIG. 3 may be formed in contact with the housing or through a part of the housing. protrude.

例如，如图4A、图4B和图4C所示，第一散热衬底52A至52C和第二散热衬底57A至57C可以形成为与壳体接触。如图4A所示，壳体59A1的上表面与第一散热衬底52A的下表面彼此接触，以实现散热。壳体59A2的下表面与第二散热衬底57A的上表面彼此接触，以实现散热。如图4B所示，壳体59B1的上表面与第一散热衬底52B的引脚彼此接触，以实现散热。壳体59B2的下表面与第二散热衬底57B的引脚彼此接触，以实现散热。如图4C所示，壳体59C1的上表面与第一散热衬底52C的引脚彼此接触，以实现散热。壳体59C2的下表面与第二散热衬底57C的引脚彼此接触，以实现散热。尽管未示出，但是第一散热衬底和第二散热衬底可以以不同的组合促进散热特性。例如，图3中示出的第一散热衬底32和第二散热衬底34是以下各项中的任何一种：图4A中示出的平板型的第一散热衬底52A和第二散热衬底57A；图4B中示出的引脚型的第一散热衬底52B和第二散热衬底57B；以及图4C中示出的鳍型的第一散热衬底52C和第二散热衬底57C。第一散热衬底和第二散热衬底可以以不同的类型被使用。For example, as shown in FIGS. 4A, 4B, and 4C, the first heat dissipation substrates 52A to 52C and the second heat dissipation substrates 57A to 57C may be formed in contact with the housing. As shown in FIG. 4A , the upper surface of the housing 59A1 and the lower surface of the first heat dissipation substrate 52A are in contact with each other to achieve heat dissipation. The lower surface of the housing 59A2 and the upper surface of the second heat dissipation substrate 57A are in contact with each other to achieve heat dissipation. As shown in FIG. 4B , the upper surface of the housing 59B1 and the pins of the first heat dissipation substrate 52B are in contact with each other to achieve heat dissipation. The lower surface of the housing 59B2 and the pins of the second heat dissipation substrate 57B are in contact with each other to achieve heat dissipation. As shown in FIG. 4C , the upper surface of the housing 59C1 and the pins of the first heat dissipation substrate 52C are in contact with each other to achieve heat dissipation. The lower surface of the housing 59C2 and the pins of the second heat dissipation substrate 57C are in contact with each other to achieve heat dissipation. Although not shown, the first heat dissipation substrate and the second heat dissipation substrate may promote heat dissipation characteristics in different combinations. For example, the first heat dissipation substrate 32 and the second heat dissipation substrate 34 shown in FIG. 3 are any of the following: the flat-type first heat dissipation substrate 52A and the second heat dissipation substrate 52A shown in FIG. 4A Substrate 57A; pin type first heat dissipation substrate 52B and second heat dissipation substrate 57B shown in FIG. 4B; and fin type first heat dissipation substrate 52C and second heat dissipation substrate shown in FIG. 4C. 57C. The first heat dissipation substrate and the second heat dissipation substrate may be used in different types.

作为另一示例，图5A、图5B和图5C示出了如下示意图：在该示意图中，图3中示出的第一散热衬底32的一部分和第二散热衬底37的一部分形成为穿过壳体的一部分突出。图5A示出了平板型的第一散热衬底62A的一部分穿过壳体69A的下部突出，并且平板型的第二散热衬底67A的一部分穿过壳体69A的上部突出，以实现散热。图5B示出了引脚型的第一散热衬底62B的引脚穿过壳体69B的下部突出，并且引脚型的第二散热衬底67B的引脚穿过壳体69B的上部突出，以实现散热。图5C示出了鳍型的第一散热衬底62C的鳍穿过壳体69C的下部突出，并且鳍型的第二散热衬底67C的鳍穿过壳体69C的上部突出，以实现散热。尽管未示出，但是第一散热衬底和第二散热衬底可以以不同的组合促进散热特性。例如，第一散热衬底和第二散热衬底中的每一个是平板型、引脚型和鳍型中的任何一种，并且第一散热衬底和第二散热衬底可以以不同的类型被使用。As another example, FIGS. 5A, 5B and 5C show a schematic diagram in which a part of the first heat dissipation substrate 32 and a part of the second heat dissipation substrate 37 shown in FIG. 3 are formed through protrudes through part of the casing. 5A shows that a part of the flat-type first heat dissipation substrate 62A protrudes through the lower part of the housing 69A, and a part of the flat-type second heat dissipation substrate 67A protrudes through the upper part of the housing 69A to achieve heat dissipation. 5B shows that the pins of the pin-type first heat dissipation substrate 62B protrude through the lower part of the housing 69B, and the pins of the pin-type second heat dissipation substrate 67B protrude through the upper part of the housing 69B, to achieve heat dissipation. 5C shows that the fins of the fin-shaped first heat dissipation substrate 62C protrude through the lower part of the housing 69C, and the fins of the fin-shaped second heat dissipation substrate 67C protrude through the upper part of the housing 69C to achieve heat dissipation. Although not shown, the first heat dissipation substrate and the second heat dissipation substrate may promote heat dissipation characteristics in different combinations. For example, each of the first heat dissipation substrate and the second heat dissipation substrate is any one of a plate type, a pin type, and a fin type, and the first heat dissipation substrate and the second heat dissipation substrate may be of different types. used.

当第一散热衬底和第二散热衬底的热导率高于壳体的热导率时，第一散热衬底的一部分和第二散热衬底的一部分被设置成向壳体的外部突出，从而通过外部空气提高热传导效率。When the thermal conductivity of the first heat dissipation substrate and the second heat dissipation substrate is higher than the thermal conductivity of the housing, a portion of the first heat dissipation substrate and a portion of the second heat dissipation substrate are disposed to protrude toward the outside of the housing. , thereby improving heat transfer efficiency through external air.

根据本发明的功率半导体模块，第一散热衬底被设置在下部位置，并且第二散热衬底被设置在上部位置，使得壳体内的功率半导体模块可以通过散热结构的二重化实现优异的散热性能。According to the power semiconductor module of the present invention, the first heat dissipation substrate is disposed in the lower position, and the second heat dissipation substrate is disposed in the upper position, so that the power semiconductor module in the housing can achieve excellent heat dissipation performance through duplication of the heat dissipation structure.

（第二实施例）(Second Embodiment)

图6示出了根据本发明的第二实施例的功率半导体模块。Figure 6 shows a power semiconductor module according to a second embodiment of the invention.

如图6所示，本发明的功率半导体模块400可以包括：基板的第一散热衬底41；具有多层结构的衬底42，该具有多层结构的衬底形成在第一散热衬底41上；半导体芯片43，该半导体芯片被布置在具有多层结构的衬底42上，并且通过键合到具有多层结构的衬底42上而以倒装芯片的形式形成；形成在半导体芯片42上的引线板44；形成在引线板44上的热界面材料层（TIM层）48；以及形成在TIM层48上的第二散热衬底47。As shown in FIG. 6 , the power semiconductor module 400 of the present invention may include: a first heat dissipation substrate 41 of a base plate; a substrate 42 with a multi-layer structure formed on the first heat dissipation substrate 41 on; a semiconductor chip 43 which is arranged on a substrate 42 having a multi-layer structure and is formed in a flip-chip form by bonding to the substrate 42 having a multi-layer structure; formed on the semiconductor chip 42 a lead plate 44 on the lead plate 44 ; a thermal interface material layer (TIM layer) 48 formed on the lead plate 44 ; and a second heat dissipation substrate 47 formed on the TIM layer 48 .

具有多层结构的衬底42可以是诸如金属-陶瓷衬底、陶瓷-金属衬底、金属-陶瓷-金属衬底等的多层衬底，并且优选地是直接键合铜（DBC）衬底，该直接键合铜衬底是铜（Cu）-陶瓷-铜（Cu）叠层。The substrate 42 having a multilayer structure may be a multilayer substrate such as a metal-ceramic substrate, a ceramic-metal substrate, a metal-ceramic-metal substrate, and the like, and is preferably a direct bonded copper (DBC) substrate , the direct bonded copper substrate is a copper (Cu)-ceramic-copper (Cu) stack.

具有多层结构的衬底42可以以整体的方式设置在第一散热衬底41上，或者具有多层结构的衬底42可以以经由键合层（例如焊接）键合到第一散热衬底41上的方式形成。在具有多层结构的衬底42以整体的方式设置在第一散热衬底41上的情况下，第一散热衬底41与具有多层结构的衬底42之间的焊料被移除，使散热性能得到改善。The substrate 42 having a multi-layer structure may be integrally disposed on the first heat dissipation substrate 41 , or the substrate 42 having a multi-layer structure may be bonded to the first heat dissipation substrate via a bonding layer (eg, soldering). 41 on the way to form. In the case where the substrate 42 having a multi-layer structure is integrally disposed on the first heat dissipation substrate 41 , the solder between the first heat dissipation substrate 41 and the substrate 42 having a multi-layer structure is removed, so that Thermal performance is improved.

本发明的半导体芯片43可以被布置在具有多层结构的衬底42上并且以倒装芯片的形式键合到具有多层结构的衬底42上。焊接可用于将半导体芯片43附接到衬底上。当将半导体芯片43附接到电路衬底时，使用半导体芯片43的底表面处的电极图案并使该电极图案按原样熔融，而无需使用诸如金属引线的附加连接结构或诸如球栅阵列的中间介质，从而形成倒装芯片的形式。如上文所述，由于不使用引线，本发明有利于小尺寸制造和减轻重量，并且还有利于散热特性，原因是电极之间的距离非常小。特别地，由于半导体芯片43具有倒装芯片的形式，因此通过双向散热改善了散热性能，并且降低了掺杂硅的热阻，从而改善了芯片接合部的接触散热。The semiconductor chip 43 of the present invention may be disposed on the substrate 42 having a multi-layer structure and bonded to the substrate 42 having a multi-layer structure in a flip-chip manner. Soldering may be used to attach the semiconductor chip 43 to the substrate. When the semiconductor chip 43 is attached to the circuit substrate, the electrode pattern at the bottom surface of the semiconductor chip 43 is used and the electrode pattern is melted as it is without using an additional connection structure such as a metal lead or an intermediate such as a ball grid array. dielectric, thus forming a flip-chip form. As mentioned above, since no wires are used, the present invention facilitates small size manufacturing and weight reduction, and also facilitates heat dissipation characteristics since the distance between electrodes is very small. In particular, since the semiconductor chip 43 has the form of a flip chip, the heat dissipation performance is improved through bidirectional heat dissipation, and the thermal resistance of the doped silicon is reduced, thereby improving the contact heat dissipation of the chip joint.

本发明的半导体芯片43可以是二极管、IGBT元件等。可以使用选自铜（Cu）、银（Ag）、铝（Al）、镍（Ni）、锡（Sn）和钼（Mo）中的两种或两种以上的合金或者任何一种来实现键合，但不限于此。The semiconductor chip 43 of the present invention may be a diode, an IGBT element, or the like. The bond may be realized using two or more alloys or any one selected from copper (Cu), silver (Ag), aluminum (Al), nickel (Ni), tin (Sn) and molybdenum (Mo). combination, but not limited to this.

本发明的TIM层48可以形成在引线板44上，并且引线板44可以形成在半导体芯片43上。TIM层48可以由选自氧化铝、氮化硅、氮化铝、氧化锌、二氧化钛、二氧化硅中的任何一种制成。替代地，可以通过使选自氧化铝、氮化硅、氮化铝、氧化锌、二氧化钛和二氧化硅中的任何一种以颗粒的形式分散在聚合物中来形成TIM层48。选自聚四氟乙烯（PTFE）、聚对苯二甲酸乙二酯（PET）、聚醚砜（PES）、聚酰亚胺（PI）、聚碳酸酯（PC）、聚氨酯（PU）、聚甲基丙烯酸甲酯（PMMA）和聚萘二甲酸乙二醇酯（PEN）中的任何一种可用作聚合物，但不限于此。如上文所述，将无机膜颗粒分散在聚合物中使用，从而产生弹性。The TIM layer 48 of the present invention may be formed on the lead plate 44 , and the lead plate 44 may be formed on the semiconductor chip 43 . The TIM layer 48 may be made of any one selected from the group consisting of aluminum oxide, silicon nitride, aluminum nitride, zinc oxide, titanium dioxide, and silicon dioxide. Alternatively, the TIM layer 48 may be formed by dispersing any one selected from the group consisting of aluminum oxide, silicon nitride, aluminum nitride, zinc oxide, titanium dioxide, and silicon dioxide in the form of particles in a polymer. Selected from polytetrafluoroethylene (PTFE), polyethylene terephthalate (PET), polyethersulfone (PES), polyimide (PI), polycarbonate (PC), polyurethane (PU), poly Any one of methyl methacrylate (PMMA) and polyethylene naphthalate (PEN) can be used as the polymer, but is not limited thereto. As mentioned above, inorganic film particles are used dispersed in polymers to create elasticity.

关于TIM层48，可以通过选自钎焊、氧化、电镀和粘贴中的任何一种方法在TIM层48的相对表面上形成铜层。此外，可以在TIM层48的上侧形成第一铜层，并且可以在TIM层48的下侧形成第二铜层。第二散热衬底47的下部部分可以以与TIM层48的上侧处的第一铜层接触的方式形成。Regarding the TIM layer 48, a copper layer may be formed on the opposite surface of the TIM layer 48 by any method selected from the group consisting of soldering, oxidation, electroplating, and pasting. Additionally, a first copper layer may be formed on the upper side of TIM layer 48 , and a second copper layer may be formed on the lower side of TIM layer 48 . The lower portion of the second heat dissipation substrate 47 may be formed in contact with the first copper layer at the upper side of the TIM layer 48 .

根据本发明的功率半导体模块在下部位置处设置有第一散热衬底41，并且在上部位置处设置有第二散热衬底47，从而通过散热结构的二重化促进了优异的散热性能。例如，通过第二散热衬底47从引线板44向上进行散热，并且通过第一散热衬底41从半导体芯片43向下进行散热。关于向下散热的性能，可以通过在基板的下方设置散热器来进行散热。The power semiconductor module according to the present invention is provided with the first heat dissipation substrate 41 at the lower position and the second heat dissipation substrate 47 at the upper position, thereby promoting excellent heat dissipation performance through duplication of the heat dissipation structure. For example, heat is dissipated upward from the lead plate 44 through the second heat dissipation substrate 47 , and heat is dissipated downward from the semiconductor chip 43 through the first heat dissipation substrate 41 . Regarding downward heat dissipation performance, heat dissipation can be achieved by placing a heat sink under the substrate.

本发明的引线板44可以被设置在半导体芯片43上。与使用导线相比，引线板44能够电连接半导体芯片43的元件以及高效地将从半导体芯片43产生的热量向上传输至第二散热衬底47。因此，半导体芯片43通过引线板44连接至第一散热衬底41而无需与导线键合，使得与由铝材料制成的导线相比，散热性能可以得到改善。选自铜（Cu）、银（Ag）和铝（Al）中的两种或两种以上的合金或任何一种可用作引线板44，但是就电特性和热传递而言，铜是最优选的。The lead plate 44 of the present invention may be provided on the semiconductor chip 43 . Compared with using wires, the lead plate 44 can electrically connect components of the semiconductor chip 43 and efficiently transmit heat generated from the semiconductor chip 43 upward to the second heat dissipation substrate 47 . Therefore, the semiconductor chip 43 is connected to the first heat dissipation substrate 41 through the lead plate 44 without bonding with wires, so that the heat dissipation performance can be improved compared to wires made of aluminum material. Two or more alloys or any one selected from copper (Cu), silver (Ag), and aluminum (Al) can be used as the lead plate 44, but copper is the best in terms of electrical characteristics and heat transfer. preferred.

本发明的壳体49可以以板的形式设置在第二散热衬底47上。The housing 49 of the present invention may be provided on the second heat dissipation substrate 47 in the form of a plate.

也就是说，如图6所示，可以形成第二散热衬底47，该第二散热衬底穿过壳体49的一部分突出。例如，尽管未示出，但是如在上述实施例中，用于覆盖功率半导体模块的板型壳体被设置在第二散热衬底47上，并且第二散热衬底47的上部部分可以形成为与壳体的下表面接触。替代地，如图6所示，用于覆盖功率半导体模块的板型壳体49可以被设置在第二散热衬底47上，并且第二散热衬底47的一部分可以形成为穿透壳体49。That is, as shown in FIG. 6 , a second heat dissipation substrate 47 protruding through a portion of the housing 49 may be formed. For example, although not shown, as in the above-described embodiment, a plate-shaped case for covering the power semiconductor module is provided on the second heat dissipation substrate 47, and the upper portion of the second heat dissipation substrate 47 may be formed as Contact with the lower surface of the housing. Alternatively, as shown in FIG. 6 , a plate-type case 49 for covering the power semiconductor module may be provided on the second heat dissipation substrate 47 , and a part of the second heat dissipation substrate 47 may be formed to penetrate the case 49 .

根据这种构型，当第二散热衬底47的热导率高于壳体49的热导率时，第二散热衬底47的一部分被设置成向壳体49的外部突出，从而通过外部空气提高热传导效率。According to this configuration, when the thermal conductivity of the second heat dissipation substrate 47 is higher than the thermal conductivity of the housing 49, a part of the second heat dissipation substrate 47 is provided to protrude to the outside of the housing 49, thereby passing through the outside Air improves heat transfer efficiency.

已经参照示出的附图描述了本发明，但是本发明不限于所描述的实施例，并且对于本领域技术人员显而易见的是，在不脱离本发明的精神和范围的情况下，可以进行各种变型和修改。因此，这样的修改和变型应当被理解为落入本发明的权利要求之内，并且应当基于所附的权利要求来解释本发明的范围。The present invention has been described with reference to the illustrated drawings, but the present invention is not limited to the described embodiments, and it is obvious to those skilled in the art that various modifications may be made without departing from the spirit and scope of the present invention. Variations and Modifications. Therefore, such modifications and variations should be understood as falling within the claims of the present invention, and the scope of the present invention should be interpreted based on the appended claims.

（对附图中的附图标记的描述）(Description of reference signs in drawings)

32、42、52A、52B、52C：第一散热衬底32, 42, 52A, 52B, 52C: first heat dissipation substrate

33、43：半导体芯片33, 43: Semiconductor chips

34、44：引线板34, 44: Lead board

35：PCB35: PCB

36：粘合剂层36: Adhesive layer

37、47、57A、57B、57C：第二散热衬底37, 47, 57A, 57B, 57C: Second heat dissipation substrate

34、48：TIM34, 48: TIM

39、49：壳体39, 49: Shell

Claims (11)

1.一种功率半导体模块，所述功率半导体模块包括：1. A power semiconductor module, said power semiconductor module comprising: 第一散热衬底；first heat dissipation substrate; 半导体芯片，所述半导体芯片被布置在所述第一散热衬底上，并且以倒装芯片的形式键合到所述第一散热衬底上；a semiconductor chip, the semiconductor chip being arranged on the first heat dissipation substrate and bonded to the first heat dissipation substrate in the form of a flip chip; 热界面材料层，所述热界面材料层被布置在所述半导体芯片上；以及a layer of thermal interface material disposed on the semiconductor chip; and PCB，所述PCB形成在所述热界面材料层上，A PCB formed on the thermal interface material layer, 其中，第二散热衬底的下部部分形成为穿透所述PCB并与所述热界面材料层接触，wherein a lower portion of the second heat dissipation substrate is formed to penetrate the PCB and contact the thermal interface material layer, 其中，在所述半导体芯片上设置引线板，并且设置粘合剂层以附接所述引线板和所述PCB，wherein a lead plate is provided on the semiconductor chip, and an adhesive layer is provided to attach the lead plate and the PCB, 其中，所述粘合剂层由各自具有1nm至50nm的直径的纳米颗粒组成，并且具有多孔结构。Wherein, the adhesive layer is composed of nanoparticles each having a diameter of 1 nm to 50 nm, and has a porous structure. 2.根据权利要求1所述的功率半导体模块，其中，第二散热衬底形成在PCB上，并且所述第二散热衬底是平板型、引脚型或鳍型的。2. The power semiconductor module according to claim 1, wherein the second heat dissipation substrate is formed on the PCB, and the second heat dissipation substrate is a flat plate type, a pin type, or a fin type. 3.根据权利要求1所述的功率半导体模块，其中，第一铜层形成在所述热界面材料层的上侧，第二铜层形成在所述热界面材料层的下侧，并且所述第二散热衬底的下部部分在所述热界面材料层的上侧处与所述第一铜层接触。3. The power semiconductor module according to claim 1, wherein a first copper layer is formed on an upper side of the thermal interface material layer, a second copper layer is formed on a lower side of the thermal interface material layer, and the A lower portion of the second heat dissipation substrate contacts the first copper layer at an upper side of the thermal interface material layer. 4.根据权利要求1所述的功率半导体模块，其中，所述热界面材料层由选自氧化铝、氮化硅、氮化铝、氧化锌、二氧化钛以及二氧化硅中的任何一种制成。4. The power semiconductor module according to claim 1, wherein the thermal interface material layer is made of any one selected from the group consisting of aluminum oxide, silicon nitride, aluminum nitride, zinc oxide, titanium dioxide, and silicon dioxide. . 5.根据权利要求1所述的功率半导体模块，其中，所述热界面材料层通过使选自氧化铝、氮化硅、氮化铝、氧化锌、二氧化钛和二氧化硅中的任何一种以颗粒的形式分散在聚合物中来形成。5. The power semiconductor module according to claim 1, wherein the thermal interface material layer is formed by using any one selected from the group consisting of aluminum oxide, silicon nitride, aluminum nitride, zinc oxide, titanium dioxide and silicon dioxide. The particles are dispersed in the polymer. 6.根据权利要求5所述的功率半导体模块，其中，所述聚合物是选自聚四氟乙烯、聚对苯二甲酸乙二酯、聚醚砜、聚酰亚胺、聚碳酸酯、聚氨酯、聚甲基丙烯酸甲酯以及聚萘二甲酸乙二醇酯中的任何一种。6. The power semiconductor module according to claim 5, wherein the polymer is selected from polytetrafluoroethylene, polyethylene terephthalate, polyethersulfone, polyimide, polycarbonate, polyurethane , any one of polymethyl methacrylate and polyethylene naphthalate. 7.根据权利要求1所述的功率半导体模块，其中，所述热界面材料层设置有通过选自钎焊、氧化、电镀和粘贴中的任何一种方法而形成在所述热界面材料层的相对表面上的铜层。7. The power semiconductor module according to claim 1, wherein the thermal interface material layer is provided with a thermal interface material layer formed by any one method selected from the group consisting of soldering, oxidation, electroplating and pasting. copper layer on the opposite surface. 8.根据权利要求1所述的功率半导体模块，其中，所述半导体芯片使用选自铜、银、铝、镍、锡和钼中的两种以上的合金或任何一种来进行键合。8. The power semiconductor module according to claim 1, wherein the semiconductor chip is bonded using two or more alloys or any one selected from the group consisting of copper, silver, aluminum, nickel, tin and molybdenum. 9.根据权利要求1所述的功率半导体模块，其中，所述半导体芯片包括绝缘栅双极型晶体管和二极管。9. The power semiconductor module of claim 1, wherein the semiconductor chip includes an insulated gate bipolar transistor and a diode. 10.根据权利要求2所述的功率半导体模块，其中，提供用于使所述功率半导体模块密闭的壳体，并且10. The power semiconductor module according to claim 2, wherein a housing for sealing the power semiconductor module is provided, and 所述第一散热衬底形成为与所述壳体的下部接触，并且所述第二散热衬底形成为与所述壳体的上部接触。The first heat dissipation substrate is formed in contact with the lower part of the housing, and the second heat dissipation substrate is formed in contact with the upper part of the housing. 11.根据权利要求2所述的功率半导体模块，其中，提供用于使所述功率半导体模块密闭的壳体，并且11. The power semiconductor module according to claim 2, wherein a housing for sealing the power semiconductor module is provided, and 在所述壳体的下部，所述第一散热衬底的一部分形成为穿透所述壳体并向外部突出，并且在所述壳体的上部，所述第二散热衬底的一部分形成为穿透所述壳体并向外部突出。At a lower portion of the housing, a portion of the first heat dissipation substrate is formed to penetrate the housing and protrude to the outside, and at an upper portion of the housing, a portion of the second heat dissipation substrate is formed to Penetrate the housing and protrude to the outside.
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