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CN111584350B - Filling method of SiC epitaxial trench and trench filling structure prepared by method - Google Patents

Filling method of SiC epitaxial trench and trench filling structure prepared by method Download PDF

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CN111584350B
CN111584350B CN202010450750.4A CN202010450750A CN111584350B CN 111584350 B CN111584350 B CN 111584350B CN 202010450750 A CN202010450750 A CN 202010450750A CN 111584350 B CN111584350 B CN 111584350B
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sic epitaxial
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epitaxial layer
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CN111584350A (en
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左万胜
钮应喜
乔庆楠
刘洋
刘锦锦
袁松
张晓洪
史田超
史文华
钟敏
胡新星
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Anhui Changfei Advanced Semiconductor Co ltd
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    • HELECTRICITY
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Abstract

The invention discloses a filling method of a SiC epitaxial groove and a groove filling structure prepared by the method, wherein after 4H-SiC grows in an epitaxial cavity, the growth condition is changed, a 3C-SiC epitaxial layer with the thickness of 100-200 nm continues to grow, and after the groove is completely etched, in the filling process of 4H-SiC in the groove, as the 3C-SiC epitaxial layer with the thickness of 100-200 nm exists at the top of a table board, the 3C-SiC continues to grow at the top of the table board; and 4H-SiC is grown in the groove. Due to the fact that the 3C-SiC and 4H-SiC stacking modes and the crystal structures are different in symmetry, the lattice constants and the tensions of the 3C-SiC and the 4H-SiC are different, after the grooves are filled, the 3C-SiC on the top of the table top is selectively etched in situ on line, the phenomenon that the epitaxial layer is damaged due to over grinding caused by the fact that CMP is used after the epitaxial channel is filled is avoided, meanwhile, device process steps are reduced, and cost is reduced.

Description

Filling method of SiC epitaxial trench and trench filling structure prepared by method
Technical Field
The invention relates to a filling method of a SiC epitaxial groove and a groove filling structure prepared by the method.
Background
With the development of energy conservation and emission reduction, new energy automobiles and smart grids, the requirements of the fields on the performance index and the reliability of the power semiconductor device are increasingly improved, and the device is required to have higher working voltage, higher current carrying capacity, higher working frequency, higher efficiency, higher working temperature, stronger heat dissipation capacity and higher reliability. After development for more than half a century, the performance of power semiconductor devices based on silicon materials has approached its physical limit, and further improvement of the performance of power electronic devices requires resorting to third generation semiconductor materials with superior overall performance. Therefore, the development of third generation semiconductor materials typified by SiC, GaN, and the like has been receiving attention.
As a typical representative third-generation wide bandgap semiconductor material, SiC has characteristics of wide bandgap, high critical breakdown field strength, high thermal conductivity, high carrier saturation rate, and the like.
A significant feature of SiC is that it has many allotropes (or allotropes), and the crystal structure of SiC can be divided into three major types according to symmetry: cubic, hexagonal, and rhombohedral. The crystal forms of 4H-SiC, 6H-SiC, 3C-SiC, 15R-SiC and the like are common ones in a plurality of homogeneous and heterogeneous crystal structures of SiC. Among the allotropic forms of SiC, 3C-SiC is the only semiconductor with a sphalerite structure, called β -SiC. And a homogeneous heteromorphic form having a hexagonal or rhombohedral structure, such as: 4H-SiC, 6H-SiC, 15R-SiC, referred to as α -SiC. Due to different stacking modes, different crystal structures and the like, the SiC allotrope isomers have certain differences in physical and chemical properties. For example, the lattice constant a of 4H-SiC is 3.073, and the lattice constant a of 3C-SiC is 4.34, the longer the bond length, the smaller the bonding force between bonding atoms, and the easier the cleavage; meanwhile, 3C-SiC is in a cubic crystal form, 4H-SiC is in a hexagonal crystal form, and the tension of the cubic crystal form is greater than that of the hexagonal crystal form, so that 3C-SiC is easier to etch than 4H-SiC. The etching reaction temperature range of the 4H-SiC is 1400-1600 ℃, and the etching temperature range of the 3C-SiC is about 1350 ℃.
One of the important directions in the advancement of optimization of SiC devices is to continuously decrease the specific on-resistance of the devices. The super junction technology is undoubtedly the most effective means to reduce the drift region specific on-resistance. The super junction technology is a technology which adopts an alternate P-type doped region structure and an N-type doped region structure to realize charge compensation and serve as a voltage-resistant layer so as to obtain low specific on-resistance and high voltage-resistant capability at the same time. Theoretically, it has been proved that the super junction device can convert Ron, sp ℃ - 2.3~2.5 Decrease to Ron, sp ^ BV 1.32
The method for obtaining the SiC super junction mainly adopts a groove etching-epitaxial backfilling technology at present, and the basic process flow is as follows: growing an N-type thick epitaxial layer on an N + type silicon substrate, etching a deep groove on the thick epitaxial layer, filling the groove with a P-type epitaxial layer, and flattening the surface by using a CMP (chemical mechanical polishing) method. The method has a large process difficulty, and particularly, how to ensure the filling quality of the trench and keep the filling time of the trench not to be too long is a main difficulty of the process for filling the trench by epitaxy of a deep trench.
Silicon carbide epitaxial fill typically uses a chlorine-containing silicon source gas and hydrogen halide gas mixture to grow inside the trench with a mask such as nickel, SiO, on the mesa top surface 2 Etc. so that it does not grow on top of the mesa. Because no SiC grows on the mask, the mask layer is easy to be over-ground to damage the epitaxial layer below because the normal deviation of a machine table cannot be ensured during the grinding of CMP. Therefore, there is a need to develop a maskless trench filling technique, which has a difficulty in controlling the growth rate of P-type epitaxy in the trench to be much higher than that of the mesa top, so as to avoid void defects when filling the trench, but this problem has not yet been solved.
Disclosure of Invention
In order to solve the technical problems, the invention provides a filling method of a SiC epitaxial trench and a trench filling structure prepared by the method. The method can avoid the damage to the epitaxial layer caused by the over grinding possibly generated by using CMP after the epitaxial channel is filled, and simultaneously, the method also reduces the device process steps and reduces the cost.
The technical scheme adopted by the invention is as follows:
a filling method of a SiC epitaxial trench comprises the following steps:
(1) sequentially growing a 4H-SiC buffer layer, a 4H-SiC epitaxial layer, a 3C-SiC nucleating layer and a 3C-SiC epitaxial layer on a 4H-SiC substrate;
(2) etching a groove downwards from the surface of the 3C-SiC epitaxial layer;
(3) filling a 4H-SiC epitaxial layer in the groove, and simultaneously continuously growing a 3C-SiC epitaxial layer on the 3C-SiC epitaxial layer;
(4) and after the grooves are filled, selectively etching away all the 3C-SiC epitaxial layer and the 3C-SiC nucleation layer in situ.
In the step (2), the etching depth of the groove is 5-30 μm, the inclination angle of the side wall of the groove is 86-90 degrees, and the upper width and the lower width are both 2-2.5 μm. In the SiC SJ-SBD device, the depth of a groove which is a key parameter of reverse withstand voltage capability of the device is determined, and a proper etching depth is selected according to the withstand voltage requirement of the device.
In the step (1), the growth conditions of the 3C-SiC epitaxial layer are as follows: introducing H into the epitaxial cavity 2 Growing a 3C-SiC epitaxial layer at 1400-1500 ℃ and 50-500 mbar of pressure by using a chlorine-containing silicon source gas, a carbon source and an Al dopant.
Said H 2 The flow rates of the chlorine-containing silicon source gas, the carbon source and the Al dopant are respectively 10-30 slm, 40-100 sccm and 20-50 sccm. The crystal quality of the obtained 3C-SiC epitaxial layer grown by the high doping of the Al dopant is poor, and the removal during subsequent in-situ etching is facilitated.
The thicknesses of the 4H-SiC buffer layer, the 4H-SiC epitaxial layer, the 3C-SiC nucleation layer and the 3C-SiC epitaxial layer are respectively 0.1-0.2 mu m, 5-30 mu m, 10-20 nm and 100-200 nm. In a SiC SJ-SBD device, the depth of a groove which is a key parameter for determining the reverse voltage endurance capability of the device is determined, so that the thicker a 4H-SiC epitaxial layer is, the deeper the groove is, and the stronger the voltage endurance capability is; the 3C-SiC nucleation layer provides nucleation points for growth of the 3C-SiC epitaxial layer, the 3C-SiC nucleation layer and the 3C-SiC epitaxial layer are too thick to facilitate subsequent in-situ etching, too thin to cover the top of the trench mesa, and during filling, the top of the mesa is not favorable for continuous growth of 4H-SiC.
The growth conditions of the 4H-SiC buffer layer are as follows: introducing H into the epitaxial cavity 2 A chlorine-containing silicon source gas, a carbon source and N 2 Growing the 4H-SiC buffer layer at 1600-1640 ℃ under 50-100mbar pressure. Said H 2 A chlorine-containing silicon source gas, a carbon source and N 2 The flow rates of the flow rate control agent are respectively 10-100 slm, 50-100 sccm and 10-20 sccm.
The growth conditions of the 4H-SiC epitaxial layer are as follows: introducing H into the epitaxial cavity 2 A chlorine-containing silicon source gas, a carbon source and N 2 And growing the 4H-SiC epitaxial layer at 1600-1700 ℃ and under 50-100mbar pressure. Said H 2 A chlorine-containing silicon source gas, a carbon source and N 2 The flow rates of the flow rate control agent are respectively 10-50 slm, 100-500 sccm and 80-150 sccm.
The growth conditions of the 3C-SiC nucleation layer are as follows: introducing H into the epitaxial cavity 2 And growing the 3C-SiC nucleation layer by using the chlorine-containing silicon source gas and the carbon source at the temperature of 1500-. Said H 2 The flow rates of the chlorine-containing silicon source gas and the carbon source are respectively 5-10 slm, 20-50 sccm and 20-50 sccm.
In the step (3), the process for filling the 4H-SiC epitaxial layer in the groove comprises the following steps: introducing H into the epitaxial cavity 2 And filling the 4H-SiC epitaxial layer into the groove at 1600-1700 ℃ and 400-600 mbar pressure until the groove is filled with the chlorine-containing silicon source gas, the carbon source, the HCl and the Al dopant.
Said H 2 The flow rates of the chlorine-containing silicon source gas, the carbon source, the HCl and the Al dopant are respectively 10-30 slm, 50-100 sccm, 1000-5000 sccm and 500-1000 sccm, and the Cl/Si ratio is controlled to be 20-50.
In the step (4), the in-situ etching conditions are as follows: continuing to introduce H into the epitaxial chamber 2 And (3) maintaining the flow rate in the same step (3) until all the 3C-SiC epitaxial layers and the 3C-SiC nucleation layers are completely etched.
Further, all the 3C-SiC epitaxial layer and the 3C-SiC nucleation layer can be completely etched by etching for 5-10 min at the pressure of 100-. Under such conditions, the mesa top 3C-SiC can be selectively etched without etching the 4H-SiC in the trench.
The chlorine-containing silicon source gas is SiCl 4 、SiHCl 3 、SiH 2 C1 2 Or SiH 3 Cl。
The invention also provides a groove filling structure prepared by the filling method of the SiC epitaxial groove.
According to the filling method of the SiC epitaxial groove, after 4H-SiC grows in the epitaxial furnace, the growth conditions are changed, the 3C-SiC epitaxial layer with the thickness of 100-200 nm continues to grow, in the groove filling process, the 3C-SiC epitaxial layer continues to grow on the top of the table top, and 4H-SiC grows in the groove.
Controlling H introduced into the epitaxial cavity when the groove is filled 2 The flow rates of the chlorine-containing silicon source gas, the carbon source, the HCl and the Al dopant are respectively 10-30 slm, 50-100 sccm, 1000-5000 sccm and 500-1000 sccm, and the groove is filled under the conditions of 1600-1700 ℃ and 400-600 mbar to control the length speed of 4H-SiC in the groove to be 5-8 mu m/H.
Filling the groove to control the growth of Cl/Si under the condition of 20-50, and controlling the growth speed of the 3C-SiC on the top of the table top to be lower than the growth speed in the groove so as to reduce the time for subsequent in-situ etching of the 3C-SiC;
controlling the pressure in the epitaxial cavity to be 400-600 mbar when filling the groove, and promoting the longitudinal growth speed to be higher than the transverse growth speed by high-pressure growth so as to avoid generating a cavity in the groove when filling the groove;
the length speed of 4H-SiC in the groove is controlled to be 5-8 mu m/H, the low growth rate is beneficial to improving the migration length of atoms, and cavities are prevented from being generated in the groove when the groove is filled;
and controlling the temperature in the epitaxial cavity to 1600-1700 ℃ when the groove is filled, and increasing the migration length of atoms by high-temperature growth so as to avoid generating cavities in the groove when the groove is filled.
Compared with the prior art, after 4H-SiC is grown in the epitaxial cavity, the growth conditions are changed, a 3C-SiC epitaxial layer with the thickness of 100-200 nm is continuously grown, and after the groove is completely etched, in the 4H-SiC filling process in the groove, as the 3C-SiC epitaxial layer with the thickness of 100-200 nm exists at the top of the table top, the 3C-SiC can be continuously grown at the top of the table top; and 4H-SiC is grown in the groove. Due to the fact that the 3C-SiC and 4H-SiC stacking modes and the crystal structures are different in symmetry, the lattice constants and the tensions of the 3C-SiC and the 4H-SiC are different, after the grooves are filled, the 3C-SiC on the top of the table top is selectively etched in situ on line, the phenomenon that the epitaxial layer is damaged due to over grinding caused by the fact that CMP is used after the epitaxial channel is filled is avoided, meanwhile, device process steps are reduced, and cost is reduced.
Drawings
Fig. 1 is a view showing a structure of an epitaxial trench obtained by the method for filling an epitaxial trench of SiC in example 1;
fig. 2 is a view showing an epitaxial trench structure obtained by the SiC epitaxial trench filling method in embodiment 2;
fig. 3 is a schematic view of a filling process of an SiC epitaxial trench in example 1;
fig. 4 is a schematic view of a filling process of the SiC epitaxial trench in example 2;
wherein, 1: substrate, 2: 4H — SiC buffer layer, 3: n-type 4H-SiC epitaxial layer, 4: 3C-SiC nucleation layer, 5: p-type 3C — SiC epitaxial layer, 6: groove, 7: and P type 4H-SiC epitaxial layer.
Detailed Description
The present invention will be described in detail with reference to examples.
And respectively carrying out half-trench filling and full-trench filling based on the requirement of device voltage resistance.
Example 1: filling of half-trenches
A filling method of a SiC epitaxial trench comprises the following steps:
1) etching the substrate on line: selection bias<11-20>Carrying out standard cleaning on a (0001)4H-SiC substrate with the direction of 4 degrees or 8 degrees; and placing the 4H-SiC substrate into the reaction chamber of the pumped SiC chemical vapor deposition equipment, and vacuumizing the reaction chamber. Introducing H at the flow rates of 10-100 slm and 5-10 slm respectively 2 And HCl at a pressure of 50-100mbar and a temperature of 1400 ℃ and 1500 ℃Etching for 5-30 min;
2) growing the 4H-SiC buffer layer: stopping introducing HCl, and introducing carrier gas H at the flow rates of 10-100 slm, 50-100 sccm and 10-20 sccm respectively 2 A chlorine-containing silicon source gas, a carbon source and N 2 Growing a 4H-SiC buffer layer with the thickness of 0.1-0.2 mu m at the temperature of 1600-1640 ℃ and the pressure of 50-100 mbar;
3) growing the N-type 4H-SiC epitaxial layer by introducing H at the flow rates of 10-50 slm, 100-500 sccm and 80-150 sccm respectively 2 A chlorine-containing silicon source gas, a carbon source and N 2 Growing an N-type 4H-SiC epitaxial layer with the thickness of 10-30 microns at 1600-1700 ℃ and 50-100mbar of dopant;
4)3C-SiC nucleation layer: shut down all sources and H 2 Cooling to 1500-1550 ℃, and introducing H at flow rates of 5-10 slm, 20-50 sccm and 20-50 sccm 2 Growing a 3C-SiC nucleation layer with the thickness of 10-20 nm under the pressure of 50-100mbar by using chlorine-containing silicon source gas and a carbon source;
4) p-type 3C-SiC epitaxial layer: shut down all sources and H 2 Cooling to 1400-1500 ℃, and introducing H at flow rates of 10-30 slm, 40-100 sccm, and 20-50 sccm 2 Growing a P-type 3C-SiC epitaxial layer with the thickness of 100-200 nm under the pressure of 50-500 mbar by using chlorine-containing silicon source gas, a carbon source and an Al source, wherein the doping concentration is 1 multiplied by 10 18 cm -3 ~1×10 19 cm -3
5) Cooling, taking out and cleaning;
6) etching the deep groove: etching a groove downwards from the surface of the P-type 3C-SiC epitaxial layer; making a pattern by photoetching, wherein a metal mask (Ni can be selected) is needed because the etching depth is deeper; performing ICP etching, wherein the etching depth is 5-8 microns, the inclination angle of the side wall of the groove is 86-90 degrees, the width of the bottom of the groove is consistent with the width of the top of the table top and is 2-2.5 microns, and removing the mask after etching;
7) cleaning again, drying, and feeding into an epitaxial furnace to fill a P-type SiC epitaxial layer in the groove: introducing H at a flow rate of 10-30 slm, 50-100 sccm, 1000-5000 sccm and 500-1000 sccm respectively 2 Chlorine-containing silicon source gas, carbon source, HCl and Al dopant, controlThe Cl/Si is 20-50, the filling rate is controlled to be 5-8 mu m/h, and the channel is filled at the temperature of 1600-1700 ℃ and the pressure of 400-600 mbar;
8) and (3) selectively etching the 3C-SiC in situ after filling the channel: closing the silicon source, HCl and Al, keeping the flow rates of the carrier gas hydrogen and the carbon source unchanged, and etching for 5-10 min at the pressure of 100-500mbar and the temperature of 1350-1400 ℃ until the 3C-SiC growing on the top of the mesa is completely etched.
Example 2: filling of full trenches
A filling method of a SiC epitaxial trench comprises the following steps:
1) etching the substrate on line: selection bias<11-20>Carrying out standard cleaning on a (0001)4H-SiC substrate with the direction of 4 degrees or 8 degrees; and placing the 4H-SiC substrate into the reaction chamber of the pumped SiC chemical vapor deposition equipment, and vacuumizing the reaction chamber. Introducing H at the flow rates of 10-100 slm and 5-10 slm respectively 2 And HCl, etching for 5-30 min under the pressure of 50-100mbar and the temperature of 1400-;
2) growing the 4H-SiC buffer layer: stopping introducing HCl, and introducing carrier gas H at the flow rates of 10-100 slm, 50-100 sccm and 10-20 sccm respectively 2 A chlorine-containing silicon source gas, a carbon source and N 2 Growing a 4H-SiC buffer layer with the thickness of 0.1-0.2 mu m at the temperature of 1600-1640 ℃ and the pressure of 50-100 mbar;
3) growing the N-type 4H-SiC epitaxial layer by introducing H at the flow rates of 10-50 slm, 100-500 sccm and 80-150 sccm respectively 2 A chlorine-containing silicon source gas, a carbon source and N 2 Growing an N-type 4H-SiC epitaxial layer with the thickness of 10-30 microns at 1600-1700 ℃ and 50-100mbar of dopant;
4)3C-SiC nucleation layer: shut off all sources and H 2 Cooling to 1500- 2 Growing a 3C-SiC nucleation layer with the thickness of 10-20 nm under the pressure of 50-100mbar by using chlorine-containing silicon source gas and a carbon source;
5) p-type 3C-SiC epitaxial layer: shut off all sources and H 2 Cooling to 1400 ℃ and 1500 ℃, and then using 10-30 slm, 40-100 sccm and 20-50 sccm respectivelyThe flow is introduced into H 2 Growing a P-type 3C-SiC epitaxial layer with the thickness of 100-200 nm under the pressure of 50-500 mbar by using chlorine-containing silicon source gas, a carbon source and an Al source, wherein the doping concentration is 1 multiplied by 10 18 cm -3 ~1×10 19 cm -3
6) Cooling, taking out and cleaning;
7) etching a deep groove: etching a groove downwards from the surface of the P-type 3C-SiC epitaxial layer; photoetching to form a pattern, wherein a metal mask (optional Ni) is needed due to the deep etching depth; performing ICP etching, wherein the etching depth is the thickness of the whole epitaxial layer, the inclination angle of the side wall of the groove is 86-90 degrees, the width of the bottom of the groove is consistent with the width of the top of the table top and is 2-2.5 mu m, and removing the mask after etching;
8) cleaning again, drying, and feeding into an epitaxial furnace to fill a P-type SiC epitaxial layer in the groove: introducing H at a flow rate of 10-30 slm, 50-100 sccm, 1000-5000 sccm and 500-1000 sccm respectively 2 The method comprises the following steps of (1) controlling Cl/Si to be 20-50, controlling the filling rate to be 5-8 mu m/h, and filling the trench at 1600-1700 ℃ and 400-600 mbar pressure by using a chlorine-containing silicon source gas, a carbon source, HCl and an Al dopant;
9) and (3) selectively etching the 3C-SiC in situ after filling the channel: and closing the silicon source, HCl and Al, keeping the flow rates of the carrier gas hydrogen and the carbon source unchanged, and etching for 5-10 min at the pressure of 100-.
The above detailed description of the filling method of SiC epitaxial trench and the trench filling structure prepared by the method with reference to the embodiments is illustrative and not restrictive, and several embodiments can be enumerated within the scope of the limitations, so that changes and modifications without departing from the general concept of the present invention shall fall within the protection scope of the present invention.

Claims (10)

1. A filling method of a SiC epitaxial trench is characterized by comprising the following steps:
(1) sequentially growing a 4H-SiC buffer layer, an N-type 4H-SiC epitaxial layer, a 3C-SiC nucleating layer and a P-type 3C-SiC epitaxial layer on a 4H-SiC substrate;
(2) etching a groove downwards from the surface of the P-type 3C-SiC epitaxial layer, and etching the groove into the N-type 4H-SiC epitaxial layer, or etching through the N-type 4H-SiC epitaxial layer to the surface of the 4H-SiC buffer layer;
(3) filling a P-type 4H-SiC epitaxial layer in the groove, and continuously growing a 3C-SiC epitaxial layer on the P-type 3C-SiC epitaxial layer;
(4) and after the grooves are filled, selectively etching away all the 3C-SiC epitaxial layer and the 3C-SiC nucleating layer in situ.
2. The filling method of the SiC epitaxial trench according to claim 1, wherein the etching depth of the trench is 5-30 μm, the inclination angle of the sidewall of the trench is 86-90 °, and the upper and lower widths are 2-2.5 μm.
3. The method for filling the SiC epitaxial trench according to claim 1 or 2, wherein in the step (1), the growth conditions of the P-type 3C-SiC epitaxial layer are as follows: introducing H into the epitaxial cavity 2 Growing a 3C-SiC epitaxial layer at 1400-1500 ℃ and 50-500 mbar of pressure by using a chlorine-containing silicon source gas, a carbon source and an Al dopant.
4. The method of filling a SiC epitaxial trench according to claim 3, characterized in that the H is 2 The flow rates of the chlorine-containing silicon source gas, the carbon source and the Al dopant are respectively 10-30 slm, 40-100 sccm and 20-50 sccm.
5. The filling method of the SiC epitaxial trench of claim 1 or 2, wherein the thicknesses of the 4H-SiC buffer layer, the N-type 4H-SiC epitaxial layer, the 3C-SiC nucleation layer and the P-type 3C-SiC epitaxial layer are 0.1-0.2 μm, 10-30 μm, 10-20 nm and 100-200 nm, respectively.
6. The filling method of the SiC epitaxial trench according to claim 1 or 2, wherein in the step (3), the process for filling the P-type 4H-SiC epitaxial layer in the trench is as follows: introducing H into the epitaxial cavity 2 A chlorine-containing silicon source gas, a carbon source, HCl andand filling the P-type 4H-SiC epitaxial layer into the groove by using the Al dopant at 1600-1700 ℃ under the pressure of 400-600 mbar until the groove is filled.
7. The method of filling an SiC epitaxial trench according to claim 6, characterized in that the H is 2 The flow rates of the chlorine-containing silicon source gas, the carbon source, the HCl and the Al dopant are respectively 10-30 slm, 50-100 sccm, 1000-5000 sccm and 500-1000 sccm, and Cl/Si = 20-50 is controlled.
8. The filling method of the SiC epitaxial trench of claim 1 or 2, wherein in the step (4), the in-situ etching conditions are as follows: continuing to introduce H into the epitaxial chamber 2 And (3) maintaining the flow rate in the same step (3) until all the 3C-SiC epitaxial layers and the 3C-SiC nucleation layers are completely etched.
9. The method for filling the SiC epitaxial trench as claimed in claim 8, wherein the etching is performed at a pressure of 500mbar and a temperature of 1350-.
10. A trench filling structure prepared by the method for filling a SiC epitaxial trench according to any one of claims 1 to 9.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030034304A (en) * 2001-10-22 2003-05-09 김형준 Deposition method and device of Sic thin films
CN101542739A (en) * 2006-11-21 2009-09-23 住友电气工业株式会社 Silicon carbide semiconductor device and process for producing the same
WO2017042963A1 (en) * 2015-09-11 2017-03-16 株式会社日立製作所 Semiconductor device, method for manufacturing same, power module, power conversion device, and rail vehicle
CN109727860A (en) * 2017-10-30 2019-05-07 全球能源互联网研究院 A method of preparing silicon carbide superjunction diode
KR20200020137A (en) * 2018-08-16 2020-02-26 포항공과대학교 산학협력단 MANUFACTURING METHOD FOR SiC MOSFET USING POWDER COLLISION AND SiC MOSFET MANUFACTURED U4 SING THE SAME

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101360070B1 (en) * 2012-12-27 2014-02-12 현대자동차 주식회사 Semiconductor device and method manufacturing the same
US10580878B1 (en) * 2018-08-20 2020-03-03 Infineon Technologies Ag SiC device with buried doped region

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030034304A (en) * 2001-10-22 2003-05-09 김형준 Deposition method and device of Sic thin films
CN101542739A (en) * 2006-11-21 2009-09-23 住友电气工业株式会社 Silicon carbide semiconductor device and process for producing the same
WO2017042963A1 (en) * 2015-09-11 2017-03-16 株式会社日立製作所 Semiconductor device, method for manufacturing same, power module, power conversion device, and rail vehicle
CN109727860A (en) * 2017-10-30 2019-05-07 全球能源互联网研究院 A method of preparing silicon carbide superjunction diode
WO2019086049A1 (en) * 2017-10-30 2019-05-09 全球能源互联网研究院有限公司 Method for preparing silicon carbide super-junction diode
KR20200020137A (en) * 2018-08-16 2020-02-26 포항공과대학교 산학협력단 MANUFACTURING METHOD FOR SiC MOSFET USING POWDER COLLISION AND SiC MOSFET MANUFACTURED U4 SING THE SAME

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