CN111564416B - Integrated circuit packaging structure adopting copper interconnection and manufacturing method thereof - Google Patents
Integrated circuit packaging structure adopting copper interconnection and manufacturing method thereof Download PDFInfo
- Publication number
- CN111564416B CN111564416B CN202010420839.6A CN202010420839A CN111564416B CN 111564416 B CN111564416 B CN 111564416B CN 202010420839 A CN202010420839 A CN 202010420839A CN 111564416 B CN111564416 B CN 111564416B
- Authority
- CN
- China
- Prior art keywords
- copper
- integrated circuit
- interconnection
- interconnect
- circuit chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 221
- 239000010949 copper Substances 0.000 title claims abstract description 221
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 221
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims description 24
- 239000004033 plastic Substances 0.000 claims description 21
- 239000011159 matrix material Substances 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 238000012858 packaging process Methods 0.000 abstract description 3
- 238000012545 processing Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 66
- 239000002609 medium Substances 0.000 description 12
- 238000010586 diagram Methods 0.000 description 10
- 238000005538 encapsulation Methods 0.000 description 9
- 238000004891 communication Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 238000009713 electroplating Methods 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 1
- 239000007640 basal medium Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000010297 mechanical methods and process Methods 0.000 description 1
- 230000005226 mechanical processes and functions Effects 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Wire Bonding (AREA)
Abstract
The application relates to the technical field of integrated circuit packaging, in particular to an integrated circuit packaging structure adopting copper interconnection and a manufacturing method thereof. The package structure includes: the wiring substrate is provided with a plurality of copper interconnection structures which are distributed at intervals; each copper interconnection structure comprises a leading-out end and a connecting end, wherein the leading-out ends are exposed out of the lower surface of the wiring substrate; and the integrated circuit chip is arranged in the wiring substrate, and the connecting end of the wiring substrate is connected with the IO end of the integrated circuit chip, so that an electric path is formed between the IO end and the leading-out end through the copper interconnection structure. The integrated circuit packaging structure adopting the copper interconnection and the manufacturing method thereof can solve the problems of scattered packaging industry chains, lower reliability and the like in the prior art and shorten the processing period of the whole packaging process.
Description
Technical Field
The application relates to the technical field of integrated circuit packaging, in particular to an integrated circuit packaging structure adopting copper interconnection and a manufacturing method of the integrated circuit packaging structure adopting copper interconnection.
Background
The plastic package of the integrated circuit can be divided into two main types according to the material characteristics of the chip carrier, wherein one type is frame type plastic package, and the plastic package comprises: transistor Outline (TO) packaging; a chip-on-Package (SOP), a Small Out-line transistor (SOT) Package, a Dual In-line Package (DIP), a quad flat Package (Quad Flat Package, QFP), etc., and another type is a substrate type Package including a Land Grid Array (LGA), a plastic ball Grid Array (Plastic Ball Grid Array Package, PBGA), etc.
In the related art, whether it is a frame type package or a substrate type package, the electrical interconnection between the chip and the carrier is realized by means of Wire Bond (W/B) or Flip Chip (FC), so that the packaging process is relatively complex and the production efficiency is relatively low.
Disclosure of Invention
The application provides an integrated circuit packaging structure adopting copper interconnection and a manufacturing method thereof, which can solve the problems of complex packaging process and low production efficiency in the prior art.
As a first aspect of the present application, there is provided an integrated circuit package structure employing copper interconnect, the package structure comprising:
the wiring substrate is provided with a plurality of copper interconnection structures which are distributed at intervals; each copper interconnection structure comprises a leading-out end and a connecting end, wherein the leading-out ends are exposed out of the lower surface of the wiring substrate;
and the integrated circuit chip is arranged in the wiring substrate, and the connecting end of the wiring substrate is connected with the IO end of the integrated circuit chip, so that an electric path is formed between the IO end and the leading-out end through the copper interconnection structure.
Optionally, the terminal is an interconnection pad, and the interconnection pad is exposed on the lower surface of the wiring substrate.
Optionally, each of the copper interconnect structures includes at least one interconnect copper pillar.
Optionally, the copper interconnection structure comprises a plurality of interconnection copper columns, and two adjacent interconnection copper columns are connected through an interconnection copper strip.
Optionally, the wiring substrate includes a plurality of interconnection layers sequentially stacked from bottom to top;
and a plurality of interconnection copper columns of the copper interconnection structure are arranged in the corresponding interconnection layers and are sequentially connected in a stacked manner from bottom to top.
Optionally, the connection end is a bridging copper strip, and the bridging copper strip is connected with the IO end of the integrated circuit chip.
As a second aspect of the present application, there is provided a method for manufacturing an integrated circuit package structure using copper interconnect, the method comprising the steps of:
providing a temporary carrier plate, and growing a metal seed layer on the temporary carrier plate;
forming a plurality of interval bottom copper interconnection structures on the metal seed layer, and plastic packaging the bottom copper interconnection structures through a matrix medium to form a basal layer;
determining an integrated circuit chip setting area, and manufacturing an upper copper interconnection structure on a bottom copper interconnection structure around the integrated circuit chip setting area so as to form an electric path between the upper copper interconnection structure and a corresponding bottom copper interconnection structure;
setting an integrated circuit chip on the integrated circuit chip setting area;
an electric path is formed between the lower IO end of the integrated circuit chip and a bottom copper interconnection structure positioned in the integrated circuit chip setting area; an electric path is formed between the upper IO end of the integrated circuit chip and the upper copper interconnection structure; the upper copper interconnection structure and the integrated circuit chip are subjected to plastic package through a matrix medium to form a packaging layer;
and stripping the temporary carrier plate.
Optionally, the forming a plurality of spacer underlying copper interconnect structures on the metal seed layer, and the step of molding the underlying copper interconnect structures through a matrix medium, the step of forming a base layer includes:
forming a plurality of leading-out ends of the bottom copper interconnection structures which are distributed at intervals on the metal seed layer;
manufacturing a bottom interconnection copper column on each leading-out end, so that the bottom interconnection copper column is electrically communicated with the corresponding leading-out end to form the bottom copper interconnection structure;
and plastic packaging the leading-out end and the bottom interconnection copper column through a matrix medium to form a substrate layer, wherein the leading-out end is exposed out of the lower surface of the substrate layer.
Optionally, the step of determining an integrated circuit chip disposition region, and fabricating an upper copper interconnect structure on a bottom copper interconnect structure located around the integrated circuit chip disposition region, such that an electrical path is formed between the upper copper interconnect structure and a corresponding bottom copper interconnect structure, includes:
determining an integrated circuit chip setting area;
and manufacturing an interconnection copper column of the upper copper interconnection structure on a bottom copper interconnection structure around the integrated circuit chip arrangement area, so that an electric path is formed between the interconnection copper column of the upper copper interconnection structure and the corresponding bottom copper interconnection structure.
Compared with the related art, the integrated circuit packaging structure adopting the copper interconnection and the manufacturing method thereof have the following advantages:
1. the application adopts the same structural materials, including epoxy resin and copper, at two stages of carrier manufacture and chip assembly, thereby improving the reliability of the integrated circuit.
2. Compared with the traditional packaging strip type carrier, the packaging carrier can be in a surface array (panel) or a wafer type, so that the packaging carrier has higher production efficiency in mass production.
3. Compared with the traditional packaged electric connection, the application is carried out one by one in a bonding mode and one by one in a flip-chip mode, and the application realizes the electric connection in an integral synchronous mode in an integral electroplating mode, thereby having higher reliability of an integrated circuit;
4. compared with the traditional packaging, the application receives the packaging completion from the chip, and the whole process is a one-stop process, so that two links of substrate processing and packaging in the traditional industry chain are fully integrated, and the development period of the product is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of an integrated circuit package structure employing copper interconnect according to an embodiment of the present application.
Fig. 2 is a schematic diagram of another integrated circuit package structure employing copper interconnect according to an embodiment of the present application.
Fig. 3 is a schematic structural diagram of a completed package method for manufacturing the package structure shown in fig. 2 according to an embodiment of the present application after step 101.
Fig. 4 is a schematic structural diagram of a completed package method for manufacturing the package structure shown in fig. 2 according to an embodiment of the present application after step 102.
Fig. 5 is a schematic structural diagram of a completed package method for manufacturing the package structure shown in fig. 2 according to an embodiment of the present application after step 105.
Fig. 6 is a schematic diagram of another integrated circuit package structure employing copper interconnect according to an embodiment of the present application.
Fig. 7 is a schematic structural diagram of a completed package method for manufacturing the package structure shown in fig. 6 according to an embodiment of the present application after step 203.
Fig. 8 is a schematic structural diagram of a completed package method for manufacturing the package structure shown in fig. 6 according to an embodiment of the present application.
Fig. 9 is a schematic structural diagram of a completed package method for manufacturing the package structure shown in fig. 6 according to an embodiment of the present application after step 208.
Fig. 10 is a schematic structural diagram of a completed package method for manufacturing the package structure shown in fig. 6 according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the application are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present application described below may be combined with each other as long as they do not collide with each other.
Referring to fig. 1, an embodiment of the present application provides an integrated circuit package structure using copper interconnection, the package structure includes: a wiring substrate 11 and an integrated circuit chip 12.
A plurality of copper interconnection structures 13 which are distributed at intervals are arranged in the wiring base layer 11; each copper interconnect structure 13 includes a terminal and a connection terminal 133, each terminal being exposed at the lower surface of the wiring substrate 11, and optionally, a solder ball 14 is provided on the exposed surface of each terminal.
The integrated circuit chip 12 is disposed in the wiring substrate 11, and the connection terminal 133 of the wiring substrate 11 is connected to the IO terminal of the integrated circuit chip 12, so that an electrical path is formed between the IO terminal and the lead-out terminal through the copper interconnection structure 13.
Referring to fig. 2, another integrated circuit package structure using copper interconnect is shown based on the package structure shown in fig. 1 according to an embodiment of the present application.
The wiring base layer comprises a base layer 111 and a packaging layer 112 which are sequentially stacked from bottom to top, the copper interconnection structure comprises a bottom copper interconnection structure 131 positioned in the base layer 111 and an upper copper interconnection structure 132 positioned in the packaging layer 112, and the corresponding bottom copper interconnection structure 131 and the upper copper interconnection structure 132 in one bottom copper interconnection structure are electrically communicated. The lower end of the underlying copper interconnect structure 131 is a lead-out end of the copper interconnect structure, which is exposed at the lower surface of the base layer 111,
the integrated circuit chip 12 is arranged in the encapsulation layer 112, and a lower IO end positioned on the lower surface of the integrated circuit chip 12 is electrically communicated with the bottom copper interconnection structure 131 positioned in the integrated circuit chip arrangement area 15; the upper IO side of the upper surface of the integrated circuit chip 12 is in electrical communication with the upper copper interconnect structure 132 around the integrated circuit chip placement area 15.
An embodiment of the present application provides a method for manufacturing an integrated circuit package structure for manufacturing a copper interconnect shown in fig. 2, the method at least comprising the steps of:
step 101: providing a temporary carrier plate, and growing and forming a metal seed layer on the temporary carrier plate.
Fig. 3 shows a temporary carrier plate 16 and a metal seed layer 17 formed on the temporary carrier plate 16. The temporary carrier plate 16 may be made of stainless steel or quartz; the metal seed layer 17 may be formed on the upper surface of the temporary carrier plate 16 by selective plating or sputtering, etc., for enabling the structure formed in the subsequent step to be well attached to the temporary carrier plate 16.
Step 102: and forming a plurality of interval bottom copper interconnection structures on the metal seed layer, and forming a basal layer by plastic packaging the bottom copper interconnection structures through a basal medium.
As shown in fig. 4, a plurality of bottom copper interconnect structures 131 are formed on the metal seed layer 17, and after plastic packaging, a base layer 111 is formed, wherein the lower end of the bottom copper interconnect structures 131 is a lead-out end of the copper interconnect structures, and the lead-out end is exposed on the lower surface of the base layer 111. The matrix medium used for forming the base layer 111 by plastic package may be epoxy resin.
Step 103: an integrated circuit chip arrangement region is determined, and an upper copper interconnect structure is fabricated on a bottom copper interconnect structure located around the integrated circuit chip arrangement region such that an electrical path is formed between the upper copper interconnect structure and a corresponding bottom copper interconnect structure.
Step 104: setting an integrated circuit chip on the integrated circuit chip setting area;
step 105: an electric path is formed between the lower IO end of the integrated circuit chip and a bottom copper interconnection structure positioned in the integrated circuit chip setting area; an electric path is formed between the upper IO end of the integrated circuit chip and the upper copper interconnection structure; the upper copper interconnection structure and the integrated circuit chip are subjected to plastic package through a matrix medium to form a packaging layer;
as shown in fig. 5, the integrated circuit chip 12 is disposed in the encapsulation layer 112, and the lower IO terminal on the lower surface of the integrated circuit chip 12 is in electrical communication with the underlying copper interconnect structure 131 in the integrated circuit chip placement area 15; the upper IO side of the upper surface of the integrated circuit chip 12 is in electrical communication with the upper copper interconnect structure 132 around the integrated circuit chip placement area 15. The matrix medium used for forming the encapsulation layer 112 by plastic encapsulation can be epoxy resin.
Step 106: and stripping the temporary carrier plate. The temporary carrier plate and the package body may be separated by heating, laser or mechanical process, so as to form an integrated circuit package structure using copper interconnection as shown in fig. 2, such that the lead-out terminal of the underlying copper interconnection structure 131 is exposed on the lower surface of the base layer 111, and solder balls are soldered on the lead-out terminal, where the solder balls are used to form pins of the package structure.
Referring to fig. 6, another integrated circuit package structure using copper interconnect is shown based on the package structure shown in fig. 2.
The base layer includes a first base layer 1111 and a second base layer 1112 stacked in this order from bottom to top, and the encapsulation layer includes a first encapsulation layer 1121 and a second encapsulation layer 1122 stacked in this order from bottom to top.
The underlying copper interconnect structure includes, in order from bottom to top, an interconnect pad 21, a first interconnect copper pillar 22, a first interconnect copper strap 23, and a second interconnect copper pillar 24 that are stacked in electrical communication, the first interconnect copper strap 23 electrically connecting the first interconnect copper pillar 22 and the second interconnect copper pillar 24 on the upper and lower sides thereof. The interconnect pad 21 and the first interconnect copper post 22 are molded in the first base layer 1111 and the first interconnect copper strap 23 and the second interconnect copper post 24 are molded in the second base layer 1112. The interconnect pad 21 is a lead-out terminal of the underlying copper interconnect structure, and is exposed on the lower surface of the first base layer 1111, the first interconnect copper pillar 22 is exposed on the upper surface of the first base layer 1111, the first interconnect copper strap 23 is exposed on the lower surface of the second base layer 1112 and contacts the first interconnect copper pillar 22, and the second interconnect copper pillar 24 is exposed on the upper surface of the second base layer 1112.
The integrated circuit chip 12 is arranged in the first packaging layer 1121, and the lower IO end of the integrated circuit chip 12 is electrically communicated with the second interconnection copper column 24 in the integrated circuit chip arrangement area 15 through the second interconnection copper strip 25; the second interconnect copper tape 25 is exposed at the lower surface of the first encapsulation layer 1121 and contacts the second interconnect copper pillar 24 located in the integrated circuit chip placement area 15.
On the second interconnect copper pillar 24 located around the integrated circuit chip placement area 15, a third interconnect copper tape 26, a bridge copper pillar 27, and a bridge copper tape 28 are sequentially stacked to form an electrical communication with each other, the third interconnect copper tape 26 and the bridge copper pillar 27 are molded in the first package layer 1121, and the bridge copper tape 28 is molded in the second package layer 1122. The third interconnect copper tape 26 is exposed on the lower surface of the first package layer 1121, and the third interconnect copper tape 26 electrically connects the second interconnect copper tape 25 located above and below the third interconnect copper tape 26 and the bridge copper pillar 27, the bridge copper pillar 27 is exposed on the upper surface of the first package layer 1121, the bridge copper tape 28 is exposed on the lower surface of the second package layer 1122, and the bridge copper tape 28 is used for electrically connecting the bridge copper pillar 27 and the upper IO terminal located on the upper surface of the integrated circuit chip 12.
The integrated circuit chip 12 is illustratively secured to the second base layer 1112 of the integrated circuit chip placement area 15 by a filler material 30.
An embodiment of the present application provides a method for manufacturing an integrated circuit package structure for manufacturing a copper interconnect shown in fig. 6, the method at least comprising the steps of:
step 201: providing a temporary carrier plate, and growing and forming a metal seed layer on the temporary carrier plate.
Step 202: and forming a plurality of interval interconnection bonding pads on the metal seed layer, correspondingly forming first interconnection copper columns on each interconnection bonding pad, and forming a first substrate layer by plastic packaging the interconnection bonding pads and the first interconnection copper columns through a matrix medium.
Step 203: correspondingly forming a first interconnection copper strip on the first interconnection copper column, and correspondingly forming a second interconnection copper column on the first interconnection copper strip, so that the first interconnection copper column and the second interconnection copper column which are positioned on the upper side and the lower side of the first interconnection copper column are electrically communicated; and molding the first interconnection copper strips and the second interconnection copper columns through a matrix medium to form a second substrate layer.
As shown in fig. 7, the base layer formed after the completion of step 203 includes a first base layer 1111 and a second base layer 1112 stacked in this order from bottom to top, the first base layer 1111 having the interconnect pad 21 and the first interconnect copper post 22 formed therein, and the second base layer 1112 having the first interconnect copper strap 23 and the second interconnect copper post 24 formed therein, the interconnect pad 21, the first interconnect copper post 22, the first interconnect copper strap 23, and the second interconnect copper post 24 being in electrical communication with each other.
Illustratively, the interconnect pad 21, the interconnect copper pillar 22, and the first interconnect copper tape 23 and the second interconnect copper pillar 24 may be sequentially stacked by sequentially performing photoresist coating, photolithography, electroplating, and photoresist stripping.
Step 204: and determining an integrated circuit chip setting area, manufacturing a third interconnection copper strip on the second interconnection copper column around the integrated circuit chip setting area, and manufacturing a bridging copper column on the third interconnection copper strip, so that the third interconnection copper strip electrically communicates the bridging copper columns above and below the third interconnection copper strip with the second interconnection copper column.
Alternatively, the third interconnection copper strip and the bridging copper column which are sequentially stacked can be sequentially manufactured through gluing, photoetching, electroplating and photoresist removal, and the second interconnection copper column, the third interconnection copper strip and the bridging copper column are sequentially contacted.
Step 205: and manufacturing a second interconnection copper strip on the second interconnection copper column of the integrated circuit chip arrangement area, and manufacturing the second interconnection copper strip.
As shown in fig. 8, the second interconnect copper tape 25 electrically communicates the second interconnect copper pillars 24 in the integrated circuit chip placement area 15, and the third interconnect copper tape 26 electrically communicates the bridge copper pillars 27 located thereabove and therebelow with the second interconnect copper pillars 24.
Step 206: arranging a chip mounting material on the second interconnection copper belt, and arranging an integrated circuit chip on the chip mounting material; the lower IO end of the integrated circuit chip is electrically communicated with the second interconnection copper strip.
Step 207: and forming a first packaging layer by plastic packaging the second interconnection copper strips, the third interconnection copper strips, the bridging copper columns and the integrated circuit chip through a matrix medium.
Step 208: opening holes on the upper IO end of the bridging copper column and the integrated circuit chip, so that the upper surface of the bridging copper column and the upper surface of the upper IO end are exposed; after step 208 is completed, the structure shown in fig. 9 is formed.
Optionally, the first encapsulation layer on the bridged copper pillars and the upper IO terminals is removed by laser drilling or milling.
Step 209: and a bridging copper strip is arranged between the upper IO end and the bridging copper column, so that two ends of the bridging copper strip are respectively contacted with the bridging copper strip and the bridging copper column. After step 209 is completed, the structure shown in fig. 10 is formed.
Step 210: and (5) plastic packaging the bridged copper column into a second packaging layer through a matrix medium.
Step 211: and stripping the temporary carrier plate. The separation of the temporary carrier plate from the package body may be achieved by a process such as heating, laser or mechanical, etc., so as to form an integrated circuit package structure using copper interconnection as shown in fig. 6, such that the interconnection pads 21 are exposed to the lower surface of the first base layer 1111, and the solder balls 14 are used to form pins of the package structure by soldering the solder balls 14 on the terminals.
The application and its embodiments have been described above without limitation, and the plastic package structure shown in the drawings is only one of the embodiments of the application, and includes not only a ball grid array plastic Package (PBGA) but also a flat no-lead package (QFN/DFN, LGA); not only is applicable to single IC package, but also is applicable to microsystem package of multiple ICs; not only for single-layer IC package, but also for stacked package of multi-layer IC
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the application.
Claims (7)
1. The method is used for manufacturing the integrated circuit packaging structure with copper interconnection, and comprises a wiring matrix, wherein a plurality of copper interconnection structures distributed at intervals are arranged in the wiring matrix; each copper interconnection structure comprises a leading-out end and a connecting end, wherein the leading-out ends are exposed out of the lower surface of the wiring substrate;
the integrated circuit chip is arranged in the wiring substrate, and the connecting end of the wiring substrate is connected with the IO end of the integrated circuit chip, so that an electric path is formed between the IO end and the leading-out end through the copper interconnection structure;
the method comprises the following steps:
providing a temporary carrier plate, and growing a metal seed layer on the temporary carrier plate;
forming a plurality of interval bottom copper interconnection structures on the metal seed layer, and plastic packaging the bottom copper interconnection structures through a matrix medium to form a basal layer;
determining an integrated circuit chip setting area, and manufacturing an upper copper interconnection structure on a bottom copper interconnection structure around the integrated circuit chip setting area so as to form an electric path between the upper copper interconnection structure and a corresponding bottom copper interconnection structure;
setting an integrated circuit chip on the integrated circuit chip setting area; an electric path is formed between the lower IO end of the integrated circuit chip and a bottom copper interconnection structure positioned in the integrated circuit chip setting area;
an electric path is formed between the upper IO end of the integrated circuit chip and the upper copper interconnection structure; the upper copper interconnection structure and the integrated circuit chip are subjected to plastic package through a matrix medium to form a packaging layer;
stripping the temporary carrier plate;
wherein, a plurality of interval bottom layer copper interconnection structures are formed on the metal seed layer, the bottom layer copper interconnection structures are encapsulated by matrix medium, and the step of forming a basal layer comprises the following steps:
forming a plurality of leading-out ends of the bottom copper interconnection structures which are distributed at intervals on the metal seed layer;
manufacturing a bottom interconnection copper column on each leading-out end, so that the bottom interconnection copper column is electrically communicated with the corresponding leading-out end to form the bottom copper interconnection structure;
and plastic packaging the leading-out end and the bottom interconnection copper column through a matrix medium to form a substrate layer, wherein the leading-out end is exposed out of the lower surface of the substrate layer.
2. The method of claim 1, wherein the terminals are interconnect pads exposed at a lower surface of the wiring substrate.
3. The method of claim 1, wherein each of the copper interconnect structures comprises at least one interconnect copper pillar.
4. The method of claim 3, wherein the copper interconnect structure comprises a plurality of interconnect copper pillars, adjacent two of the interconnect copper pillars being connected by an interconnect copper strap.
5. The method of claim 4, wherein the wiring substrate comprises a plurality of interconnect layers stacked in sequence from bottom to top; and a plurality of interconnection copper columns of the copper interconnection structure are arranged in the corresponding interconnection layers and are sequentially connected in a stacked manner from bottom to top.
6. The method of claim 1, wherein the connection terminal is a bridged copper strap, the bridged copper strap connecting to an IO terminal of the integrated circuit chip.
7. The method of claim 1, wherein the step of defining an integrated circuit die placement area, fabricating an upper copper interconnect structure on a lower copper interconnect structure located around the integrated circuit die placement area such that an electrical path is formed between the upper copper interconnect structure and a corresponding lower copper interconnect structure, comprises:
determining an integrated circuit chip setting area;
and manufacturing an interconnection copper column of the upper copper interconnection structure on a bottom copper interconnection structure around the integrated circuit chip arrangement area, so that an electric path is formed between the interconnection copper column of the upper copper interconnection structure and the corresponding bottom copper interconnection structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010420839.6A CN111564416B (en) | 2020-05-18 | 2020-05-18 | Integrated circuit packaging structure adopting copper interconnection and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010420839.6A CN111564416B (en) | 2020-05-18 | 2020-05-18 | Integrated circuit packaging structure adopting copper interconnection and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111564416A CN111564416A (en) | 2020-08-21 |
| CN111564416B true CN111564416B (en) | 2023-10-31 |
Family
ID=72073514
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010420839.6A Active CN111564416B (en) | 2020-05-18 | 2020-05-18 | Integrated circuit packaging structure adopting copper interconnection and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111564416B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN205248252U (en) * | 2015-12-23 | 2016-05-18 | 中国电子科技集团公司第十三研究所 | Gas tightness chip flip -chip installation is with ceramic pad array shell structure |
| CN109003959A (en) * | 2018-06-29 | 2018-12-14 | 华进半导体封装先导技术研发中心有限公司 | A kind of high thermal conductivity encapsulating structure that bonding wire is preforming and its manufacturing method |
| CN209374446U (en) * | 2018-12-26 | 2019-09-10 | 合肥矽迈微电子科技有限公司 | Multichip stacking encapsulation body |
-
2020
- 2020-05-18 CN CN202010420839.6A patent/CN111564416B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN205248252U (en) * | 2015-12-23 | 2016-05-18 | 中国电子科技集团公司第十三研究所 | Gas tightness chip flip -chip installation is with ceramic pad array shell structure |
| CN109003959A (en) * | 2018-06-29 | 2018-12-14 | 华进半导体封装先导技术研发中心有限公司 | A kind of high thermal conductivity encapsulating structure that bonding wire is preforming and its manufacturing method |
| CN209374446U (en) * | 2018-12-26 | 2019-09-10 | 合肥矽迈微电子科技有限公司 | Multichip stacking encapsulation body |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111564416A (en) | 2020-08-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10008438B2 (en) | Low profile leaded semiconductor package and method of fabricating the same | |
| US10861824B2 (en) | Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices | |
| US8278150B2 (en) | Stackable packages for three-dimensional packaging of semiconductor dice | |
| US8030741B2 (en) | Electronic device | |
| US7087461B2 (en) | Process and lead frame for making leadless semiconductor packages | |
| US7335532B2 (en) | Method of assembly for multi-flip chip on lead frame on overmolded IC package | |
| US8237250B2 (en) | Advanced quad flat non-leaded package structure and manufacturing method thereof | |
| CN103201836B (en) | There is the stackable molding microelectronics Packaging of face array element connector | |
| US6878570B2 (en) | Thin stacked package and manufacturing method thereof | |
| US7598599B2 (en) | Semiconductor package system with substrate having different bondable heights at lead finger tips | |
| US7927918B2 (en) | Packaged products, including stacked package modules, and methods of forming same | |
| US20090127682A1 (en) | Chip package structure and method of fabricating the same | |
| US20040080025A1 (en) | Lead frame, method of manufacturing the same, and semiconductor device manufactured with the same | |
| KR20140032923A (en) | Wireless module | |
| US6677219B2 (en) | Method of forming a ball grid array package | |
| KR100271676B1 (en) | Package and semiconductor device for semiconductor device and their manufacturing method | |
| US7262494B2 (en) | Three-dimensional package | |
| US20150084171A1 (en) | No-lead semiconductor package and method of manufacturing the same | |
| CN111564416B (en) | Integrated circuit packaging structure adopting copper interconnection and manufacturing method thereof | |
| CN101211794A (en) | Method for manufacturing a leadframe, packaging method for semiconductor element and semiconductor package product | |
| JP4030363B2 (en) | Semiconductor device | |
| US20120241954A1 (en) | Unpackaged and packaged IC stacked in a system-in-package module | |
| JPH05218295A (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |