CN111540753B

CN111540753B - 3D memory device and method of manufacturing the same

Info

Publication number: CN111540753B
Application number: CN202010418528.6A
Authority: CN
Inventors: 孙中旺; 张中; 周文犀
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2020-05-18
Filing date: 2020-05-18
Publication date: 2021-12-31
Anticipated expiration: 2040-05-18
Also published as: CN111540753A; CN114709219A

Abstract

Disclosed are a 3D memory device and a method of manufacturing the same, the device including: a substrate; the memory cell array is positioned on the substrate and comprises a gate stack structure and a plurality of channel columns penetrating through the gate stack structure, the gate stack structure comprises a plurality of gate conductor layers and a plurality of interlayer insulating layers which are alternately stacked, and the bottom ends of the channel columns are connected with the substrate; the word line conductive channels at least penetrate through part of the grid conductor layer and the interlayer insulating layer, and each word line conductive channel is electrically connected with the corresponding grid conductor layer. In the 3D memory device, the word line conductive channels are connected with the corresponding gate conductor layers in a hole contact mode, so that the stress on the word line conductive channels is reduced, and the positions of the word line conductive channels are not limited to the positions and the structures of the step areas.

Description

3D memory device and method of manufacturing the same

Technical Field

The invention relates to the technical field of memory devices, in particular to a 3D memory device and a manufacturing method thereof.

Background

The increase in memory density of memory devices is closely related to the progress of semiconductor manufacturing processes. As the feature size of semiconductor manufacturing processes becomes smaller, the storage density of memory devices becomes higher. In order to further increase the memory density, a memory device of a three-dimensional structure (i.e., a 3D memory device) has been developed. The 3D memory device includes a plurality of memory cells stacked in a vertical direction, can increase integration in multiples on a unit area of a wafer, and can reduce cost.

In the 3D memory device of the NAND structure, referring to fig. 1 and 2, a core region 10 and a step region 20 are divided. The core region 10 is used for forming a memory cell string, the stepped region 20 is used for forming a Word Line (WL), and as the number of memory cell layers of the 3D memory device is increased, the word line channel formed in the stepped region 20 is also subjected to greater stress and expansion, so that the word line conductive channel is prone to have problems, and the yield and reliability of the device are reduced.

Disclosure of Invention

In view of the foregoing problems, it is an object of the present invention to provide a 3D memory device and a method for fabricating the same, in which a word line conductive channel is formed at an end of an existing step instead of a hole contact method, so that not only is stress applied to the word line conductive channel reduced, but also the position of the word line conductive channel is not limited to the position and structure of the step region.

According to an aspect of the present invention, there is provided a 3D memory device including: a substrate; the memory cell array is positioned on the substrate and comprises a gate stack structure and a plurality of channel columns penetrating through the gate stack structure, the gate stack structure comprises a plurality of gate conductor layers and a plurality of interlayer insulating layers which are alternately stacked, and the bottom ends of the channel columns are connected with the substrate; the word line conductive channels at least penetrate through part of the grid conductor layer and the interlayer insulating layer, and each word line conductive channel is electrically connected with the corresponding grid conductor layer.

Preferably, between the side wall of the word line conductive channel and the gate stack structure, further includes: and the side wall of the word line conductive channel is isolated from the gate stack structure through the dielectric layer.

Preferably, the bottom of the word line conductive channel contacts the upper surface of the corresponding gate conductor layer.

Preferably, the bottom of the word line conductive channel is in contact with the inside of the corresponding gate conductor layer.

Preferably, the cross-sectional shapes of the word line conductive channel and the dielectric layer on the side wall of the word line conductive channel along the substrate surface direction include a circle, a rectangle, a triangle or a rounded rectangle.

Preferably, the maximum diameters of the dielectric layers on the side walls of the word line conductive channel and the word line conductive channel are smaller than the minimum diameter of the gate conductor layer.

Preferably, the plurality of word line conductive channels are respectively located in a core region and/or a step region of the gate stack structure.

Preferably, two of the word line conductive channels respectively electrically connected to any two adjacent gate conductor layers are respectively located in a core region and/or a step region of the gate stack structure.

According to another aspect of the present invention, there is provided a method of manufacturing a 3D memory device, including forming an insulating stack structure on a substrate, the insulating stack structure including a plurality of sacrificial layers and a plurality of interlayer insulating layers alternately stacked; forming a plurality of channel pillars through the insulating stack; forming a gate line gap extending from a surface of the insulating laminated structure to a vicinity of the substrate surface; replacing the plurality of sacrificial layers with a plurality of gate conductor layers through the gate line gaps to form a gate stack structure; a plurality of word line conductive channels are formed in the gate stack structure to reach the plurality of gate conductor layers, respectively, each word line conductive channel being electrically connected to a corresponding gate conductor layer, respectively.

Preferably, the step of forming a plurality of word line conductive paths in the gate stack structure to the plurality of gate conductor layers, respectively, comprises: forming a patterned mask layer on the surface of the gate stack structure, wherein the mask layer is provided with a plurality of grooves with different depths; forming a plurality of first channel holes respectively reaching the gate conductor layer in the gate stack structure through the mask layer; filling an insulating material in the plurality of first channel holes; respectively forming a plurality of second channel holes in one-to-one correspondence in the insulating materials of the plurality of first channel holes, wherein the diameter of each second channel hole is smaller than that of each first channel hole, the bottom of each second channel hole exposes corresponding gate conductor layers, and the insulating materials on the side walls of the second channel holes form dielectric layers; and forming a plurality of word line conductive channels in the second channel holes, wherein the side walls of the word line conductive channels are isolated from the gate stack structure through the dielectric layer.

According to the 3D memory device provided by the invention, the contact holes leading to the gate conductors are respectively formed in the edge area of the gate stack structure, and the word line conductive channels are formed in the contact holes, so that the problems of expansion and extrusion and large stress when the word line conductive channels are formed at the step end part of the step area are solved.

According to the 3D memory device provided by the invention, the word line conductive channels are in a hole contact mode, so that the positions of the word line conductive channels can be arranged at the edge parts of the gate stack structure, for example, the word line conductive channels can be arranged in a core region, the sequence of the word line conductive channels respectively leading to the gate conductors is not limited by the step shape, and the adjustment can be carried out according to the structure of the memory device.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1 illustrates a block diagram of a 3D memory device according to the related art;

FIG. 2 illustrates a partial view of a 3D memory device according to the prior art;

fig. 3a and 3b show an equivalent circuit diagram and a schematic structural diagram, respectively, of a memory cell string of a 3D memory device;

FIG. 4 is a schematic perspective view of a 3D memory device according to a first embodiment of the present invention;

fig. 5a and 5b illustrate a partially cutaway perspective view and a cross-sectional view, respectively, of a 3D memory device according to a first embodiment of the present invention;

fig. 6a to 6i are cross-sectional views illustrating stages of a method of fabricating a 3D memory device according to a first embodiment of the present invention;

fig. 7 illustrates a partially cut-away perspective view of a 3D memory device according to a second embodiment of the present invention.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.

The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.

It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.

If for the purpose of describing the situation directly above another layer, another area, the expression "directly above … …" or "above and adjacent to … …" will be used herein.

In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

In the present application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a memory device, including all layers or regions that have been formed. Hereinafter, unless otherwise specified, "semiconductor structure" refers to an intermediate structure comprising a wafer and a gate stack structure formed thereon.

In a 3D memory device of a NAND structure, gate conductors of a selection transistor and a memory transistor are provided in a stacked structure, and a memory cell string having a memory function is formed in a single channel formation (single channel formation) structure. In the related art, a 3D memory device includes a core region 10 and a step region 20, as shown in fig. 1, a memory cell string is located in the core region 10, and conductive paths of select lines and word lines are located in the step region.

In order to form a conductive path from the gate conductor to the select line and word line, a stepped structure needs to be formed at edge portions of the gate stack, i.e., edge portions of each gate conductor are exposed with respect to the overlying gate conductor to provide electrical connection regions, as shown in fig. 2.

Since the number of memory cell layers stacked in the vertical direction in the 3D memory device is increasing, the stress applied to the conductive channel in the step region is also increasing, and the probability of damage is also increasing, the inventors of the present application have noticed the above problem affecting the 3D memory device, and thus have proposed a further improved 3D memory device and a method for manufacturing the same.

The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.

Fig. 3a and 3b show a circuit diagram and a structure diagram, respectively, of a memory cell string of a 3D memory device. The case where the memory cell string includes 4 memory cells is shown in this embodiment. It is to be understood that the present invention is not limited thereto, and the number of memory cells in the memory cell string may be any number, for example, 32 or 64.

As shown in fig. 3a, the memory cell string 100 has a first terminal connected to the bit line BL and a second terminal connected to the source line SL. The memory cell string 100 includes a plurality of transistors connected in series between a first terminal and a second terminal, including: a first select transistor Q1, memory transistors M1-M3, and a second select transistor Q2. The gate of the first select transistor Q1 is connected to a string select line SSL, and the gate of the second select transistor Q2 is connected to a ground select line GSL. The gates of the memory transistors M1 through M3 are connected to corresponding ones of the word lines WL1 through WL3, respectively.

As shown in fig. 3b, the first and second select transistors Q1 and Q2 of the memory cell string 100 include

gate conductors

122 and 123, respectively, and the memory transistors M1 through M3 include gate conductors 121, respectively. The

gate conductors

121, 122, and 123 correspond to a stacking order of transistors in the memory cell string 100, and adjacent gate conductors are spaced apart from each other by an interlayer insulating layer, thereby forming a gate stack structure. Further, the memory cell string 100 includes a channel pillar 170. Channel pillars 170 extend through the gate stack structure. In the middle portion of the channel pillar 170, a tunnel dielectric layer 172, a charge storage layer 173, and a blocking dielectric layer 174 are interposed between the gate conductor 121 and the channel layer 171, thereby forming memory transistors M1 through M3. At both ends of the channel pillar 170, a blocking dielectric layer 174 is interposed between the

gate conductors

122 and 123 and the channel layer 171, thereby forming a first selection transistor Q1 and a second selection transistor Q2.

In this embodiment, the channel layer 171 is composed of, for example, doped polysilicon, the tunneling dielectric layer 172 and the blocking dielectric layer 174 are respectively composed of an oxide such as silicon oxide, the charge storage layer 173 is composed of an insulating layer containing quantum dots or nanocrystals such as silicon nitride containing particles of a metal or a semiconductor, and the

gate conductors

121, 122, and 123 are composed of a metal such as tungsten. The channel layer 171 serves to provide channel regions for controlling the selection transistor and the memory transistor, and the doping type of the channel layer 171 is the same as that of the selection transistor and the memory transistor. For example, for N-type select and memory transistors, the channel layer 171 may be N-type doped polysilicon.

In this embodiment, the core of the channel pillar 170 is an additional insulating layer, and the channel layer 171, the tunneling dielectric layer 172, the charge storage layer 173, and the blocking dielectric layer 174 form a stacked structure surrounding sidewalls of the core insulating layer. In an alternative embodiment, the core of channel pillar 170 is channel layer 171, and tunnel dielectric layer 172, charge storage layer 173, and blocking dielectric layer 174 form a stacked structure around the core.

In this embodiment, the first and second selection transistors Q1 and Q2, the memory transistors M1 to M3 use the common channel layer 171 and the blocking dielectric layer 174. In channel pillar 170, channel layer 171 provides source and drain regions and a channel layer for a plurality of transistors. In an alternative embodiment, the semiconductor layer and the blocking dielectric layer of the first and second selection transistors Q1 and Q2 and the semiconductor layer and the blocking dielectric layer of the memory transistors M1 to M3, respectively, may be formed in separate steps from each other.

In a write operation, the memory cell string 100 writes data to a selected one of the memory transistors M1 through M3 using FN tunneling efficiency. Taking the memory transistor M2 as an example, while the source line SL is grounded, the ground selection line GSL is biased to a voltage of about zero volts, so that the selection transistor Q2 corresponding to the ground selection line GSL is turned off, and the string selection line SSL is biased to a high voltage VDD, so that the selection transistor Q1 corresponding to the string selection line SSL is turned on. Further, BIT line BIT2 is grounded, word line WL2 is biased at the programming voltage VPG, e.g., around 20V, and the remaining word lines are biased at the low voltage VPS 1. Since only the word line voltage of the selected memory transistor M2 is higher than the tunneling voltage, electrons in the channel region of the memory transistor M2 reach the charge storage layer 173 through the tunneling dielectric layer 172, thereby converting data into charges stored in the charge storage layer 173 of the memory transistor M2.

In a read operation, the memory cell string 100 determines the amount of charge in the charge storage layer from the on-state of a selected one of the memory transistors M1 through M3, thereby obtaining data indicative of the amount of charge. Taking the memory transistor M2 as an example, the word line WL2 is biased at the read voltage VRD, and the remaining word lines are biased at the high voltage VPS 2. The on state of the memory transistor M2 is related to its threshold voltage, i.e., the amount of charge in the charge storage layer, so that a data value can be determined according to the on state of the memory transistor M2. The memory transistors M1 and M3 are always in a conductive state, and therefore, the conductive state of the memory cell string 100 depends on the conductive state of the memory transistor M2. The control circuit judges the conductive state of the memory transistor M2 based on the electric signals detected on the bit line BL and the source line SL, thereby obtaining the data stored in the memory transistor M2.

Fig. 4 illustrates a perspective view of a 3D memory device according to an embodiment of the present invention. For the sake of clarity, only the semiconductor structure and the conductive structure are illustrated in fig. 4, and an interlayer insulating layer for separating the semiconductor structure and the conductive structure from each other is not illustrated.

As shown in fig. 4, the 3D memory device 200 shown in this embodiment includes a substrate 101, a memory cell array on the substrate 101, a plurality of channel pillars 110 penetrating the memory cell array, and conductive paths of word lines and select lines connected to gate conductor layers, respectively.

The memory cell array includes 16 memory cell strings in total of 4 × 4, each memory cell string including 4 memory cells, thereby forming a memory array of 64 memory cells in total of 4 × 4. It is to be understood that the present invention is not limited thereto, and the 3D memory device may include any number of memory cell strings, for example, 1024, and the number of memory cells in each memory cell string may be any number, for example, 32 or 128.

The memory cell array includes a gate stack structure 120 on a substrate 101, a channel pillar 110 penetrating the gate stack structure 120, and an interconnect structure on the gate stack structure 120. The interconnect structure includes a plurality of conductive channels connecting the gate conductor with the source lines and bit lines, the source lines, the bit lines, and at least one insulating layer (not shown in FIG. 4). The gate stack structure 120 includes, for example,

gate conductors

121, 122, and 123. The plurality of gate conductors in the gate stack structure 120 form, for example, vias that respectively reach the gate conductors for providing space for conductive paths of the word lines and the select lines to extend to reach the corresponding gate conductors.

In the memory cell array, the memory cell strings respectively include respective channel pillars 110, and

common gate conductors

121, 122, and 123. The

gate conductors

121, 122 and 123 are in accordance with the stacking order of the transistors in the memory cell string 100 in fig. 3b, and adjacent gate conductors are separated from each other by an interlayer insulating layer, thereby forming a gate stack structure.

In this embodiment, the internal structure of the trench pillar 110 is shown in fig. 3b, and will not be described in detail. The channel pillars 110 penetrate the gate stack structure 120 and are arranged in an array. The semiconductor substrate 101 is located under the gate stack structure 120, wherein a common source region is formed in a first surface of the semiconductor substrate 101. First ends of the channel pillars 110 are commonly connected to a common source region through a channel region, and second ends of the channel pillars 110 are connected to respective bit lines BL via conductive vias. The gate stack structure 120 is divided into different gate lines by a gate line slit (gate line slit) 161.

The gate conductor 122 of the first selection transistor Q1 is divided into different gate lines by a gate line slit (gate line slit) 161. The gate lines of the plurality of channel pillars 110 of the same row are respectively connected to the corresponding string selection lines SGD via conductive vias 134.

The gate conductors 121 of the memory transistors M1-M4 are each connected to a corresponding word line WL. If the gate conductors 121 of the memory transistors M1 and M4 are divided into different gate lines by the gate line slit 161, the gate lines of the same layer are connected to the corresponding word lines WL via the conductive paths 131, respectively.

The gate conductors of the second select transistors Q2 are connected in one piece. If the gate conductor 123 of the second selection transistor Q2 is divided into different gate lines by the gate line slit 161, the gate lines are connected to the corresponding ground selection lines SGS via conductive paths, respectively.

In this embodiment, the conductive channel 131 of the word line WL of the 3D memory device reaches the corresponding gate conductor by means of a via contact, i.e., the conductive channel 131 passes through the gate conductor above the corresponding gate conductor, and the bottom portion is in contact with the upper surface of the corresponding gate conductor or the inside of the gate conductor. The maximum diameter of the contact hole is smaller than the minimum diameter of the gate conductor, the diameter of the contact hole is larger than the diameter of the conductive channel 131, and the conductive channel 131 is isolated from other gate conductors through which the conductive channel 131 passes in the gate stack structure by the dielectric layer.

Fig. 5a and 5b are a partially cutaway perspective view and a partially cutaway cross-sectional view, respectively, of a 3D memory device according to a first embodiment of the present invention, and fig. 5a and 5b are a partially cutaway perspective view and a partially cutaway cross-sectional view taken along line AA in fig. 4.

Referring to fig. 5a and 5b, in a region of the 3D memory device for forming a word line conductive path, a conductive path 131 penetrates a portion of the gate stack structure to be connected to a corresponding gate conductor, and a dielectric layer 107 is further formed between a sidewall of the conductive path 131 and the gate stack structure to insulate the conductive path 131 from the gate stack structure above the corresponding gate conductor layer.

The 3D memory device provided by the invention has the advantages that the contact holes leading to the gate conductors are respectively formed in the edge regions of the gate stack structure, the word line conductive channels 131 are formed in the contact holes, and the problems of expansion and extrusion and large stress when the word line conductive channels 131 are formed at the step ends of the step regions are reduced by means of contact through the holes.

According to the 3D memory device provided by the invention, the word line conductive channel 131 adopts a hole contact mode, so that the position of the word line conductive channel 131 can be arranged at no edge part of the gate stack structure, for example, the word line conductive channel can be arranged in a core region and/or a step region, the sequence of the word line conductive channels respectively leading to the gate conductor is not limited by the step shape, and the adjustment can be carried out according to the structure of the memory device.

Fig. 6a to 6i are cross-sectional views illustrating stages of a method of manufacturing a 3D memory device according to a first embodiment of the present invention, for example, a cross-sectional view taken along a direction indicated by an AA line in fig. 4 to obtain a 3D memory device. Not only the plurality of semiconductor and/or conductive structures but also an interlayer insulating layer that separates the plurality of semiconductor and/or conductive structures from each other is shown in the sectional view.

The method begins with a substrate 101, and a plurality of recess regions formed in the substrate 101. In this embodiment, the substrate 101 is, for example, a P-type single crystal silicon substrate, and the recess region is, for example, a channel region.

As shown in fig. 6a, an insulating stacked structure is formed on the surface of a substrate 101.

The insulating stack structure includes a plurality of sacrificial layers 102 stacked, with adjacent sacrificial layers 102 separated from each other by insulating layers 103. In this embodiment, the insulating layer 103 is composed of, for example, silicon oxide, and the sacrificial layer 102 is composed of, for example, silicon nitride.

As described below, sacrificial layer 102 is replaced with gate conductors 121-123, gate conductor 122 is connected to the string select line in one step, gate conductor 123 is connected to the ground select line in one step, and gate conductor 121 is connected to the word line in one step.

Further, a channel pillar 110 is formed in the insulating stack structure, as shown in fig. 6 b.

In this step, for example, a photoresist mask is formed on the surface of the semiconductor structure, and then anisotropic etching is performed to form a channel hole in the insulating stacked structure. The anisotropic etching may be dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation. For example, a selective etchant is used so that the etch reaches the surface of the semiconductor substrate. The photoresist mask is removed by dissolving or ashing in a solvent after etching.

Further, a channel pillar 110 is formed in the channel hole. The sidewalls of channel pillar 110 include a plurality of functional layers, such as a channel layer, a tunnel dielectric layer, a charge storage layer, and a blocking dielectric layer, which in this embodiment, sequentially surround the core, and the specific structure is shown in fig. 3 b.

In the final 3D memory device, the upper end of the channel pillar 110 will be connected to a bit line, thereby forming an effective memory cell. The channel pillar 110 has, for example, an ONOP (oxide-nitride-oxide-polysilicon) structure, i.e., the blocking dielectric layer, the charge storage layer, the tunneling dielectric layer, and the channel layer are respectively composed of an oxide, a nitride, an oxide, and a polysilicon.

In this embodiment, the channel pillar 110 further includes an insulating layer as a core, and the channel layer, the tunneling dielectric layer, the charge storage layer, and the blocking dielectric layer form a stacked-layer structure surrounding the core. In an alternative embodiment, the insulating layer may be omitted from the channel pillar 110.

Further, a gate line slit 161 (see fig. 4) is formed in the insulating stack structure, and the sacrificial layer 102 in the insulating stack structure is replaced with gate conductors 121 to 123 via the gate line slit 161 to form a gate stack structure, as shown in fig. 6 c.

In this step, a gate line slit 161 is formed in the insulating stack structure, the gate line slit 161 extending downward from the surface of the insulating stack to the surface of the substrate 101. In this step, a gate stack structure is formed using a plurality of interlayer insulating layers 103 as an etch stop layer, removing the sacrificial layer 102 by etching through the gate line slit 161 to form a cavity, and filling the cavity with a metal layer to form gate conductors 121 to 123, wherein the plurality of gate conductors 121 to 123 are sequentially stacked and separated from each other by the insulating layers 103.

In forming the gate line slit 161, anisotropic etching, for example, dry etching such as ion milling etching, plasma etching, reactive ion etching, or laser ablation may be used. For example, by controlling the etching time so that the etching is stopped near the surface of the semiconductor substrate 101. In this embodiment, the gate line slit 161 divides the gate conductors 121 to 123 into a plurality of gate lines. For this, the gate line slit 161 penetrates the insulating laminated structure.

In forming the cavity, the sacrificial layer 102 in the insulating stacked structure is removed by isotropic etching using the gate line slit 161 as an etchant channel to form the cavity. The isotropic etching may employ selective wet etching or vapor etching. An etching solution is used as an etchant in wet etching, wherein the semiconductor structure is immersed in the etching solution. Etching gases are used as etchants in vapor phase etching, wherein the semiconductor structure is exposed to the etching gas.

In the case where the insulating layer 103 and the sacrificial layer 102 in the insulating stacked structure are composed of silicon oxide and silicon nitride, respectively, a phosphoric acid solution may be used as an etchant in wet etching, and one or more of C4F8, C4F6, CH2F2, and O2 may be used in vapor etching. In the etching step, the gate line slit 206 is filled with an etchant. The end portion of the sacrificial layer 102 in the insulation stack structure is exposed in the opening of the gate line slit 161, and thus, the sacrificial layer 102 is contacted to the etchant. The etchant gradually etches the sacrificial layer 102 from the opening of the gate line slit 161 toward the inside of the insulating stacked structure. Due to the selectivity of the etchant, the etching removes the sacrificial layer 102 with respect to the insulating layer 103 in the insulating stack structure.

When the gate conductors 121 to 123 are formed, the gate line slit 161 is used as a deposition channel, and a metal layer is filled in the cavity by Atomic Layer Deposition (ALD), thereby forming a gate stack structure.

In this embodiment, the metal layer is composed of tungsten, for example. The precursor source used in atomic layer deposition is, for example, tungsten hexafluoride WF6, and the reducing gas used is, for example, silane SiH4 or diborane B2H 6. In the step of atomic layer deposition, the deposition process is realized by obtaining tungsten material by chemical adsorption of a reaction product of tungsten hexafluoride WF6 and silane SiH 4.

The gate line slit 161 is filled with an insulating material. In this step, an insulating material is deposited on the surface of the semiconductor structure by a deposition process, such as physical vapor deposition, chemical vapor deposition, or the like, the gate line slit 161 is filled with the insulating material, and the surface of the insulating layer is planarized by chemical mechanical polishing.

The insulating material for filling the gate line slit 161 is formed as a continuous layer with the insulating layer 103 for separating the gate conductor, and thus both are shown as an insulating layer as a whole. However, the present invention is not limited thereto, and a plurality of interlayer insulating layers between adjacent gate conductors and a filling material in the gate line slit 161 may be formed using a plurality of independent deposition steps.

Further, a patterned mask layer 104 is formed on the surface of the semiconductor structure, as shown in fig. 6 d.

In this step, a mask layer 104 is deposited on the surface of the semiconductor structure by a deposition process, such as physical vapor deposition, chemical vapor deposition, etc., and a plurality of trenches 105 are formed in the mask layer 104 by anisotropic etching, such as dry etching, e.g., ion milling etching, plasma etching, reactive ion etching, laser ablation, etc.

In this embodiment, the plurality of trenches 105 in the mask layer 104 are used to form via holes reaching the respective gate conductor layers in subsequent steps, and thus the plurality of trenches 105 are located at edge portions of the gate stack structure, and the height h of the plurality of trenches 105 is related to the distance d from the corresponding gate conductor in the gate stack to the surface of the gate stack and the etching ratio of the mask layer 104 to the gate stack structure. Specifically, the trench 105 reaching the lowermost gate conductor in fig. 6d is taken as an example. The distance between the upper surface of the gate conductor 123 closest to the substrate in the gate stack structure and the surface of the gate stack structure is d1, the height of the corresponding trench 105 in the mask layer 104 is h1, and when the etching ratio of the mask layer to the gate stack structure is 1: 1, then h 1: d1 is also 1: 1, when the etching ratio of the mask layer to the gate stack structure is greater than 1, then h 1: d1 is also greater than 1, and when the etching ratio of the mask layer to the gate stack structure is less than 1, then h 1: d1 is also less than 1, and the height of the mask layer 104 is not less than h 1. Accordingly, the height of the trench 105 at other positions and the distance from the corresponding gate conductor to the surface of the gate stack structure are also the same as the etching ratio of the mask layer to the gate stack structure.

Further, a plurality of first via holes 106 are formed in the gate stack structure through the mask layer 104, as shown in fig. 6 e.

In this embodiment, the plurality of first via holes 106 are formed in the gate stack structure using an anisotropic etch, for example, using a dry etch process such as ion mill etching, plasma etching, reactive ion etching, laser ablation, and the like.

In this embodiment, the bottoms of the plurality of first via holes 106 reach the surfaces of different gate conductor layers, respectively, and penetrate through the insulating layer and the gate conductor layer above the corresponding gate conductor layer.

Further, an insulating material is deposited on the surface of the semiconductor structure, as shown in fig. 6 f.

In this step, an insulating material is deposited on the surface of the semiconductor structure using a deposition process, such as physical vapor deposition, chemical vapor deposition, etc., and the insulating material fills the plurality of first via holes 106.

In this embodiment, the insulating material for filling the plurality of first via holes is formed as a continuous layer with the insulating layer 103 for separating the gate conductors, and both may be integrally shown as insulating layers. However, the present invention is not limited thereto, and a plurality of independent deposition steps may be employed to form a plurality of interlayer insulating layers between adjacent gate conductors and a filling material in the plurality of first via holes 106.

Further, a plurality of second via holes 108 and a dielectric layer 107 are formed at corresponding positions of the insulating material filling the plurality of first via holes 106, respectively, as shown in fig. 6 h.

In this step, for example, a photoresist mask is formed on the surface of the semiconductor structure, and then anisotropic etching is performed to form the second via hole 108 and the dielectric layer 107 in the insulating material of the first via hole 106. The anisotropic etching may be dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation. For example, a selective etchant is employed so that the etch reaches the surface of the corresponding gate conductor layer. The photoresist mask is removed by dissolving or ashing in a solvent after etching.

In this embodiment, the bottom of the second via hole 108 exposes the upper surface of the corresponding gate conductor layer or the inside of the corresponding gate conductor layer, and a dielectric layer 107 exists between the sidewall of the second via hole 108 and the gate stack structure, i.e., the diameter of the second via hole 108 is smaller than the diameter of the first via hole 106.

Further, the second via hole 108 is filled with a conductive material, and the surface of the semiconductor structure is planarized by chemical mechanical polishing, so as to form a word line conductive via 131, as shown in fig. 6 i.

In this step, a deposition process, such as physical vapor deposition, chemical vapor deposition, or the like, is used to deposit a conductive material on the surface of the semiconductor structure, wherein the conductive material fills the plurality of second via holes 108. Further, the surface of the semiconductor structure is planarized using chemical mechanical polishing, and the upper surface of the channel pillar 110 is exposed.

In this embodiment, the bottom of the word line conductive channel 131 is connected to the upper surface of the corresponding gate conductor, or the bottom of the word line conductive channel 131 is connected to the inside of the corresponding gate conductor.

Further, forming an interconnect structure (see fig. 4) over the semiconductor structure, the interconnect structure including a plurality of conductive channels connecting the gate conductor with the source and bit lines, and at least one insulating layer (not shown in fig. 4).

In the 3D memory device according to the first embodiment of the present application, the word line conductive channel reaches the gate conductor through the corresponding channel hole and is interconnected with the gate conductor, and the channel hole passes through the gate stack structure above the corresponding gate conductor layer.

Referring to fig. 7, in the process of forming the word line conductive channel 131, the depths of the contact holes 109 for contacting with the corresponding gate conductor layers are different, and the order of the contact holes 109 of different depths does not have to be arranged from low to high or from high to low, and can be adjusted according to actual conditions. The position of the contact hole 109 is not limited to the edge portion of the gate stack structure, and other positions of the gate stack structure where the word line conductive path 131 can be electrically connected to the corresponding gate conductor layer may be used.

The 3D memory device adopts the hole contact mode to form the word line conductive channel, and avoids the problem that the word line conductive channel is damaged due to the extrusion of the stress between the step region gate laminated structure and the insulating layer when a step structure is adopted.

Furthermore, the word line conductive channel is formed in a hole contact mode, the word line conductive channel can be located at any position of the gate stack structure, the sequence of the conductive channels leading to the corresponding gate conductor layer is not limited by the step structure, and the sequence can be interrupted according to actual conditions.

While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method of manufacturing a 3D memory device includes,

forming an insulating stack structure on a substrate, the insulating stack structure including a plurality of sacrificial layers and a plurality of interlayer insulating layers alternately stacked;

forming a plurality of channel pillars through the insulating stack;

forming a gate line gap extending from a surface of the insulating laminated structure to a vicinity of the substrate surface;

replacing the plurality of sacrificial layers with a plurality of gate conductor layers through the gate line gaps to form a gate stack structure;

forming a patterned mask layer on the surface of the gate stack structure, wherein the mask layer is provided with a plurality of grooves with different depths;

forming a plurality of word line conductive channels in the gate stack structure via the mask layer, each word line conductive channel being electrically connected to a corresponding gate conductor layer,

the depth of the groove in the mask layer is related to the distance between the corresponding grid conductor layer in the grid laminated structure and the surface of the grid laminated structure and the etching ratio of the mask layer to the grid laminated structure, and the bottoms of the word line conductive channels are in contact with the upper surface or the inner part of the corresponding grid conductor layer.

2. The method of manufacturing of claim 1, wherein forming a plurality of word line conductive vias in the gate stack structure comprises:

forming a plurality of first channel holes respectively reaching the gate conductor layer in the gate stack structure through the mask layer;

filling an insulating material in the plurality of first channel holes;

respectively forming a plurality of second channel holes in one-to-one correspondence in the insulating materials of the plurality of first channel holes, wherein the diameter of each second channel hole is smaller than that of each first channel hole, the bottom of each second channel hole exposes corresponding gate conductor layers, and the insulating materials on the side walls of the second channel holes form dielectric layers;

forming a plurality of word line conductive vias in the plurality of second via holes,

the side wall of the word line conductive channel is isolated from the gate stack structure through the dielectric layer.

3. The manufacturing method according to claim 1, wherein the plurality of word line conductive channels are respectively located in a core region and/or a step region of the gate stack structure.

4. The manufacturing method according to claim 1, wherein two of the word line conductive channels respectively electrically connected to any two adjacent gate conductor layers are respectively located in a core region and/or a step region of the gate stack structure.

5. A 3D memory device employing the manufacturing method of any one of claims 1-4, comprising:

a substrate;

the memory cell array is positioned on the substrate and comprises a gate stack structure and a plurality of channel columns penetrating through the gate stack structure, the gate stack structure comprises a plurality of gate conductors and a plurality of interlayer insulating layers which are alternately stacked, and the bottom ends of the channel columns are connected with the substrate;

a plurality of word line conductive vias extending through at least portions of the gate conductor layers and the interlayer insulating layer, each word line conductive via being electrically connected to a respective gate conductor layer,

the bottom parts of the plurality of word line conductive channels are in contact with the upper surface or the inner part of the corresponding grid conductor layer, and the arrangement sequence of the plurality of word line conductive channels is not related to the sequence of the corresponding grid conductor layer in the plurality of grid conductor layers.

6. The 3D memory device of claim 5, wherein between the sidewalls of the word line conductive vias and the gate stack structure further comprises: and the side wall of the word line conductive channel is isolated from the gate stack structure through the dielectric layer.

7. The 3D memory device of claim 6, wherein a cross-sectional shape of the dielectric layer of the wordline conductive channel and the wordline conductive channel sidewalls in a substrate surface direction includes a circle, a rectangle, a triangle, or a rounded rectangle.

8. The 3D memory device of claim 7, wherein the maximum diameter of the dielectric layer of the wordline conductive channel and the wordline conductive channel sidewalls are each less than the minimum diameter of the gate conductor layer.

9. The 3D memory device of claim 5, wherein the plurality of wordline conductive channels are located in a core region and/or a step region of the gate stack structure, respectively.

10. The 3D memory device of claim 5, wherein two of the wordline conductive vias electrically connected to any two adjacent gate conductor layers, respectively, are located in a core region and/or a step region of the gate stack structure, respectively.