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CN111512417A - Patterning a material film layer with a metal-containing topcoat to enhance sensitivity for extreme ultraviolet lithography (EUV) - Google Patents

Patterning a material film layer with a metal-containing topcoat to enhance sensitivity for extreme ultraviolet lithography (EUV) Download PDF

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Publication number
CN111512417A
CN111512417A CN201880081456.1A CN201880081456A CN111512417A CN 111512417 A CN111512417 A CN 111512417A CN 201880081456 A CN201880081456 A CN 201880081456A CN 111512417 A CN111512417 A CN 111512417A
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metal
layer
resist layer
resist
containing topcoat
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CN201880081456.1A
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CN111512417B (en
Inventor
E·A·德希尔瓦
D·戈德法布
N·费利克斯
D·科利斯
R·沃吉特基
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • G—PHYSICS
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    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/091—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers characterised by antireflection means or light filtering or absorbing means, e.g. anti-halation, contrast enhancement
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    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
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    • G03F7/094—Multilayer resist systems, e.g. planarising layers
    • G—PHYSICS
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    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2002—Exposure; Apparatus therefor with visible light or UV light, through an original having an opaque pattern on a transparent support, e.g. film printing, projection printing; by reflection of visible or UV light from an original such as a printed image
    • G03F7/2004—Exposure; Apparatus therefor with visible light or UV light, through an original having an opaque pattern on a transparent support, e.g. film printing, projection printing; by reflection of visible or UV light from an original such as a printed image characterised by the use of a particular light source, e.g. fluorescent lamps or deep UV light
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    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
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    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0335—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
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    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/0045—Photosensitive materials with organic non-macromolecular light-sensitive compounds not otherwise provided for, e.g. dissolution inhibitors
    • G—PHYSICS
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    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/092—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers characterised by backside coating or layers, by lubricating-slip layers or means, by oxygen barrier layers or by stripping-release layers or means
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    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/093—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers characterised by antistatic means, e.g. for charge depletion
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Abstract

The photoetching patterning method comprises the following steps: forming a multi-layer patterned material film stack on a semiconductor substrate, the patterned material film stack comprising a resist layer formed on one or more additional layers; and forming a metal-containing topcoat layer over the resist layer. The method further includes exposing the multilayer patterned material film stack to patterning radiation through the metal-containing topcoat to form a desired pattern in the resist layer, removing the metal-containing topcoat, developing the pattern formed in the resist layer, etching at least one underlying layer according to the developed pattern, and removing the remaining portions of the resist layer. The metal-containing topcoat layer may be formed, for example, by atomic layer deposition or spin-on deposition on the resist layer, or by self-detachment from the resist layer.

Description

Patterning a material film layer with a metal-containing topcoat to enhance sensitivity for extreme ultraviolet lithography (EUV)
Background
The present invention relates to the fabrication of semiconductor integrated circuits, and more particularly to the patterning of semiconductor integrated circuit features using a lithographic process.
As part of the ongoing efforts worldwide to shrink integrated circuit device dimensions, a variety of single-pattern and multi-pattern lithographic processes have been performed based on Deep Ultraviolet (DUV) radiation wavelengths such as 193nm (193nm), and although extending such arrangements further to feature patterning at production nodes below 10nm can be problematic, such approaches are still widely used. Recent developments in Extreme Ultraviolet (EUV) lithography processes using wavelengths such as 13.5nm are expected to facilitate accurate patterning of features at production nodes below 10nm, but significant difficulties remain in the practical implementation of EUV processes. For example, the output power of an EUV radiation source is limited, thus requiring a longer wafer exposure time. It would be highly desirable to provide a mechanism to mitigate this drawback.
Disclosure of Invention
Embodiments of the present invention provide a metal-containing topcoat for use with a patterned material film stack in an EUV lithography process. Such an arrangement may significantly increase the EUV sensitivity of the patterned material film stack, thereby reducing the required wafer exposure time and/or the power requirements of the EUV radiation source. This in turn can result in significant improvements in wafer productivity and corresponding reductions in integrated circuit manufacturing costs.
In one embodiment of the present invention, a lithographic patterning method includes forming a multi-layer patterned material film stack on a semiconductor substrate, the film stack including a resist layer formed on one or more additional layers, and forming a metal-containing topcoat layer on the resist layer. The method further includes exposing the film stack to patterning radiation through the topcoat layer to form a desired pattern in the resist layer, removing the topcoat layer, developing the pattern formed in the resist layer, etching at least one underlying layer according to the developed pattern, and removing the remaining portions of the resist layer. The topcoat layer may be formed, for example, by atomic layer deposition or spin-on deposition on the resist layer or by self-detachment from the resist layer.
In another embodiment of the present invention, a semiconductor structure comprises: a semiconductor substrate; and a multilayer patterned material film stack formed on the substrate, the film stack including a resist layer formed on one or more additional layers such as a hard mask layer and an organic planarization layer. The structure also includes a metal-containing topcoat layer formed over the resist layer. The top coat may include at least one of a transition metal and a post-transition metal, possibly in the form of one or more metal oxides. The top coat may also comprise one or more metalloids. The topcoat layer may be configured to be soluble in a developer solution or other fluid used to develop the pattern formed in the resist layer.
In another embodiment of the present invention, a metal-containing material is configured to form a metal-containing topcoat layer on a resist layer of a multi-layer patterned material film stack formed on a semiconductor substrate. The patterned material stack includes a resist layer and one or more additional layers on which the resist layer is formed. The metal-containing material is configured to form the topcoat layer by one of depositing on and self-detaching from the resist layer. The metal-containing material may include at least one of a transition metal and a post-transition metal, possibly in the form of one or more metal oxides. The metal-containing material may also comprise one or more metalloids. The metal-containing material includes a self-dissociating fluorine-functionalized metal additive configured to be included in a resist mixture used to form the resist layer.
Drawings
FIG. 1 illustrates a cross-sectional view of a semiconductor structure after an organic planarization layer is formed on a semiconductor substrate in an embodiment of the present invention;
FIG. 2 illustrates a cross-sectional view of the structure after a hard mask layer is formed on the planarization layer in an embodiment of the present invention;
FIG. 3 illustrates a cross-sectional view of the structure after a resist layer is formed on the hard mask layer in an embodiment of the present invention;
FIG. 4 illustrates a cross-sectional view of the structure after forming a metal-containing topcoat layer over the resist layer in an embodiment of the present invention;
FIG. 5 shows a cross-sectional view of a patterned EUV radiation exposed structure incorporating a resist layer through a topcoat in an embodiment of the present invention;
FIG. 6 shows a cross-sectional view of the structure after development of the pattern in the resist layer in an embodiment of the invention;
FIG. 7 illustrates a cross-sectional view of the structure after etching the hard mask layer according to the pattern formed in the resist layer in an embodiment of the present invention;
fig. 8 illustrates a cross-sectional view of the structure showing the etched hard mask layer after removal of the remaining portions of the resist layer in an embodiment of the present invention.
Detailed Description
Embodiments of the invention are described herein in the context of an EUV lithographic process and related patterned material film stacks and metal-containing topcoats. However, it should be understood that the application of the present invention is not limited to these arrangements, and the present invention is broadly applicable to a variety of different lithographic processes, film stacks, topcoats, and other features and functions. For example, other embodiments of the invention are not limited to use with any particular single-pattern or multi-pattern EUV lithography process, but may be applied to a variety of other types of lithography processes, including both single-pattern and multi-pattern DUV lithography processes. Also, in other embodiments of the invention, the particular arrangement of layers used within the film stack may be varied. Moreover, in other embodiments of the invention, the particular components of the topcoat layer and the manner in which it is formed may vary. These and many other variations in the disclosed arrangements will be apparent to those skilled in the art.
Embodiments of the present invention relate to forming a metal-containing topcoat layer on a resist layer of a multi-layer patterning material stack to increase the EUV sensitivity of the patterning material film stack in an EUV lithographic process. The topcoat layer may be formed by deposition on the resist layer, by self-separation from the resist layer, or using other techniques, including a combination of deposition and self-separation techniques. By providing increased EUV sensitivity in the film stack, embodiments of the invention may reduce the required wafer exposure time and/or power requirements of the EUV radiation source. This in turn can lead to significant improvements in wafer productivity and corresponding reductions in integrated circuit manufacturing costs.
Fig. 1-8 illustrate a portion of an EUV lithography process that includes forming a metal-containing topcoat layer on a resist layer of a patterned material film stack in an embodiment of the invention. EUV lithography processes are applied to semiconductor wafers in conjunction with integrated circuit fabrication. The figures show various cross-sectional views of a portion of a wafer as it undergoes sequential processing operations as part of an EUV lithographic process. It will be appreciated that various elements and other features shown in the figures are simplified for clarity and simplicity of illustration and have not necessarily been drawn to scale.
It should also be noted that references herein to the formation of a layer or structure "on" or "over" another layer or structure are intended to be interpreted broadly, and should not be interpreted as excluding the presence of one or more intervening layers or structures.
Referring first to FIG. 1, a semiconductor structure 100 represents a portion of a semiconductor wafer having a semiconductor substrate 102. at least a portion of the substrate 102 may be formed of silicon (Si) and may have a thickness of about 500 to 1000 micrometers (μm.) the substrate 102 itself may include multiple layers, although it is shown as a single layer in the figures, again stated for clarity and simplicity of illustration. the semiconductor structure 100 also includes an organic planarization layer (OP L) 104. OP L may be formed to a thickness of about 60nm, although this and other dimensions are shown here as illustrative examples and should not be construed as limiting. OP L104 may be the lowest layer referred to herein as a "multilayer patterned material film stack", although such a stack need not include OP L in other embodiments of the invention.
As shown in fig. 2, the hard mask layer 106 is formed on OP L, resulting in a structure 200. the hard mask layer 106 may be formed from a silicon-based material, such as silicon oxide, silicon nitride, or silicon oxynitride, although a variety of other inorganic or organic materials may be used.
Turning now to fig. 3, a resist layer 108 is formed on the hard mask layer 106, resulting in a structure 300. the structure 300 comprises a multilayer patterned material film stack 110 comprising OP L104, the hard mask layer 106, and a resist layer 108. the resist layer comprises a photosensitive material suitable for patterning using an EUV radiation source and a corresponding photomask.
In other embodiments of the present invention, stack 110 may include additional or alternative layers below resist layer 108 accordingly, the particular stack 110 shown in the figures is presented by way of illustrative example only.
As shown in FIG. 4, a metal-containing topcoat layer 112 is formed over resist layer 108 of stack 110, resulting in structure 400. A deposition process (e.g., as an atomic layer deposition (A L D) process or a spin deposition process) may be used to form a topcoat layer over the resist layer the topcoat layer 112 is illustratively formed as a relatively thin layer to avoid any risk of pattern collapse due to high aspect ratios.
For example, the A L D process may be used to deposit a topcoat to a thickness of about 2nm to 5 nm.such A L D process may utilize low temperature deposition conditions, which may involve utilizing a deposition temperature that is less than the temperature of a post-application bake (PAB) process applied to the resist layer 108. for example, the temperature of the PAB process for the resist layer 108 may be 150 deg.C, where the deposition temperature used to form the metal-containing topcoat 112 in the A L D process will be substantially less than 150 deg.C. for example, a low temperature deposition of 50 deg.C may be used.
As used herein, the term "metal-containing topcoat layer" is intended to be broadly interpreted as encompassing various coatings or other types of layers or arrangements of layers that may be formed on a resist layer as part of a lithographic patterning process.
As described above, the topcoat layer 112 may also be formed using a spin-on deposition process. For example, the topcoat layer 112 may be formed using a spin-on deposition process after applying the PAB process to the resist layer 108 as a spin-on layer of metal oxide nanoparticles.
The topcoat layer 112 may be formed using processes similar to those used to form bottom anti-reflective coatings (BARCs) in EUV lithography. Such BARC processes are typically used to form thin film coatings with high uniformity. Other examples of deposition processes that may be used to form topcoat layer 112 include Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD).
Techniques other than deposition may be used to form the topcoat layer 112. For example, the topcoat layer 112 in the structure 400 of FIG. 4 may be formed on the resist layer 108 using a self-separation process from the resist layer 108. In this type of arrangement, the self-separating material is provided in a resist mixture used to form the resist layer 108, which is used to form the resist layer 108, and then the resist layer 108 is subjected to a specified process to self-separate the self-separating material from the resist layer to form the topcoat layer 112. For example, the self-separating material may include a fluorine-functionalized metal additive. The designated process of self-separating the self-separating material from the resist layer 108 to form the topcoat layer 112 illustratively includes a PAB process.
A self-separating material incorporated into a resist mixture to form the topcoat layer 112 by self-separation is considered an example embodiment of the present invention, and a resist mixture containing such a self-separating material is also considered an example embodiment of the present invention.
Examples of self-separating materials that can be used to form the top coat layer by self-separation include additive materials with fluoroalcohol functionalization that can be incorporated into resist mixtures, as well as polymers based on metal pendant groups or metal backbones.
The topcoat 112 may include a metal composition including at least one of a transition metal and a post-transition metal. For example, the topcoat layer may include at least one transition metal, such as at least one of (Hf), zirconium (Zr), tantalum (Ta), tungsten (W), chromium (Cr), cobalt (Co), iron (Fe), and platinum (Pt). Additionally or alternatively, the topcoat layer 112 may include at least one post-transition metal, such as tin (Sn). The topcoat layer 112 may also incorporate at least one metalloid, such as antimony (Sb).
The above-mentioned metals and metalloids are examples of what are generally referred to herein as "high Z" atoms, where Z represents the atomic number of an atom, and alternatively, in other embodiments, high Z atoms may be used for the metal-containing topcoat 112.
The metal composition for the top coat may be in the form of a metal oxide at a concentration of less than about 30% of the top coat 112. For example, the top coating 112 may be formed by low temperature deposition of tin oxide (SnOx) at 50 ℃. In the context herein and other similar contexts, concentration percentage amounts refer to mole percent (mol%).
Examples of compositions that may be used to form the topcoat layer 112 by self-detachment from the resist layer 108 include copolymers with Hexafluoroacetone (HFA), and tin (Sn) -containing or other types of metal-containing monomeric units.
As a more specific example, a copolymer having an HFA suitable for use in forming the metal-containing topcoat layer 112 has the formula wherein R represents hydrogen (H) or a methyl or alkyl group:
Figure BDA0002543133290000051
in the above example, X represents the number of units. For typical polymer to metal unit combinations, HFAs and possibly one or more other units, the percentage of HFAs will be about 5% to 15% to support self-separation of the topcoat layer 112 from the resist layer 108, the percentage again referring to the mole percent (mol%).
As another example, a tin (Sn) containing monomer unit suitable for forming topcoat layer 112 has the following formula:
Figure BDA0002543133290000061
in this example, n represents the number of units present and R represents an alkyl group.
Again, the above material formulations are merely examples, and a variety of other materials having different chemical compositions may be used in forming topcoat layer 112, including other copolymers with HFAs, other metal-containing monomeric units, and other types of compositions.
Topcoat layer 112 may be configured to increase EUV sensitivity of stack 110 by increasing the generation of secondary electrons in resist layer 108. In such examples, topcoat layer 112 enhances the ability of resist layer 108 to absorb EUV radiation by allowing it to capture more EUV photons during exposure.
For example, the resist material of the resist layer 108 may experience enhanced sensitivity through selective permeation and subsequent reaction to the components of the topcoat layer 112. As a more specific example, in the case of depositing the SnOx topcoat layer described above, the SnOx particles may penetrate into the resist layer 108 or become part of the resist layer 108.
These and other embodiments of the present invention including a metal-containing topcoat layer can significantly improve EUV sensitivity without sacrificing patterned feature resolution or adversely affecting patterning quality metrics such as line edge roughness (L ER) and line width roughness (L WR).
Referring now to FIG. 5, stack 110 is exposed to EUV patterning radiation through top coat layer 112 to form a desired pattern in resist layer 108. The resulting structure 500 includes a patterned resist layer, represented in the figure by reference numeral 108'.
The topcoat layer 112 is then removed and the patterned resist layer 108' is developed, resulting in the structure 600 shown in FIG. 6. For example, the topcoat layer 112 may be removed by stripping, after which the patterned resist layer is developed 108' using a developer solution. Development of the patterned resist layer 108 'results in a developed resist layer 108' in which a portion of the resist layer is removed according to a pattern.
Alternatively, the topcoat layer 112 may be made of a material that is soluble in a developer solution used to develop the pattern formed in the resist layer 108'. For example, topcoat layer 112 may be configured to be soluble in the base and/or water during resist development. In this type of arrangement, the topcoat layer 112 is removed as part of the process of developing the pattern formed in the resist layer 108'. Again, development of the patterned resist layer 108' results in a developed resist layer 108 "in which a portion of the resist layer is removed according to a pattern.
Thus, the exposed topcoat layer 112 may be stripped in a separate step or, if configured to have an inherent solubility function, may be removed as part of the resist development process.
As shown in fig. 7, the hard mask layer 106 underlying the developed resist layer 108 "is etched according to the developed pattern to produce a structure 700. This portion of the process results in the pattern being transferred from the developed resist layer 108 "to the patterned hard mask layer 106' as shown. The etching may be performed using a process such as Reactive Ion Etching (RIE) or wet etching.
The remaining portions of the developed resist layer 108 "are then removed, as shown in FIG. 8, resulting in a structure 800. Additional processing operations, well known to those skilled in the art, are then performed on the structure 800 in order to form the desired integrated circuit structure on the semiconductor wafer. For example, a portion of the process as previously described in connection with fig. 1-8 may be repeated using a different pattern mask to further configure the hard mask layer according to additional pattern features.
In other embodiments of the invention, other types of multi-layer patterned material film stacks may be used. For example, in some embodiments of the present invention, the hard mask layer is omitted and one or more layers of the substrate 102 are etched according to the pattern of the developed resist layer 108 ". These and many other lithographic patterning arrangements using a metal-containing topcoat layer formed over a resist layer can be achieved using the techniques disclosed herein, as will be understood by those skilled in the art.
Embodiments of the invention may include a semiconductor structure comprising a semiconductor substrate and a multilayer stack of patterned material films formed on the substrate, wherein the stack comprises a resist layer formed on one or more additional layers, such as a hard mask layer and an organic planarization layer. The structure also includes a metal-containing topcoat layer formed over the resist layer. The top coat may include at least one of a transition metal and a post-transition metal, possibly in the form of one or more metal oxides. The top coat may also comprise one or more metalloids. The topcoat layer may be configured so that it is soluble in a developer solution used to develop the pattern formed in the resist layer.
Other embodiments of the invention may include a metal-containing material configured to form a metal-containing topcoat layer on a resist layer of a multi-layer patterned material film stack formed on a semiconductor substrate. The stack includes a resist layer and one or more additional layers on which the resist layer is formed. The metal-containing material is configured to form the topcoat layer by one of deposition on the resist layer and self-detachment from the resist layer. The metal-containing material may include at least one of a transition metal and a post-transition metal, possibly in the form of one or more metal oxides. The metal-containing material may also comprise one or more metalloids. The metal-containing material may include a self-dissociating fluorine-functionalized metal additive configured to be included in a resist mixture used to form the resist layer.
Further embodiments of the present invention may include a multi-layer patterned material film stack that includes a resist layer formed on one or more additional layers (e.g., a hard mask layer and an organic planarization layer). A metal-containing topcoat layer is formed over the resist layer and may be considered as part of the stack. The stack may be formed on a semiconductor substrate or other type of substrate, layer or material.
For example, an EUV lithography tool (e.g., ASM L NXE: 3300B or NXE: 3350B) operating at a wavelength of 13.5nm may be modified to perform the above-described type of EUV lithography process, including forming a metal-containing topcoat layer using the techniques disclosed herein.
Examples of integrated circuit structures that can be formed using the EUV lithography process disclosed herein include nanosheet Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. The use of the metal-containing topcoat layer disclosed herein may facilitate the fabrication of such devices by increasing the EUV sensitivity of the stack, thereby facilitating the formation of features below 10 nm. Similar improvements are provided for alternative ranges of feature sizes (e.g., features below 50 nm). A wide variety of other types of integrated circuit devices may be fabricated using an EUV lithographic process that includes one or more iterations of at least a portion of the steps shown in fig. 1-8.
In the above description, various materials and dimensions for the different elements are provided. These materials are given by way of example only, and the embodiments are not limited to the specific examples given, unless otherwise specified. Similarly, unless otherwise specified, all dimensions are given by way of example, and embodiments of the invention are not limited to the specific dimensions or ranges given.
It will be appreciated that the various layers, structures and/or regions described above are not necessarily drawn to scale. In addition, for ease of explanation, one or more layers, structures, and regions commonly used to form semiconductor devices or structures may not be explicitly shown in a given figure. This does not mean that any layers, structures and regions not explicitly shown are omitted from the actual semiconductor structure.
Further, it is to be understood that the embodiments of the invention discussed herein are not limited to the specific process steps shown and described herein. In particular, with respect to semiconductor process steps, it is emphasized that the description provided herein is not intended to encompass all process steps that may be used to form a functional semiconductor integrated circuit device. Rather, certain processing steps typically used in forming semiconductor devices, such as wet cleaning and annealing steps, are not intentionally described herein for purposes of economy of description.
The terms "about" or "substantially" as used herein with respect to thickness, width, percentage, range, and the like are intended to mean close or approximate, but not exact. For example, the term "about" or "substantially" as used herein means that a small margin of error, such as, by way of example only, 1% or less than the stated amount, may exist. Moreover, the illustrated ratio of one layer, structure, and/or region to another layer, structure, and/or region in the figures is not necessarily intended to represent an actual ratio.
Semiconductor devices and methods of forming the same according to the above-described techniques may be used in a variety of applications, hardware and/or electronic systems, including but not limited to personal computers, communication networks, electronic commerce systems, portable communication devices (e.g., cellular and smart phones), solid state media storage devices, functional circuits, and the like. One of ordinary skill in the art, in view of the teachings provided herein, will be able to contemplate other implementations and applications of embodiments of the present invention.
In some embodiments of the present invention, the above-described techniques are used in connection with the fabrication of semiconductor integrated circuit devices, including by way of non-limiting example, CMOS devices, MOSFET devices, and/or FinFET devices, and/or other types of semiconductor integrated circuit devices incorporating or utilizing CMOS, MOSFET, and/or FinFET technologies.
Thus, at least a portion of one or more of the semiconductor structures described herein may be implemented in an integrated circuit. The resulting integrated circuit chips may be distributed by the manufacturer in raw wafer form (i.e., a single wafer having a plurality of unpackaged chips), bare die, or packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier, leads mounted on a motherboard or other higher level carrier) or in a multi-chip package (e.g., a ceramic carrier with either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product (e.g., a motherboard) or (b) an end product. The end product can be any product that contains integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The description of various embodiments of the present invention has been presented for purposes of illustration but is not intended to be exhaustive or limited to the disclosed embodiments of the invention. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the invention. The terms used herein were chosen in order to best explain the principles of the invention, the practical application or technical improvements of the technology found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments of the invention disclosed herein.

Claims (19)

1. A lithographic patterning method, comprising:
forming a multi-layer patterned material film stack on a semiconductor substrate, the patterned material film stack comprising a resist layer formed on one or more additional layers;
forming a metal-containing topcoat layer on the resist layer;
exposing said multilayer patterned material film stack to a patterning radiation through said metal-containing topcoat to
Forming a desired pattern in the resist layer;
removing the metal-containing topcoat;
developing the pattern formed in the resist layer;
etching at least one underlying layer according to the developed pattern; and
removing the remaining portions of the resist layer;
wherein forming the metal-containing topcoat layer over the resist layer comprises forming the metal-containing topcoat layer using a self-separation process from the resist layer.
2. The method of claim 1, wherein the one or more additional layers of the patterned material film stack comprise at least one of:
a hard mask layer; and
and an organic planarization layer.
3. The method of claim 2, wherein etching at least one underlying layer according to the developed pattern comprises etching the hard mask layer.
4. The method of claim 1, wherein forming the metal-containing topcoat layer over the resist layer comprises forming the metal-containing topcoat layer over the resist layer using a deposition process.
5. The method of claim 4, wherein the deposition process for forming the metal-containing topcoat layer comprises an atomic layer deposition process.
6. The method of claim 4, wherein the deposition process for forming the metal-containing topcoat layer comprises a spin-on process.
7. The method of claim 1, wherein forming the metal-containing topcoat layer using a self-separation process from the resist layer comprises:
providing a self-separating material in a resist mixture used to form the resist layer;
using the resist mixture to form the resist layer; and
subjecting the resist layer to a specified process to self-dissociate the self-dissociating material from the resist layer to form the metal-containing topcoat layer.
8. The method of claim 7, wherein the designated process of self-separating the self-detaching material from the resist layer to form the metal-containing topcoat layer comprises a post-application bake process.
9. The method of claim 1, wherein the metal-containing topcoat comprises at least one transition metal, and the at least one transition metal comprises at least one of hafnium (Hf), zirconium (Zr), tantalum (Ta), tungsten (W), chromium (Cr), cobalt (Co), iron (Fe), and platinum (Pt).
10. The method of claim 1, wherein the metal-containing topcoat comprises at least one post-transition metal, and the at least one post-transition metal comprises tin (Sn).
11. The method of claim 1, wherein the metal-containing topcoat further comprises at least one metalloid, and the at least one metalloid comprises antimony (Sb).
12. The method of claim 1, wherein the metal-containing topcoat layer is soluble in a developer solution used to develop a pattern formed in the resist layer.
13. The method of claim 1, wherein removing the metal-containing topcoat layer comprises removing the metal-containing topcoat layer as part of developing the pattern in the resist layer.
14. A semiconductor structure, comprising:
a semiconductor substrate;
a plurality of patterned material film stacks formed on the semiconductor substrate, the patterned material film stacks comprising a resist layer formed on one or more additional layers; and
a metal-containing topcoat layer formed over the resist layer.
15. The semiconductor structure of claim 14, wherein said metal-containing topcoat layer is soluble in a developer solution used to develop a pattern formed in said resist layer.
16. A metal-containing material configured to form the metal-containing topcoat layer of the semiconductor structure of claim 14, the metal-containing material configured to form the metal-containing topcoat layer by one of depositing on the resist layer and self-detaching from the resist layer.
17. The metal-bearing material of claim 16, wherein the metal-bearing material comprises at least one of a transition metal and a post-transition metal.
18. The metal-containing material of claim 16, wherein the metal-containing material comprises a metal oxide.
19. The metal-containing material of claim 16, wherein the metal-containing material comprises a self-segregated fluorine-functionalized metal additive configured to be included in a resist mixture used to form the resist layer.
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