CN111509035A - Low-cost high-performance groove type power semiconductor device and preparation method thereof - Google Patents

Abstract

The invention relates to a trench type power semiconductor device and a preparation method thereof, in particular to a low-cost high-performance trench type power semiconductor device and a preparation method thereof, belonging to the technical field of trench type power semiconductor devices. After at least one implanted region of the second conductivity type of the substrate is arranged between the second trench of the substrate cell and the terminal area, it can prevent breakdown at the bottom of the second trench of the substrate cell during withstand voltage, and fully increase the terminal area The withstand voltage can reduce the junction depth requirement of the second conductivity type body region of the substrate terminal, improve the degree of freedom of design, and make the power semiconductor device have higher breakdown voltage and reliability, or under the same breakdown voltage, The area of the device can be further reduced, the cost can be reduced, and the reliability of the power semiconductor device can be improved at the same time.

Description

Low-cost high-performance trench type power semiconductor device and preparation method thereof

technical field

The invention relates to a trench type power semiconductor device and a preparation method thereof, in particular to a low-cost high-performance trench type power semiconductor device and a preparation method thereof, belonging to the technical field of trench type power semiconductor devices.

Background technique

At present, power semiconductor devices are developing rapidly. On the one hand, the technology of IGBT (Insulated Gate Bipolar Transistor) and VDMOS are constantly innovating to achieve excellent performance; on the other hand, low cost has also become the pursuit goal of power semiconductor development. In the processing cost of power semiconductors, the cost of the mask and the corresponding photolithography process are often the main factors. Therefore, reducing the number of masks becomes the key to reducing the cost of the device. In most cases, there is often a trade-off between high-performance devices and low cost, unless new devices, process methods, etc. appear.

FIG. 1 to FIG. 9 are cross-sectional views of the specific preparation process steps of the front surface structure of the existing trench-type power semiconductor device, taking an N-type power semiconductor device as an example, specifically,

As shown in FIG. 1 , an N-type semiconductor substrate 1 is provided, and a first photoresist layer 2 of the substrate is coated on the front surface of the semiconductor substrate 1 , and the first photoresist layer 2 of the substrate is subjected to Photolithography is performed to obtain the first photoresist layer window 6 of the substrate passing through the first photoresist layer 2 of the substrate. The semiconductor substrate 1 is trench-etched by using the substrate first photoresist layer 2 and the substrate first photoresist layer window 6 to obtain substrate cell trenches 4 in the semiconductor substrate 1 and substrate terminal trenches 5 .

As shown in FIG. 2 , the first photoresist layer 2 of the substrate is removed by using technical means commonly used in the technical field, and thermal oxidation is performed on the front surface of the semiconductor substrate 1 to obtain a surface covering the sidewalls and bottom walls of the cell trenches 4 of the substrate. The substrate cell trench insulating oxide layer 7 and the substrate terminal trench insulating oxide layer 9 covering the sidewalls and bottom walls of the substrate terminal trench 5 .

After the substrate cell trench insulating oxide layer 7 and the substrate terminal trench insulating oxide layer 9 are obtained, conductive polysilicon is deposited on the front surface of the semiconductor substrate 1 to obtain the substrate cell trench filled in the substrate cell trench 4 The groove polysilicon body 8 and the substrate terminal trench conductive polysilicon 10 filled in the substrate terminal trench 5, the substrate cell trench polysilicon body 8 passes through the substrate cell trench insulating oxide layer 7 and the sidewall of the substrate cell trench 4 and bottom wall insulation isolation; the substrate terminal trench polysilicon body 10 can be insulated and isolated from the sidewall and bottom wall of the substrate terminal trench 5 through the substrate terminal trench insulating oxide layer 9 .

As shown in FIG. 3 , P-type impurity ion implantation is performed on the front surface of the semiconductor substrate 1 to obtain a substrate P-type layer 11 on the upper part of the semiconductor substrate 1 . The substrate P-type layer 11 penetrates the front surface of the semiconductor substrate 1 , and the substrate P The type layer 11 extends vertically downward from the front surface of the semiconductor substrate 1 , and the substrate P type layer 11 is located above the substrate cell trench 4 and the substrate terminal trench 5 corresponding to the groove bottom.

As shown in FIG. 4 , the second photoresist layer 12 of the substrate is obtained by coating the front surface of the semiconductor substrate 1 , and the second photoresist layer 12 of the substrate is subjected to photolithography by using the second mask plate 13 of the substrate.

As shown in FIG. 5 , the semiconductor substrate 1 is shielded by the second photoresist layer 12 of the substrate, and P-type impurity ions and N-type impurity ions are implanted and trapped on the front surface of the semiconductor substrate 1 , so that the semiconductor substrate is The central area of 1 obtains the substrate P-type base region 15 and the substrate N+ source region 16 located above the substrate P-type base region 15, the substrate N+ source region 16 is adjacent to the substrate P-type base region 15, and the substrate P-type base region 15 It is located above the bottom of the cell groove 4 of the substrate. Meanwhile, after the substrate P-type base region 15 is obtained, the substrate P-type body region 14 can be obtained by using the substrate P-type layer 11 in the terminal region of the semiconductor substrate 1 .

As shown in FIG. 6 , the second photoresist layer 12 of the substrate is removed, and an insulating dielectric layer is deposited on the front surface of the semiconductor substrate 1 to obtain a substrate insulating dielectric layer 17 covering the front surface of the semiconductor substrate 1 . After the substrate insulating medium layer 17 is obtained, the substrate third photoresist layer 18 is obtained by coating the substrate insulating medium layer 17 , and the substrate third photoresist layer 18 can be photoetched by using the substrate third mask 19 , so as to obtain a plurality of windows 20 of the third photoresist layer of the substrate passing through the third photoresist layer 18 of the substrate.

As shown in FIG. 7 , the substrate insulating dielectric layer 17 is etched by using the third substrate photoresist layer 18 and the substrate third photoresist layer window 20 to obtain substrate source contact holes penetrating the substrate insulating dielectric layer 17 21 , the substrate source contact hole 21 is directly corresponding to the substrate third photoresist layer window 20 , and the substrate source contact hole 21 also penetrates the substrate N+ source region 16 under the substrate insulating medium layer 17 .

As shown in FIG. 8 , the above-mentioned third photoresist layer 18 of the substrate is removed, and metal deposition is performed on the front surface of the semiconductor substrate 1 to obtain a front surface metal layer covering the substrate insulating medium layer 17 .

After the metal layer on the front side of the substrate is obtained, the fourth photoresist layer 21 of the substrate is obtained by coating the metal layer on the front side of the substrate, and the fourth photoresist layer 21 of the substrate is photoetched by using the fourth mask plate 22 of the substrate to obtain a through The substrate fourth photoresist layer window 24 of the substrate fourth photoresist layer 21 .

The metal layer on the front side of the substrate is etched by using the fourth photoresist layer 21 of the substrate and the window 24 of the fourth photoresist layer of the substrate to obtain the metal layer window 23 on the front side of the substrate passing through the metal layer on the front side of the substrate. The metal layer on the front side of the substrate can be divided into a metal layer 65 on the front side of the substrate and a terminal metal layer 68 on the front side of the substrate. The metal layer 20 is located on the outer circumference of the central area of the semiconductor substrate 1 .

As shown in FIG. 9 , a passivation material is deposited on the front side of the semiconductor substrate 1 to obtain a substrate passivation layer 25 on the front side of the semiconductor substrate 1 , and the substrate passivation layer 25 covers the cell metal layer 65 on the front side of the substrate. and on the terminal metal layer 68 on the front side of the substrate.

The fifth photoresist layer 26 of the substrate is obtained by coating on the passivation layer 25 of the substrate, and the fifth photoresist layer 26 of the substrate is photoetched by using the fifth mask of the substrate 27 to obtain the fifth photoresist layer 26 that penetrates the substrate The substrate fifth photoresist layer window 28 is used to etch the substrate passivation layer 25 by using the substrate fifth photoresist layer 26 and the substrate fifth photoresist layer window 28 to obtain a substrate penetrating the substrate passivation layer 25 The passivation layer window 29 is used to expose the cell metal layer 65 on the front side of the substrate by using the substrate passivation layer window 29 .

After the above steps are performed, the fifth photoresist layer 26 of the substrate needs to be removed, and a required backside process is performed on the backside of the semiconductor substrate 1 to obtain the required backside structure. According to the different backside structures, IGBT devices can be prepared. or MOSFET devices.

It can be seen from the above specific process steps that the substrate P-type layer 11 is first prepared on the upper part of the semiconductor substrate 1, and then the substrate P-type base region 15 and the substrate P-type body region 14 can be formed through the substrate P-type layer 11, and the substrate P-type layer can be formed. 11 is obtained by implanting P-type impurity ions on the entire front surface of the semiconductor substrate 1 . In order to achieve a relatively high breakdown voltage, the junction depth of the substrate P-type layer 11 after the well is pushed and the depths of the substrate cell trench 4 and the substrate terminal trench 5 in the semiconductor substrate 1 should not be too different. Otherwise, the prepared semiconductor The device is prone to breakdown at the bottom of the substrate cell trench 4 adjacent to the substrate termination trench 5 , as shown in the breakdown region 30 in FIG. 10 .

When the terminal breakdown voltage is improved by increasing the junction depth of the P-type layer 11 of the substrate, the junction depth of the basic P-type base region 15 in the cell region of the substrate will also increase correspondingly, which will lead to trenches in the cell region of the device. The channel length increases and the JFET effect manifests, resulting in an increase in the turn-on voltage drop of the device. Therefore, the closest prior art has a trade-off relationship between achieving the smallest on-voltage drop and the highest BV, and cannot achieve the optimal value at the same time.

SUMMARY OF THE INVENTION

The purpose of the present invention is to overcome the deficiencies in the prior art, and to provide a low-cost, high-performance trench-type power semiconductor device and a preparation method thereof, which can achieve higher breakdown voltage and improve the reliability of the power semiconductor device operation. , compatible with existing processes.

According to the technical solution provided by the present invention, the low-cost high-performance trench-type power semiconductor device includes a semiconductor substrate with a first conductivity type, a cell region disposed in the central region of the semiconductor substrate, and a cell region disposed in the semiconductor substrate The terminal area on the bottom and located in the outer circle of the cell area; the cell in the cell area adopts a groove structure;

On the top plan view of the power semiconductor device, the cell of the cell region includes a second trench in the annular substrate cell and a plurality of liners located in the inner circumference of the second trench in the annular substrate cell the first groove of the bottom cell, and the terminal area is located on the outer ring of the second groove of the annular substrate cell;

On the cross section of the power semiconductor device, the second conductive type base region of the substrate and the first conductive substrate located above the second conductive type base region of the substrate are provided on both sides of the first trench of the substrate cell type source region, the base region of the second conductivity type of the substrate is located above the corresponding groove bottom of the first trench of the substrate cell and the second trench of the substrate cell, and the base region of the second conductivity type of the substrate, the first trench of the substrate cell The conductive type source regions are all in contact with the corresponding sidewalls of the first trenches of the adjacent substrate cells;

On the cross section of the power semiconductor device, the second trench in the substrate cell is adjacent to the outer sidewall of the first trench in the substrate cell and the corresponding base region of the second conductivity type of the substrate and the source of the first conductivity type of the substrate At least one implanted region of the second conductivity type of the substrate is arranged between the sidewall of the second trench of the substrate cell adjacent to the termination region and the termination region, and the second trench of the substrate cell is adjacent to the outer sidewall of the termination region and the termination region. The second conductive type implanted region of the adjacent substrate is in contact, and the depth of the second conductive type implanted region of the substrate in the semiconductor substrate is greater than that of the first trench of the substrate cell and the second trench of the substrate cell in the semiconductor substrate the depth of the bottom;

A cell metal layer on the front side of the substrate is arranged above the front side of the semiconductor substrate, and the cell metal layer on the front side of the substrate can be connected with the base region of the second conductivity type of the substrate, the source region of the first conductivity type of the substrate, and the element of the substrate. The second conductive type implanted region of the substrate contacted by the second trench sidewall of the cell is ohmically contacted.

Corresponding inner sidewalls and bottom walls of the first trench of the substrate cell and the second trench of the substrate cell are covered with an insulating oxide layer of the substrate cell, and the first trench of the substrate cell and the corresponding inner sidewall and bottom wall of the substrate cell are covered with an insulating oxide layer of the substrate cell. The second trench is also filled with substrate cell trench polysilicon; the substrate cell trench polysilicon filled in the first trench of the substrate cell passes through the liner in the filled first trench of the substrate cell The bottom cell insulating oxide layer is insulated from the inner sidewall and bottom wall of the filled first trench of the substrate cell, and the substrate cell trench polysilicon filled in the second trench of the substrate cell passes through the filled lining The substrate cell insulating oxide layer in the second trench of the bottom cell is insulated and isolated from the inner sidewall and bottom wall of the filled second trench of the substrate cell;

The slots corresponding to the first trench of the substrate cell and the second trench of the substrate cell are covered by the substrate insulating medium layer covering the front surface of the semiconductor substrate, and the substrate in the first trench of the substrate cell The cell trench polysilicon and the substrate cell trench polysilicon in the second trench of the substrate cell can be insulated and isolated from the cell metal layer on the front side of the substrate through the substrate insulating medium layer.

The substrate front cell metal layer is supported on the substrate insulating medium layer, and the substrate front terminal metal layer is also provided on the substrate insulating medium layer, the substrate front terminal metal layer, the substrate front cell metal layer The layers are separated by a base metal passivation layer, and the base metal passivation layer is supported on the terminal metal layer on the front side of the substrate and the cell metal layer on the front side of the substrate;

It also includes a substrate passivation layer window penetrating the substrate metal passivation layer, and the substrate front surface cell metal layer corresponding to the substrate passivation layer window can be exposed through the substrate passivation layer window.

On the cross section of the power semiconductor device, the termination region includes at least one substrate termination trench and substrate termination second conductivity type body regions located on both sides of the substrate termination trench, the substrate termination first The two-conductivity-type body region is located above the trench bottom corresponding to the substrate terminal trench, the first trench of the substrate cell, and the second trench of the substrate cell;

A substrate terminal insulating oxide layer is provided on the sidewall and bottom wall of the substrate terminal trench, and the substrate terminal trench with the substrate terminal insulating oxide layer is filled with polysilicon. The trench polysilicon is insulated and isolated from the sidewall and bottom wall of the substrate termination trench through the substrate termination insulating oxide layer; the notch of the substrate termination trench is covered by the substrate insulating dielectric layer.

On the cross section of the power semiconductor device, the cell region further includes a cell edge transition region trench, and the cell edge transition region trench is located between the second cell trench and the termination region of the substrate, and the substrate second trench The depth of the conductive type implanted region in the semiconductor substrate is greater than the depth of the cell edge transition region trench in the semiconductor substrate, and the second conductive type implantation of the substrate is in contact with the sidewall of the second trench of the substrate cell the outer sidewall of the cell edge transition zone trench is covered by the zone;

The groove bottom of the cell edge transition region trench is located below the base region of the second conductivity type of the substrate, the substrate cell insulating oxide layer is provided on the inner sidewall and the bottom wall of the cell edge transition region trench, and the substrate cell insulation oxide layer is arranged on the inner sidewall and the bottom wall of the cell edge transition region trench. The cell edge transition region trench of the bottom cell insulating oxide layer is also filled with substrate cell trench polysilicon, and the substrate cell trench polysilicon is insulated by the substrate cell in the cell edge transition region trench. The oxide layer is insulated from the sidewall and bottom wall of the trench in the transition region of the cell edge where it is located.

A preparation method of a low-cost high-performance trench type power semiconductor device, the preparation method comprises the following steps:

Step 1. Provide a semiconductor substrate with a first conductivity type, and perform required trench etching on the front surface of the semiconductor substrate to obtain the first trench of the substrate cell in the cell region of the semiconductor substrate a groove and a second trench in the substrate cell, and the second trench in the substrate cell is adjacent to the terminal area;

Step 2. Disposing an insulating oxide layer of the substrate cell in the first trench of the substrate cell and the second trench of the substrate cell, and in the first trench of the substrate cell and the second trench of the substrate cell The groove is also filled with substrate cell trench polysilicon; the insulating oxide layer of the substrate cell covers the side walls and bottom walls corresponding to the first trench of the substrate cell, the second trench of the substrate cell, and the bottom wall;

The substrate cell trench polysilicon filled in the first trench of the substrate cell passes through the substrate cell insulating oxide layer in the filled substrate cell first trench and the filled substrate cell first trench The sidewall and bottom wall of the groove are insulated and isolated, and the polysilicon of the substrate cell trench filled in the second trench of the substrate cell is connected to the insulating oxide layer of the substrate cell in the second trench of the filled substrate cell through the substrate cell insulating oxide layer. The sidewall and bottom wall of the filled second trench of the substrate cell are insulated and isolated;

Step 3. Prepare a base region of the second conductivity type of the substrate, a source region of the first conductivity type of the substrate, and at least one implanted region of the second conductivity type of the substrate in the semiconductor substrate; wherein, the base region of the second conductivity type of the substrate is located in the substrate. Above the corresponding groove bottom of the first trench of the bottom cell and the second trench of the substrate cell, the source region of the first conductivity type of the substrate is located above the base region of the second conductivity type of the substrate, and the implantation region of the second conductivity type of the substrate is located Between the second trench of the substrate cell and the termination region, the depth of the implanted region of the second conductivity type of the substrate in the semiconductor substrate is greater than that of the first trench of the substrate cell and the second trench of the substrate cell in the semiconductor substrate. the depth of the bottom;

The implanted region of the second conductivity type of the substrate adjacent to the second trench of the substrate cell is in contact with the outer sidewall of the second trench of the substrate cell adjacent to the termination region, and the second trench of the substrate cell is adjacent to the first trench of the substrate cell The outer sidewall of the trench is in contact with the second conductive type base region of the substrate and the first conductive type source region of the substrate, and the outer sidewalls of the first trench of the substrate cell are all in contact with the corresponding second conductive type base region of the substrate and the substrate. bottom first conductivity type source contact;

Step 4: Deposition a dielectric layer on the front side of the above-mentioned semiconductor substrate to obtain a substrate insulating dielectric layer covering the front side of the semiconductor substrate; perform contact hole etching on the substrate insulating dielectric layer to obtain a through-substrate insulating dielectric layer The substrate source contact hole;

In step 5, metal deposition is performed on the front side of the above-mentioned semiconductor substrate to obtain a front side metal layer of the substrate. The front side metal layer of the substrate is covered on the insulating medium layer of the substrate. The cell metal layer on the front side of the substrate and the terminal metal layer on the front side of the substrate are obtained. In the substrate source contact hole; the substrate front cell metal layer and the substrate second conductivity type base region, the substrate first conductivity type source region and the substrate cell first region filled in the substrate source contact hole The ohmic contact of the implanted region of the second conductivity type of the substrate in contact with the sidewalls of the two trenches;

Step 6, depositing a passivation layer on the front side of the above-mentioned semiconductor substrate to obtain a substrate metal passivation layer, the substrate metal passivation layer covering the cell metal layer on the front side of the substrate and the terminal metal layer on the front side of the substrate on the substrate, and the substrate metal passivation layer can be used to separate the front surface cell metal layer of the substrate and the front terminal metal layer of the substrate;

Step 7: Etch the above-mentioned substrate metal passivation layer to obtain a substrate metal passivation layer window passing through the substrate metal passivation layer. The front cell metal layer of the substrate corresponding to the chemical layer window is exposed;

Step 8. Perform a required backside process on the backside of the semiconductor substrate to obtain a required substrate backside structure on the backside of the semiconductor substrate.

When trench etching is performed on the semiconductor substrate, a substrate termination trench located in the termination region can also be obtained, and the substrate termination insulating oxide layer is prepared in the substrate termination trench and filled in the substrate termination The substrate terminal trench polysilicon in the trench, the substrate terminal trench polysilicon is insulated and isolated from the inner sidewall and bottom wall of the substrate terminal trench where it is located through the substrate terminal insulating oxide layer;

In step 3, when the base region of the second conductivity type of the substrate is prepared, the second conductivity type body region of the substrate terminal passing through the terminal region can also be obtained at the same time, and the second conductivity type body region of the substrate terminal is located at the terminal end of the substrate. Above the bottom of the trench, the doping concentration of the second conductive type body region of the substrate terminal is lower than the doping concentration of the second conductive type base region of the substrate.

For step 3, it specifically includes the following steps:

Step 3.1. Perform the implantation of impurity ions of the second conductivity type above the front surface of the semiconductor substrate to prepare at least one substrate second trench between the second trench of the substrate cell and the substrate terminal trench of the adjacent cell region. a conductivity type implanted region, and the substrate second conductivity type implanted region adjacent to the second trench of the substrate cell is in contact with the sidewall of the substrate cell second trench adjacent to the termination region, the substrate second conductivity type implanted The depth of the region in the semiconductor substrate is greater than the depths of the first trench of the substrate cell, the second trench of the substrate cell and the substrate terminal trench in the semiconductor substrate;

In step 3.2, the second conductivity type impurity ion implantation is performed again on the front surface of the above-mentioned semiconductor substrate to obtain a substrate second conductivity type layer that penetrates the semiconductor substrate, and the substrate second conductivity type layer is located on the first substrate cell. a trench, a second trench of the substrate cell, and above the corresponding trench bottom of the substrate terminal trench;

Step 3.3. Perform the first conductivity type impurity ion implantation and the second conductivity type impurity ion implantation on the above-mentioned semiconductor substrate, and use the implanted second conductivity type impurity ions and the second conductivity type layer of the substrate in the cell area to be in the cell area. The second conductive type base region of the substrate located in the cell region is obtained, and the first conductive type source region of the substrate located above the second conductive type base region of the substrate can be obtained by using the implanted impurity ions of the first conductive type. The bottom first conductive type source region is adjacent to the substrate second conductive type base region; meanwhile, the substrate termination second conductive type body region can be obtained by using the substrate second conductive type layer in the termination region.

For step 3, it specifically includes the following steps:

Step 3.a. Perform ion implantation of impurities of the second conductivity type on the front surface of the semiconductor substrate to obtain a second conductivity type layer of the substrate that penetrates the semiconductor substrate, and the second conductivity type layer of the substrate is located in the cell of the substrate Above the corresponding groove bottom of the first trench, the second trench of the substrate cell and the substrate terminal trench;

Step 3.b. Perform the implantation of impurity ions of the second conductivity type again above the front surface of the upper semiconductor substrate to prepare at least one element between the second trench of the substrate cell and the substrate terminal trench of the adjacent cell region. The implanted region of the second conductivity type of the substrate, and the implanted region of the second conductivity of the substrate adjacent to the second trench of the substrate cell is in contact with the sidewall of the second trench of the substrate cell adjacent to the termination region, the substrate first The depth of the two-conductivity-type implantation region in the semiconductor substrate is greater than the depths of the first trench in the substrate cell, the second trench in the substrate cell, and the substrate terminal trench in the semiconductor substrate;

Step 3.c, performing the first conductivity type impurity ion implantation and the second conductivity type impurity ion implantation on the above-mentioned semiconductor substrate, using the implanted second conductivity type impurity ions and the second conductivity type layer of the substrate in the cell area The second conductive type base region of the substrate located in the cell region can be obtained, and the first conductive type source region of the substrate located above the second conductive type base region of the substrate can be obtained by using the implanted first conductive type impurity ions, so The first conductive type source region of the substrate is adjacent to the second conductive type base region of the substrate; meanwhile, the second conductive type body region of the substrate terminal can be obtained by using the second conductive type layer of the substrate in the terminal region.

When trench etching is performed on the semiconductor substrate, a cell edge transition region trench located in the cell region can also be obtained, and the cell edge transition region trench is located in the second trench and the terminal region of the substrate cell In between, the depth of the implanted region of the second conductivity type of the substrate in the semiconductor substrate is greater than the depth of the cell edge transition region trench in the semiconductor substrate, and the depth of the cell in contact with the sidewall of the second trench of the substrate cell The second conductivity type implantation region of the substrate covers the outer sidewall of the cell edge transition region trench;

The groove bottom of the cell edge transition region trench is located below the base region of the second conductivity type of the substrate, the substrate cell insulating oxide layer is provided on the inner sidewall and the bottom wall of the cell edge transition region trench, and the substrate cell insulation oxide layer is arranged on the inner sidewall and the bottom wall of the cell edge transition region trench. The cell edge transition region trench of the bottom cell insulating oxide layer is also filled with substrate cell trench polysilicon, and the substrate cell trench polysilicon is insulated by the substrate cell in the cell edge transition region trench. The oxide layer is insulated from the sidewall and bottom wall of the trench in the transition region of the cell edge where it is located.

In both the "first conductivity type" and the "second conductivity type", for N-type power semiconductor devices, the first conductivity type refers to N-type, and the second conductivity type is P-type; for P-type power semiconductor devices, the first conductivity type refers to N-type. A conductivity type and a second conductivity type refer to types that are just opposite to N-type power semiconductor devices.

The advantages of the present invention are as follows: after at least one implanted region of the second conductivity type of the substrate is arranged between the second trench and the terminal of the substrate cell, the implanted region of the second conductivity type of the substrate adjacent to the second trench of the substrate cell and all the implanted regions of the second conductivity of the substrate are provided. The second trench of the substrate cell is in contact with the outer sidewall of the terminal region adjacent to the substrate cell, and the addition of the second conductivity type implantation region of the substrate can alleviate the electric field concentration at the bottom of the trench bottom of the second trench of the substrate cell and the cell edge transition region, and reduce the impact of the substrate cell. The electric field strength at the bottom of the second trench of the bottom cell and the bottom of the trench in the transition region of the cell edge prevents premature breakdown at the bottom of the second trench of the substrate cell and the bottom of the trench in the transition region of the cell edge, and fully increases the electrical field in the terminal region. Withstanding voltage, it can reduce the junction depth requirement of the second conductive type body region of the substrate terminal, improve the degree of freedom of design, and make power semiconductor devices have higher breakdown voltage and reliability, or under the same breakdown voltage, can The area of the device is further reduced, the cost is reduced, and the reliability of the power semiconductor device is improved at the same time.

Description of drawings

FIG. 1 to FIG. 9 are specific manufacturing process steps diagrams of the existing power semiconductor devices, wherein

FIG. 1 is a cross-sectional view of a substrate cell trench and a substrate terminal trench after preparation.

FIG. 2 is a cross-sectional view of the substrate cell trench polysilicon and the substrate terminal trench polysilicon after preparation.

FIG. 3 is a cross-sectional view of the substrate after the P-type layer is prepared.

FIG. 4 is a cross-sectional view of the second photoresist layer on the substrate after photolithography is prepared.

5 is a cross-sectional view of a substrate P base region, a substrate N+ source region and a substrate P-type body region after preparation.

FIG. 6 is a cross-sectional view after obtaining a third photoresist layer window of the substrate.

FIG. 7 is a cross-sectional view of a substrate source contact hole obtained.

FIG. 8 is a cross-sectional view after obtaining a metal layer window on the front side of the substrate.

FIG. 9 is a cross-sectional view after obtaining the substrate passivation layer window.

FIG. 10 is a schematic diagram of a breakdown position of a conventional power semiconductor device.

11 to 21 are cross-sectional views of specific manufacturing process steps of the power semiconductor device of the present invention, wherein

FIG. 11 is a cross-sectional view of the first trench in the substrate cell, the second trench in the substrate cell, and the terminal trench in the substrate prepared by the present invention.

12 is a cross-sectional view of the present invention after obtaining the substrate cell trench polysilicon and the substrate terminal trench polysilicon.

FIG. 13 is a cross-sectional view of the present invention after obtaining the P+ implantation region of the substrate.

FIG. 14 is a cross-sectional view of the present invention after obtaining the P-type layer of the substrate.

FIG. 15 is a cross-sectional view of the second photoresist layer of the substrate after photolithography according to the present invention.

16 is a cross-sectional view of the substrate P-type base region, the substrate N+ source region and the substrate P-type body region obtained by the present invention.

FIG. 17 is a cross-sectional view of the present invention after obtaining the window of the third photoresist layer of the substrate.

FIG. 18 is a cross-sectional view after the substrate source contact hole is obtained according to the present invention.

FIG. 19 is a cross-sectional view of the present invention after obtaining a metal layer window on the front side of the substrate.

FIG. 20 is a cross-sectional view after the substrate passivation layer window is obtained in the present invention.

21 is a cross-sectional view of the present invention after removing the sixth photoresist layer of the substrate.

FIG. 22 is a cross-sectional view of the present invention when a cell edge transition region trench is provided in the cell region.

Description of reference numerals: 1-semiconductor substrate, 2-substrate first photoresist layer, 3-substrate first mask, 4-substrate cell trench, 5-substrate terminal trench, 6-substrate first lithography Adhesive layer window, 7-substrate cell trench insulating oxide layer, 8-substrate cell trench polysilicon body, 9-substrate terminal trench insulating oxide layer, 10-substrate terminal trench conductive polysilicon, 11-substrate P-type layer , 12-substrate second photoresist layer, 13-substrate second mask, 14-substrate P-type body region, 15-substrate P-type base region, 16-substrate N+ source region, 17-substrate insulating medium layer, 18-substrate P-type base region -Substrate third mask, 20-substrate third photoresist layer window, 21-substrate fourth photoresist layer, 22-substrate fourth mask, 23-substrate front metal layer window, 24-substrate fourth light Resist layer window, 25-substrate passivation layer, 26-substrate fifth photoresist layer, 27-substrate fifth mask, 28-substrate fifth photoresist layer window, 29-substrate passivation layer window, 30 -Breakdown region, 31-semiconductor substrate, 32-substrate first photoresist layer, 33-substrate cell first trench, 34-substrate terminal trench, 35-substrate first photoresist Layer window, 36-substrate cell trench polysilicon, 37-substrate cell insulating oxide layer, 38-substrate terminal trench polysilicon, 39-substrate terminal insulating oxide layer, 40-substrate second photoresist layer, 41-substrate second photoresist layer window, 42-substrate P+ injection region, 43-substrate P-type layer, 44-substrate third photoresist layer, 45-substrate third mask, 46-substrate third photoresist layer window, 47-substrate P-type base region, 48-substrate N+ source region, 49-substrate terminal P-type body region, 50-substrate insulating dielectric layer, 51-liner Bottom fourth photoresist layer, 52-substrate fourth mask, 53-substrate fourth photoresist layer window, 54-substrate source contact hole, 55-substrate front terminal metal layer, 56-liner Bottom fifth photoresist layer, 57-substrate fifth mask, 58-substrate fifth photoresist layer window, 59-substrate front metal layer window, 60-substrate metal passivation layer, 61-lining Bottom sixth photoresist layer, 62-substrate sixth mask, 63-substrate sixth photoresist layer window, 64-substrate passivation layer window, 65-substrate front cell metal layer, 66-lining Bottom front cell metal layer, 67-substrate cell second trench, 68-substrate front terminal metal layer, 69-substrate first mask and 70-cell edge transition region trench.

Detailed ways

The present invention will be further described below with reference to the specific drawings and embodiments.

As shown in FIG. 21: In order to achieve higher breakdown voltage and improve the reliability of power semiconductor devices, taking N-type trench type power semiconductor devices as an example, the present invention includes a semiconductor substrate 31 having an N conductivity type, The cell area disposed in the central area of the semiconductor substrate 31 and the terminal area disposed on the semiconductor substrate 31 and located in the outer circle of the cell area; the cell in the cell area adopts a trench structure;

On the top plan view of the power semiconductor device, the cells of the cell region include a second trench 67 in the annular substrate cell and a plurality of inner circles located in the second trench 67 in the annular substrate cell The first groove 33 of the substrate cell, the terminal area is located in the outer ring of the second groove 67 of the annular substrate cell;

On the cross section of the power semiconductor device, a substrate P-type base region 47 and a substrate N+ source region 48 located above the substrate P-type base region 47 are provided on both sides of the first trench 33 of the substrate cell , the substrate P-type base region 47 is located above the corresponding groove bottoms of the first trench 33 of the substrate cell and the second trench 67 of the substrate cell, and the substrate P-type base region 47 and the substrate N+ source region 48 are both contact with the corresponding sidewall of the first trench 33 of the adjacent substrate cell;

On the cross section of the power semiconductor device, the second trench 67 in the substrate cell is adjacent to the outer sidewall of the first trench 33 in the substrate cell and the corresponding substrate P-type base region 47 and substrate N+ source region 48 Contact, at least one substrate P+ implantation region 42 is provided between the sidewall of the second trench 67 of the substrate cell adjacent to the termination region and the termination region, and the second trench 67 of the substrate cell is adjacent to the outer sidewall of the termination region and adjacent to the termination region. The depth of the substrate P+ implantation region 42 in the semiconductor substrate 31 is greater than that of the first trench 33 of the substrate cell and the second trench 67 of the substrate cell in the semiconductor substrate 31 the depth within;

A substrate front cell metal layer 66 is provided above the front surface of the semiconductor substrate 31, and the substrate front cell metal layer 66 can be connected to the substrate P-type base region 47, the substrate N+ source region 48 and the substrate element The P+ implant region 42 of the substrate, which is in contact with the sidewall of the second trench 67, is in ohmic contact.

Specifically, the semiconductor substrate 1 can use semiconductor materials commonly used in the technical field, such as silicon, etc. The specific material type can be selected according to actual needs, which will not be repeated here. Generally, a cell region can be formed in the central region of the semiconductor substrate 1, and a terminal region can be formed in the outer circle of the cell region. The specific functions of the cell region and the terminal region in power semiconductors, and the cell region and the terminal region The specific coordination of the interval is consistent with the existing ones, which are well known to those skilled in the art, and will not be repeated here.

In the embodiment of the present invention, the cells in the cell region adopt a trench structure. Specifically, the cells in the cell region include the first trench 33 of the substrate cell and the second trench 67 of the substrate cell, wherein, On the cross section of the power semiconductor device, the second trench 67 of the substrate cell is adjacent to the terminal region, that is, in the central region of the cell region, both the first trench 33 of the substrate cell and the second trench of the substrate cell The groove 67 is between the first trench 33 of the substrate cell and the termination region, and the second trench 67 of the substrate cell is adjacent to the termination region. In the top view of the power semiconductor device, the termination region surrounds the cell region, and in the cell region, the annular second trench 67 of the substrate cell is adjacent to the termination region, and the first trench 33 of the substrate cell is located in the annular region The inner circle of the second groove 67 of the substrate cell, and the number of the first grooves 33 of the substrate cell in the inner circle of the second groove 67 of the substrate cell are selected according to the actual needs, which are specifically related to the existing grooves. type power semiconductor devices, and will not be repeated here.

On the cross section of the power semiconductor device, a substrate P-type base region 47 and a substrate N+ source region 48 are provided on both sides of the first trench 33 of the substrate cell, and the substrate N+ source region 48 is located at the substrate P-type base Above the region 47, and the substrate N+ source region 48 is adjacent to the substrate P-type base region 47, the substrate N+ source region 48 and the substrate P-type base region 47 are in contact with the outer sidewall of the substrate first cell trench 33, namely Above the outer sidewalls of the first trench 33 of the substrate cell, both are in contact with the substrate P-type base region 47 and the substrate N+ source region 48 . The substrate P-type base region 47 is located above the bottom of the first trench 33 in the substrate cell and above the bottom of the second trench 67 in the substrate cell.

On the cross section of the power semiconductor device, the outer sidewall of the second trench 67 of the substrate cell adjacent to the first trench 33 of the substrate cell is in contact with the substrate P-type base region 47 and the substrate N+ source region 48, and at the same time , at least one substrate P+ implantation region 42 is arranged between the side of the second trench 67 of the substrate cell adjacent to the termination region and the termination region, and the substrate P+ implantation region 42 adjacent to the second trench 67 of the substrate cell In contact with the outer sidewalls of the second trench 67 of the substrate cell adjacent to the termination region. The depth of the substrate P+ implantation region 42 in the semiconductor substrate 31 is greater than the depth of the substrate cell first trench 33 and the substrate cell second trench 67 in the semiconductor substrate 31, that is, the substrate P+ implantation region The bottom of 42 is located below the corresponding groove bottoms of the first trench 33 of the substrate cell and the second trench 67 of the substrate cell. When there are multiple substrate P+ implanted regions 42, only the substrate P+ implanted regions 42 adjacent to the second trench 67 of the substrate cell contact the outer sidewall of the second trench 67 of the substrate cell adjacent to the termination region .

During specific implementation, the substrate P-type base region 47 and the substrate N+ source region 48 may also be provided on the side of the second trench 67 in the substrate cell adjacent to the terminal region. Of course, the second trench 67 in the substrate cell The substrate P-type base region 47 on the side adjacent to the terminal region and the substrate P-type base region 47 on both sides of the first trench 33 in the substrate cell are formed by the same process step, and the second trench 67 in the substrate cell is adjacent to the terminal. The substrate N+ source region 48 on one side of the substrate cell and the substrate N+ source region 48 on both sides of the first trench 33 in the substrate cell are obtained by the same process steps. After the substrate P-type base region 47 and the substrate N+ source region 48 are disposed on the side of the second trench 67 of the substrate cell adjacent to the termination region, the substrate P-type base region 47 and the substrate N+ source region 48 are both In contact with the outer sidewalls of the second trench 67 of the substrate cell adjacent to the termination region. In addition, after the substrate P-type base region 47 and the substrate N+ source region 48 are provided on the side of the second trench 67 of the substrate cell adjacent to the terminal region, the corresponding substrate P-type base region 47 and the substrate N+ source region The region 48 covers the upper portion of the substrate P+ implanted region 42 , and the substrate P-type base region 47 and the substrate N+ source region 48 are in contact with the substrate P+ implanted region 42 . In the top view of the power semiconductor device, the substrate P+ implantation region 42 is annular, and the substrate P+ implantation region 42 surrounds the second trench 67 of the substrate cell. When there are a plurality of annular substrate P+ implantation regions 42, adjacent substrate P+ implantation regions 42 are spaced apart from each other.

In order to form the source electrode of the power semiconductor device, a substrate front cell metal layer 66 is provided above the front surface of the semiconductor substrate 31, the substrate cell metal layer 66 is connected to the substrate P-type base region 47, the substrate N+48 and The substrate P+ implanted region 42 in contact with the outer sidewall of the second trench 67 of the substrate cell is in ohmic contact. When there are multiple substrate P+ implanted regions 42, except the substrate P+ implanted region 42 in contact with the outer sidewall of the second trench 67 of the substrate cell and the cell metal layer 66 on the front side of the substrate in ohmic contact, the rest of the substrate The P+ implanted regions 42 all need to be insulated and isolated from the cell metal layer 66 on the front side of the substrate.

Further, the corresponding inner sidewalls and bottom walls of the first trench 33 of the substrate cell and the second trench 67 of the substrate cell are covered with the substrate cell insulating oxide layer 37, and the first trench of the substrate cell The trench 33 and the second trench 67 of the substrate cell are also filled with the substrate cell trench polysilicon 36; the substrate cell trench polysilicon 36 filled in the first trench 33 of the substrate cell is filled with The substrate cell insulating oxide layer 37 in the first trench 33 of the substrate cell is insulated from the inner sidewall and bottom wall of the filled first trench 33 of the substrate cell, and is filled in the second trench of the substrate cell The substrate cell trench polysilicon 36 in the trench 67 passes through the substrate cell insulating oxide layer 37 in the filled substrate cell second trench 67 and the inner sidewall of the filled substrate cell second trench 67 and bottom wall insulation;

The first trench 33 of the substrate cell and the corresponding notch of the second trench 67 of the substrate cell are covered by the substrate insulating medium layer 50 covering the front surface of the semiconductor substrate 31, and the first trench 33 of the substrate cell The inner substrate cell trench polysilicon 36 and the substrate cell trench polysilicon 36 in the second substrate cell trench 67 can be insulated and isolated from the substrate front cell metal layer 66 through the substrate insulating medium layer 50 .

In the embodiment of the present invention, the substrate cell insulating oxide layer 37 is provided on the inner sidewall and the bottom wall of the first trench 33 in the substrate cell, and at the same time, the inner sidewall and bottom of the second trench 67 in the substrate cell are provided. The substrate cell insulating oxide layer 37 is also provided on the wall, the substrate cell insulating oxide layer 37 is a silicon dioxide layer, and the substrate cell insulating oxide layer 37 can be grown on the first substrate cell simultaneously by thermal oxidation. within trench 33 and grown within second trench 67 of the substrate cell.

Both the first trench 33 of the substrate cell and the second trench 67 of the substrate cell are filled with the substrate cell trench polysilicon 36, and the substrate cell trench polysilicon 36 is a conventional conductive polysilicon , wherein, the substrate cell trench polysilicon 36 filled in the substrate cell first trench 33 passes through the substrate cell insulating oxide layer 37 in the filled substrate cell first trench 33 and the filled substrate cell trench polysilicon 36 The inner sidewall and bottom wall of the first trench 33 of the substrate cell are insulated and isolated, and the polysilicon 36 of the substrate cell trench filled in the second trench 67 of the substrate cell passes through the filled second trench of the substrate cell The substrate cell insulating oxide layer 37 in the substrate cell 67 is insulated and isolated from the inner sidewall and bottom wall of the filled substrate cell second trench 67 .

In the specific implementation, the polysilicon 36 in the first trench 33 of the substrate cell and the second trench 67 of the substrate cell are drawn out and then in ohmic contact with the gate metal, so that power can be obtained. As for the gate electrode of the semiconductor device, the specific form of forming the gate electrode by using the substrate cell trench polysilicon 36 to cooperate with the gate metal is consistent with the existing ones, and will not be repeated here. The gate metal and the front cell metal layer 66 of the substrate are insulated and isolated from each other, and the specific positional relationship between the gate metal and the cell metal layer 66 on the front side of the substrate is consistent with the existing ones, which are well known to those skilled in the art. , and will not be repeated here.

In the embodiment of the present invention, the cells in the cell area are connected together by the front cell metal layer 66 of the substrate. A substrate insulating medium layer 50 is provided on the front side of the semiconductor substrate 31, the substrate insulating medium layer 50 is a silicon dioxide layer, and the substrate insulating medium layer 50 covers the front side of the semiconductor substrate 31, so that the substrate insulating medium layer 50 is used. The layer 50 can cover the notch corresponding to the first trench 33 of the substrate cell and the second trench 67 of the substrate cell, and the substrate front cell metal layer 66 is supported on the substrate insulating medium layer 50, so that the front side of the substrate is supported. The cell metal layer 66 utilizes the insulating isolation between the substrate insulating dielectric layer 50 and the substrate cell trench polysilicon 36 .

Further, the substrate front cell metal layer 66 is supported on the substrate insulating medium layer 50, and the substrate front terminal metal layer 55 is also provided on the substrate insulating medium layer 50, and the substrate front terminal metal layer is 66. The substrate front cell metal layer 55 is separated by the substrate metal passivation layer 60, and the substrate metal passivation layer 60 is supported on the substrate front terminal metal layer 55 and the substrate front cell metal layer 66;

It also includes a substrate passivation layer window 64 penetrating through the substrate metal passivation layer 60, and through the substrate passivation layer window 64, the substrate front cell metal layer corresponding to the substrate passivation layer window 64 can be made 66 exposed.

In the embodiment of the present invention, the substrate front terminal metal layer 55 is further provided on the substrate insulating medium layer 50. The substrate front terminal metal layer 55 and the substrate front cell metal layer 66 are the same process step layer, and the substrate front terminal metal layer 55 is the same process step layer. The metal layer 55 corresponds to the terminal area of the semiconductor substrate 31, and the terminal metal layer 55 on the front side of the substrate and the cell metal layer 66 on the front side of the substrate are separated by the substrate metal passivation layer 60, and the substrate metal passivation layer 60 is supported on the substrate. The terminal metal layer 55 on the front side of the substrate and the cell metal layer 66 on the front side of the substrate are described. The metal passivation layer 60 of the substrate can be made of existing commonly used materials, such as silicon nitride, and the specific material type can be selected according to actual needs, which will not be repeated here.

In order to facilitate the extraction of the cell metal layer 66 on the front side of the substrate, the substrate metal passivation layer 60 is etched to obtain a substrate passivation layer window 64 penetrating the substrate metal passivation layer 60. The layer window 64 can expose the substrate front cell metal layer 66 corresponding to the substrate passivation layer window 64, so as to facilitate the extraction of the substrate front cell metal layer 66 to form the source electrode of the power semiconductor device.

Further, on the cross section of the power semiconductor device, the termination region includes at least one substrate termination trench 34 and substrate termination P-type body regions 49 located on both sides of the substrate termination trench 34 . The substrate terminal P-type body region 49 is located above the corresponding groove bottoms of the substrate terminal trench 34, the first trench 33 of the substrate cell, and the second trench 67 of the substrate cell;

A substrate terminal insulating oxide layer 39 is provided on the inner sidewall and bottom wall of the substrate terminal trench 34, and the substrate terminal trench 34 provided with the substrate terminal insulating oxide layer 39 is filled with substrate terminal trench polysilicon 38, The substrate terminal trench polysilicon 38 is insulated from the inner sidewall and bottom wall of the substrate terminal trench 34 through the substrate terminal insulating oxide layer 39; the notch of the substrate terminal trench 34 is insulated by the substrate The dielectric layer 50 covers.

In the embodiment of the present invention, on the cross section of the power semiconductor device, at least one substrate termination trench 34 is provided in the termination region, and FIG. 21 shows the situation in which two substrate termination trenches 34 are provided in the termination region; Then, on the top plan view of the power semiconductor device, the two substrate termination trenches 34 are both annular in the termination region. The substrate termination P-type body region 49 runs through the termination region, so that there are substrate P-type body regions 49 on both sides of the substrate termination trench 34 , and the substrate P-type body region 49 is located at the bottom of the substrate termination trench 34 above. Generally, the depth of the substrate terminal P-type body region 49 in the semiconductor substrate 31 is the same as the depth of the substrate P-type base region 47 in the semiconductor substrate 31 .

A substrate terminal insulating oxide layer 39 is provided on the inner sidewall and the bottom wall of the substrate terminal trench 34 , and the substrate terminal trench 34 is filled with polysilicon 38 , which is filled in the substrate terminal trench 34 The substrate terminal trench polysilicon 38 is insulated from the inner sidewall and bottom wall of the filled substrate terminal trench 34 by the substrate terminal insulating oxide layer 39 in the filled substrate terminal trench 34 . After the substrate insulating dielectric layer 50 is disposed on the front surface of the semiconductor substrate 31, the substrate insulating dielectric layer 50 can cover the notch of the substrate terminal trench 34 at the same time, and at the same time, the substrate terminal trench polysilicon 38 passes through the substrate insulating dielectric layer. 50 can be insulated from the substrate front termination metal layer 55 in the termination region.

In specific implementation, the substrate terminal trench 34, the substrate cell first trench 33 and the substrate cell second trench 67 are obtained by the same process steps, so that the substrate terminal trench 34 and the substrate cell are obtained by using the same process steps. The cell first trench 33 and the substrate cell second trench 67 have the same depth within the semiconductor substrate 31 . The substrate cell insulating oxide layer 37 and the substrate terminal insulating oxide layer 39 are obtained by the same process step, and the substrate cell trench polysilicon 36 and the substrate terminal trench polysilicon 38 are obtained by the same process step.

In the embodiment of the present invention, after at least one substrate P+ implantation region 42 is arranged between the second trench 67 of the substrate cell and the terminal end, the substrate P+ implantation region 42 adjacent to the second trench 67 of the substrate cell and the The second trench 67 of the substrate cell is in contact with the outer sidewall of the adjacent terminal region. The addition of the substrate P+ implantation region 42 can alleviate the electric field concentration at the bottom of the second trench 67 of the substrate cell and the bottom of the trench 70 in the transition region at the cell edge. The electric field is concentrated, reducing the electric field strength at the bottom of the second trench 67 of the substrate cell and the electric field strength at the bottom of the trench 70 in the transition region of the cell edge, preventing trenches at the bottom of the second trench 67 of the substrate cell and the transition region of the cell edge. The bottom of the trench 70 breaks down prematurely, which fully increases the withstand voltage of the terminal region, which can reduce the junction depth requirement of the P-type body region 49 of the substrate terminal, improve the degree of freedom of design, and enable the power semiconductor device to have a higher breakdown voltage and Reliability, or under the same breakdown voltage, can further reduce the area of the device, reduce the cost, and improve the reliability of the power semiconductor device.

In addition, a substrate backside structure is provided on the backside of the semiconductor substrate 31, and the power semiconductor device can be an IGBT device or a power MOSFET device through the substrate backside structure.

In the embodiment of the present invention, the IGBT device and the power MOSFET device may adopt the same front cell structure, and only if the required substrate back surface structure is provided on the back surface of the semiconductor substrate 31, the power semiconductor device can be an IGBT device or a power MOSFET device. The specific form of forming an IGBT device or a power MOSFET device by using the backside structure of the substrate is consistent with the existing ones, which are well known to those skilled in the art, and will not be repeated here.

As shown in FIG. 22, on the cross section of the power semiconductor device, the cell region further includes a cell edge transition region trench 70, and the cell edge transition region trench 70 is located between the second trench 67 of the substrate cell and the cell edge transition region trench 70. Between the termination regions, the depth of the substrate P+ implantation region 42 in the semiconductor substrate 31 is greater than the depth of the cell edge transition region trench 70 in the semiconductor substrate 31, and the depth of the substrate cell second trench 67 The substrate P+ implantation region 42 in contact with the sidewall covers the outer sidewall of the cell edge transition region trench 70 .

The groove bottom of the cell edge transition region trench 70 is located below the substrate P-type base region 47, and the substrate cell insulating oxide layer 37 is provided on the inner sidewall and bottom wall of the cell edge transition region trench 70. The cell edge transition region trench 70 where the substrate cell insulating oxide layer 37 is provided is also filled with the substrate cell trench polysilicon 36, and the substrate cell trench polysilicon 36 passes through the cell edge transition region trench 70 The inner substrate cell insulating oxide layer 37 is insulated and isolated from the sidewall and bottom wall of the cell edge transition region trench 70 where it is located.

In the embodiment of the present invention, the cell edge transition region trench 70 is formed in the same process step as the substrate cell first trench 33 , the substrate cell second trench 67 and the substrate termination trench 34 . The transition region trench 70 has the same depth as the substrate cell first trench 33 , the substrate cell second trench 67 and the substrate termination trench 34 . The cell edge transition region trench 70 is closer to the termination region than the substrate cell second trench 67 . In the cross section of the power semiconductor device, the cell edge transition region trench 70 is located between the second trench 67 of the substrate cell and the substrate termination trench 34 of the adjacent cell region.

It can be seen from the above description that the groove bottom of the cell edge transition region trench 70 is located below the substrate P-type base region 47 and the substrate terminal P-type body region 49, but the cell edge transition region trench 70 is located at the bottom of the substrate. Above the bottom of the bottom P+ implant region 42 . In the embodiment of the present invention, the cell edge transition region trench 70 is located in the substrate P+ implantation region 42 in contact with the sidewall of the second trench 67 of the substrate cell, that is, the outer sidewall of the cell edge transition region trench 70 is The substrate P+ implant region 42 in contact with the sidewall of the second trench 67 of the substrate cell is clad. When at least one substrate P+ implantation region 42 is provided between the second trench 67 of the substrate cell and the termination region, the cell edge transition region trench 70 will only be in contact with the sidewall of the second trench 67 of the substrate cell The P+ implantation region 42 of the substrate. For the case where multiple substrate P+ implant regions 42 are present, adjacent substrate P+ implant regions 42 are separated by substrate termination P-type body regions 49 .

In FIG. 22 , the substrate P+ implantation region 42 in contact with the sidewall of the second trench 67 of the substrate cell also covers the bottom wall of the cell edge transition region trench 70 . In specific implementation, when preparing the substrate P+ implantation region 42, according to the implantation energy of the P-type impurity ions and the annealing temperature, the substrate P+ implantation region 42 can cover the outer sidewall of the cell edge transition region trench 70, or At the same time, the bottom wall of the cell edge transition region trench 70 can be covered. Regardless of whether the substrate P+ implantation region 42 covers the bottom wall of the cell edge transition region trench 70 or not, the junction depth of the substrate P+ implantation region 42 in the semiconductor substrate 31 must be greater than that of the first trench 33 and the lining of the substrate cell. The depths of the bottom cell second trench 67 and the cell edge transition region trench 70, that is, the substrate P+ implantation region 42 at the bottom of the semiconductor substrate 31 is located in the substrate cell first trench 33, the substrate cell No. The two trenches 67 and the cell edge transition region trenches 70 are below the trench bottom.

When there are multiple substrate P+ implanted regions 42 , the cell edge transition region trench 70 is only within the substrate P+ implanted region 42 in contact with the outer sidewalls of the second trench 67 of the substrate cell. In addition, there may also be a plurality of cell edge transition region trenches 70 in the substrate P+ implantation region 42 in contact with the outer sidewall of the second trench 67 of the substrate cell, and between adjacent cell edge transition region trenches 70 Spaced by substrate P+ implant regions 42 .

It can be seen from the above description that the cell edge transition region trench 70 cannot form a conductive channel, and will not affect the specific functions of the substrate cell first trench 33 and the substrate cell second trench 67 .

As shown in FIG. 11 to FIG. 21 , the above-mentioned power semiconductor device can be prepared by the following process steps. Specifically, the preparation method includes the following steps:

Step 1. Provide a semiconductor substrate 31 with an N conductivity type, and perform required trench etching on the front surface of the semiconductor substrate 31 to obtain the first substrate cell in the cell area of the semiconductor substrate 31. a trench 33 and a second trench 67 in the substrate cell, the second trench 67 in the substrate cell is adjacent to the terminal region within the cell region;

As shown in FIG. 11 , the semiconductor substrate 31 can be made of conventional semiconductor materials, such as silicon, etc. For an N-type power semiconductor device, the conductivity type of the semiconductor substrate 31 is N-type. When trench etching is performed on the semiconductor substrate 31, it is necessary to coat the front surface of the semiconductor substrate 31 to obtain the substrate first photoresist layer 32, and then use the substrate first mask 69 to etch the substrate first photoresist layer 32. The photoresist layer 32 is subjected to photolithography to pattern the substrate first photoresist layer 32 to obtain a substrate first photoresist layer window 36 penetrating the substrate first photoresist layer 32 .

After the first substrate photoresist layer window 36 is obtained, the semiconductor substrate 31 is etched by using the substrate first photoresist layer 32 and the substrate first photoresist layer window 36 to obtain the substrate cell The first trench 33 and the second trench 67 in the substrate cell, wherein the first trench 33 in the substrate cell and the second trench 67 in the substrate cell correspond to the first photoresist layer window 36 in the substrate.

In addition, when the terminal region also adopts the trench structure, the substrate terminal trench 34, the substrate terminal trench 34, the first trench 33 of the substrate cell and the second trench 67 of the substrate cell can also be obtained at the same time. have the same depth. The number of substrate termination trenches 34 in the termination region can be selected as required. The cross-sectional view of FIG. 11 shows a situation in which two substrate termination trenches 34 are provided in the middle termination region. Similarly, the number of the first trenches 33 in the substrate cell in the cell area can also be selected according to actual needs, but in the cross-sectional view, the first trenches 33 in the substrate cell adjacent to the terminal area and the adjacent cell area There is only one substrate cell second trench 67 between the substrate termination trenches 34 .

Specifically, the process and process conditions of etching the semiconductor substrate 31 to obtain the first trench 33 of the substrate cell, the second trench 67 of the substrate cell and the terminal trench 34 of the substrate can be realized by using the existing common technology. , which is well known to those skilled in the art. The first trench 33 of the substrate cell, the second trench 67 of the substrate cell, and the notch of the substrate terminal trench 34 are all located on the front side of the semiconductor substrate 34. After obtaining the first trench 33 of the substrate cell The second trench 67 of the substrate cell and the notch of the substrate terminal trench 34 are located behind the semiconductor substrate 34, and the first photoresist layer 32 of the substrate needs to be removed by technical means commonly used in the art.

In order to obtain the structure shown in FIG. 22, when performing trench etching, the cell edge transition region trench 70 can also be obtained, that is, the cell edge transition region trench 70 and the substrate cell first trench 33, the lining The bottom cell second trench 67 and the substrate termination trench 34 are prepared in the same process step and have the same depth.

Step 2. Set the substrate cell insulating oxide layer 37 in the above-mentioned first trench 33 of the substrate cell and the second trench 67 of the substrate cell, and set the substrate cell insulating oxide layer 37 in the first trench 33 of the substrate cell and the substrate cell. The cell second trench 67 is also filled with the substrate cell trench polysilicon 36; the substrate cell insulating oxide layer 37 covers the substrate cell first trench 33 and the substrate cell second trench 67 Corresponding side walls and bottom walls;

The substrate cell trench polysilicon 36 filled in the first trench 33 of the substrate cell passes through the substrate cell insulating oxide layer 37 in the filled substrate cell first trench 33 and the filled substrate cell. The sidewall and bottom wall of the first trench 33 are insulated and isolated, and the substrate cell trench polysilicon 36 filled in the substrate cell second trench 67 passes through the filled substrate cell second trench 67. The substrate cell insulating oxide layer 37 is insulated and isolated from the sidewall and bottom wall of the filled second trench 67 of the substrate cell;

As shown in FIG. 12 , using the thermal oxidation process, the substrate cell insulating oxide layer 37 can be grown in the first trench 33 of the substrate cell and the second trench 67 of the substrate cell. A substrate terminal insulating oxide layer 39 is grown in the terminal trench 34 .

After the substrate cell insulating oxide layer 37 and the substrate terminal insulating oxide layer 39 are obtained, polysilicon material is deposited to obtain the first trench 33 and the second trench 67 filled in the substrate cell. At the same time, the substrate terminal trench polysilicon 38 filled in the substrate terminal trench 34 can be obtained.

After the cell edge transition region trench 70 is obtained, the substrate cell insulating oxide layer 37 can be grown on the inner sidewall and bottom wall of the cell edge transition region trench 70, and the cell edge transition region trench can be grown on the cell edge transition region trench 70. 70 is filled to obtain the substrate cell trench polysilicon 36, and the substrate cell trench polysilicon 36 in the cell edge transition region trench 70 passes through the substrate cell insulating oxide layer 37 in the cell edge transition region trench 70 It is insulated and isolated from the inner sidewall and bottom wall of the cell edge transition region trench 70 .

Step 3. Prepare a substrate P-type base region 47, a substrate N+ source region 48 and at least one substrate P+ implantation region 42 in the semiconductor substrate 31; wherein, the substrate P-type base region 47 is located in the first substrate cell The trench 33 and the second trench 67 of the substrate cell are above the corresponding groove bottoms, the substrate N+ source region 48 is located above the substrate P-type base region 47, and the substrate P+ injection region 42 is located above the second trench of the substrate cell 67 and the terminal region, the depth of the substrate P+ implantation region 42 in the semiconductor substrate 31 is greater than the depths of the first trench 33 of the substrate cell and the second trench 67 of the substrate cell in the semiconductor substrate 31;

The substrate P+ implantation region 42 adjacent to the second trench 67 of the substrate cell is in contact with the sidewall of the second trench 67 of the substrate cell adjacent to the termination region, and the second trench 67 of the substrate cell is adjacent to the first trench 67 of the substrate cell. The sidewalls of a trench 33 are in contact with the substrate P-type base region 47 and the substrate N+ source region 48, and the two sidewalls of the first trench 33 in the substrate cell are in contact with the corresponding substrate P-type base region 47 and the substrate respectively. Bottom N+ source region 48 contacts;

In the embodiment of the present invention, the specific process for preparing the substrate P-type base region 47 , the substrate N+ source region 48 , the substrate P+ injection region 42 and the substrate terminal P-type body region 49 can be realized by different processes. You can choose according to actual needs. The specific process is described below.

As shown in Figure 13, Figure 14, Figure 15 and Figure 16, step 3 specifically includes the following steps:

Step 3.1. Implantation of P-type impurity ions is performed above the front surface of the semiconductor substrate 31 to prepare at least one substrate P+ between the second trench 67 of the substrate cell and the substrate terminal trench 34 adjacent to the cell region The implanted region 42, and the substrate P+ implanted region 42 adjacent to the second trench 67 of the substrate cell is in contact with the sidewall of the second trench 67 of the substrate cell adjacent to the termination region. The substrate P+ implanted region 42 is in the semiconductor The depth in the substrate 31 is greater than the depths of the first trench 33 in the substrate cell, the second trench 67 in the substrate cell and the substrate terminal trench 34 in the semiconductor substrate 31;

As shown in FIG. 13 , the second photoresist layer 40 of the substrate is obtained by coating the front surface of the semiconductor substrate 31 , and the second photoresist layer 40 of the substrate is photoetched by using the second reticle to obtain a through-hole The substrate second photoresist layer window 41 of the substrate second photoresist layer 40 . Specifically, the second photoresist layer window 41 of the substrate is between the second trench 67 of the substrate cell and the substrate terminal trench 34 adjacent to the cell region.

After the second photoresist layer window 41 of the substrate is obtained, the semiconductor substrate 31 is shielded by the second photoresist layer 40 of the substrate, and the implantation of P-type impurity ions is performed on the top of the semiconductor substrate 31. The type of ion can be selected as required, which is well known to those skilled in the art. After the P-type impurity ion implantation is performed, a well push is performed to obtain a substrate P+ implantation region 42 , and the substrate P+ implantation region 42 is directly corresponding to the window 41 of the second photoresist layer of the substrate. On the top view plane after the process, the obtained substrate P+ implantation region 42 is annular, and the number of the substrate P+ implantation region 42 can be selected according to actual needs.

Specifically, the substrate P+ implantation region 42 adjacent to the second trench 67 of the substrate cell is in contact with the sidewall of the second trench 67 of the substrate cell adjacent to the termination region, and the substrate P+ implantation region 42 is in the semiconductor substrate The depth inside 31 is greater than the depths of the first trench 33 in the substrate cell, the second trench 67 in the substrate cell, and the substrate terminal trench 34 in the semiconductor substrate 31; that is, the bottom of the substrate P+ implantation region 42 is located at Below the second trench 67 of the substrate cell. After the substrate P+ implantation region 42 is prepared, the second photoresist layer 40 of the substrate is removed from the front surface of the semiconductor substrate 31 using technical means commonly used in the art.

In the embodiment of the present invention, after the substrate P+ implantation region 42 is prepared, the substrate P+ implantation region 42 that is in contact with the sidewall of the second trench 67 of the substrate cell adjacent to the terminal region can realize the cell edge transition region trench 70 wrapping, that is, the substrate P+ implantation region 42 can wrap the outer sidewall and bottom wall of the cell edge transition region trench 70, as shown in FIG. 22 .

Step 3.2, perform P-type impurity ion implantation on the front surface of the above-mentioned semiconductor substrate 31 again to obtain a substrate P-type layer 43 penetrating the semiconductor substrate 31, and the substrate P-type layer 43 is located in the first groove of the substrate cell Above the groove 33, the second groove 67 of the substrate cell and the corresponding groove bottom of the substrate terminal groove 34;

As shown in FIG. 14 , P-type impurity ion implantation is performed again on the front surface of the semiconductor substrate 31 to obtain a substrate P-type layer 43 penetrating the semiconductor substrate 31 , wherein the substrate P-type layer 43 is formed from the semiconductor substrate 31 . The front side of the substrate P-type layer 43 extends vertically downward, and the bottom of the substrate P-type layer 43 is located above the corresponding groove bottoms of the substrate cell first trench 33 , the substrate cell second trench 67 and the substrate terminal trench 34 . The doping concentration of the substrate P-type layer 43 is lower than the doping concentration of the substrate P+ implantation region 42 .

Step 3.3, perform N-type impurity ion implantation and P-type impurity ion implantation on the above-mentioned semiconductor substrate 31, and use the implanted P-type impurity ions and the substrate P-type layer 43 in the cell area to obtain a result located in the cell area. The substrate P-type base region 47 can be obtained by using the implanted N-type impurity ions to obtain the substrate N+ source region 48 located above the substrate P-type base region 47. The substrate N+ source region 48 and the substrate P-type base region 48 At the same time, the substrate terminal P-type body region 49 can be obtained by using the substrate P-type layer 43 in the terminal region.

As shown in FIG. 15 , the third photoresist layer 44 of the substrate is obtained by coating the front surface of the semiconductor substrate 31 first, and then the third photoresist layer 44 of the substrate is subjected to photolithography by using the third substrate mask 45 , so as to obtain a third substrate photoresist layer window 46 penetrating the substrate third photoresist layer 44 , and through the substrate third photoresist layer window 46 , the corresponding area in the cell area can be exposed. In FIG. 15 , part of the substrate P+ implantation region 42 that is in contact with the sidewall of the second trench 67 of the substrate cell is exposed. Of course, in the specific implementation, the substrate element can be protected by the third photoresist layer 44 of the substrate. The second trench 67 and all the substrate P+ implantation regions 42 are shielded.

After obtaining the third substrate photoresist layer window 46, the substrate third photoresist layer 44 and the substrate third photoresist layer window 46 are used to carry out N-type impurity ions and P-type impurity ions above the front surface of the semiconductor substrate 31. Impurity ions are implanted, and the well is pushed after the implantation. Using the implanted P-type impurity ions and the substrate P-type layer 43 in the cell region, the substrate P-type base region 47 in the cell region can be obtained. The N-type impurity ions can obtain the substrate N+ source region 48 located above the substrate P-type base region 47, and the substrate N+ source region 48 is adjacent to the substrate P-type base region 47; Bottom P-type layer 43 enables substrate termination P-type body region 49 . In the embodiment of the present invention, the doping concentration of the substrate P-type base region 47 is greater than the doping concentration of the terminal P-type body region 49 , that is, the substrate P-type layer 43 is not implanted with P-type impurity ions and N-type impurity ions. The regions can form substrate termination P-type body regions 49 . The depth of the substrate P-type base region 47 in the semiconductor substrate 31 corresponds to the depth of the substrate terminal P-type body region 49 .

When there is a part of the substrate P+ implantation region 42 in contact with the sidewall of the second trench 67 of the substrate cell that is not shielded by the third photoresist layer 44 of the substrate, after N-type impurity ions and P-type impurity ions are implanted , the substrate P-type base region 47 and the substrate N+ source region 48 in contact with the substrate P+ implantation region 42 can be obtained. For the substrate P+ implantation region 42 in contact with the sidewall of the second trench 67 in the substrate cell, the substrate P-type base region 47 and the substrate N+ source region 48 in contact with the substrate P+ implantation region 42 are also in contact with the substrate. The bottom cell second trench 67 contacts the outer wall adjacent to the termination region. When the substrate P+ implantation region 42 is completely shielded by the substrate third photoresist layer 44, the substrate P+ implantation region 42 will not be affected during the N-type impurity ion and P-type impurity ion implantation. In FIG. 16 , the case where a substrate P-type base region 47 and a substrate N+ source region 48 are formed on the substrate P+ implantation region 42 is shown. It can be seen from the above description that when there are multiple substrate P+ implantation regions 42 between the second trench 67 of the substrate cell and the substrate terminal trench 34 of the adjacent cell region, the adjacent substrate P+ implantation regions 42 are formed by the substrate P+ implantation region 42. Bottom terminal P-type body regions 49 are spaced apart, and substrate P+ implant regions 42 are in contact with substrate terminal P-type body regions 49 through the spacers. In FIG. 16 , for the case where there is only one substrate P+ implantation region 42 , the substrate P+ implantation region 42 is in contact with the substrate terminal P-type body region 49 . In FIG. 22, the cell edge transition region trench 70 is located in the substrate P+ implant region 42 in contact with the second trench 67 of the substrate cell, and the second trench 67 in the substrate cell is adjacent to the outer sidewall of the termination region Also in contact with the substrate P-type base region 47 and the substrate N+ source region 48 .

In the above process, after the N-type impurity ions and the P-type impurity ions are carried out, after the required annealing process, the substrate P-type base region 47 and the substrate N+ source region 48 can be simultaneously formed. Specifically, the process of ion implantation is carried out. And the annealing process is consistent with the prior art, and the specific process is well known to those skilled in the art, and will not be repeated here. In addition, since the annealing temperature of N+ cannot be too high, during annealing, the well push depth of the P-type base region 47 of the substrate will be limited.

In order to improve the push-well depth of the P-type base region 47 of the substrate, a substrate transition medium layer can be deposited on the front side of the semiconductor substrate 31, and a transition medium layer photoresist layer can be coated on the substrate transition medium layer. The transition medium layer reticle photolithography the transition medium layer photoresist layer to obtain a patterned transition medium layer photoresist layer. Using the patterned photoresist layer of the transition medium layer, the substrate transition medium layer is etched to obtain a substrate transition medium layer window penetrating the substrate transition medium layer. After the substrate transition medium layer window is obtained, P-type impurity ion implantation is performed on the front surface of the semiconductor substrate 31, and after the P-type impurity ion implantation, the photoresist layer of the transition medium layer is removed and the thermal well push is performed to obtain the substrate In the P-type base region 47, at this time, the obtained junction depth of the substrate P-type base region 47 is greater than the junction depth obtained by the above process. After the P-type base region 47 of the substrate is obtained, N-type impurity ion implantation is performed on the front surface of the semiconductor substrate 31 by using the substrate transition medium layer, and after the N-type impurity ion implantation, thermal push well is performed to obtain the substrate N+ source region 48 . After the substrate N+ source region 48 is obtained, the substrate transition medium layer is removed from the semiconductor substrate 31; of course, the substrate transition medium layer can also be retained according to actual needs, as long as the substrate transition medium layer does not affect the prepared power semiconductor The device is sufficient, and the details are familiar to those skilled in the art, and details are not repeated here.

In specific implementation, the conditions for implanting P-type impurity ions, the implantation conditions for N-type impurity ions, the process of thermally pushing the well after P-type impurity ion implantation, and the process of thermally pushing the well after N-type impurity ion implantation are all the same as those of the prior art. Consistent, if you can refer to the technical solution disclosed in Publication No. CN110047757A, the specific process conditions and processes are well known to those skilled in the art, and will not be repeated here.

In addition, other processes can also be used to prepare the substrate P-type base region 47, the substrate N+ source region 48, the substrate P+ injection region 42 and the substrate terminal P-type body region 49; thus, step 3 specifically includes the following step:

Step 3.a, perform P-type impurity ion implantation on the front surface of the above-mentioned semiconductor substrate 31 to obtain a substrate P-type layer 43 penetrating the semiconductor substrate 31, and the substrate P-type layer 43 is located in the first cell of the substrate. Above the trench 33, the second trench 67 of the substrate cell and the corresponding trench bottom of the substrate terminal trench 34;

In the embodiment of the present invention, the implantation of P-type impurity ions is performed by using technical means commonly used in the technical field, so as to obtain the substrate P-type layer 43 penetrating the semiconductor substrate 31 . Extend vertically downwards. The substrate P-type layer 43 is located above the first trench 33 of the substrate cell, the second trench 67 of the substrate cell and the corresponding bottom of the substrate terminal trench 34 .

In step 3.b, the implantation of P-type impurity ions is performed again above the front surface of the upper semiconductor substrate 31 to prepare at least One substrate P+ implanted region 42, and the substrate P+ implanted region 42 adjacent to the second trench 67 of the substrate cell is in contact with the sidewall of the second trench 67 of the substrate cell adjacent to the termination region, the substrate P+ implanted The depth of the region 42 in the semiconductor substrate 31 is greater than the depths of the substrate cell first trench 33, the substrate cell second trench 67 and the substrate termination trench 34 in the semiconductor substrate;

In the embodiment of the present invention, after the substrate P-type layer 43 is obtained, a substrate-implanted photoresist layer is obtained by coating the front surface of the semiconductor substrate 31, and the substrate-implanted photoresist layer mask is used to inject the substrate into the substrate. The photoresist layer is subjected to photolithography to obtain a patterned substrate implanted into the photoresist layer. The substrate P+ implantation region 42 is prepared by implanting P-type impurity ions into the photoresist layer. The doping concentration of the substrate P+ implantation region 42 is greater than that of the substrate P-type layer 43 . After obtaining the substrate P+ implanted region 42, a form consistent with that of FIG. 14 can be obtained.

Step 3.c, perform N-type impurity ion implantation and P-type impurity ion implantation on the above-mentioned semiconductor substrate 31, and use the implanted P-type impurity ions and the substrate P-type layer 43 in the cell area to obtain the P-type impurity ions located in the cell. The substrate P-type base region 47 within the region can be obtained by using the implanted N-type impurity ions to obtain the substrate N+ source region 48 located above the substrate P-type base region 47. The substrate N+ source region 48 is connected to the substrate P-type The base region 47 is adjacent; at the same time, the substrate termination P-type body region 49 can be obtained by using the substrate P-type layer 43 in the termination region.

Specifically, the processes shown in FIG. 15 and FIG. 16 can be used to prepare the substrate P-type base region 47, the substrate N+ source region 48 and the substrate terminal P-type body region 49. For details, please refer to the above description, which is not repeated here. Repeat.

Compared with the process of FIG. 13 to FIG. 16 , in the process of step 3.a to step 3.c, only the substrate P-type layer 43 is prepared first, and then the substrate P+ implantation region 42 is prepared, and the rest of the process is performed. All are consistent with steps 3.1 to 3.3. For details, please refer to the above description, which will not be described in detail here. In addition, in the process of step 3.a to step 3.c, for the condition of the trench 70 in the cell edge transition region, reference may be made to the corresponding description in the above step 3.1 to step 3.3, which will not be repeated here.

Step 4: Perform dielectric layer deposition on the front surface of the semiconductor substrate 31 to obtain a substrate insulating dielectric layer 50 covering the front surface of the semiconductor substrate 31; perform contact hole etching on the substrate insulating dielectric layer 50 to obtain a through liner the substrate source contact hole 54 of the bottom insulating dielectric layer 50;

Specifically, the substrate insulating dielectric layer 50 is a silicon dioxide layer. Specifically, the substrate insulating dielectric layer 50 can be deposited by using technical means commonly used in the technical field. The substrate insulating dielectric layer 50 covers the front surface of the semiconductor substrate 31 .

In order to obtain the substrate source contact hole 54, it is necessary to coat the substrate insulating medium layer 50 to obtain the substrate fourth photoresist layer 51, and use the substrate fourth mask to apply the substrate fourth photoresist layer 51 to the substrate. Photolithography is performed to obtain a fourth substrate photoresist layer window 53 penetrating the substrate fourth photoresist layer 51, so as to realize the required patterning of the substrate fourth photoresist layer 51, as shown in FIG. 17 shown.

The substrate insulating dielectric layer 50 is etched by using the fourth substrate photoresist layer 51 and the fourth substrate photoresist layer window 53 to obtain the substrate source contact hole 54 . In FIG. 18 , the substrate source contact holes 54 are located on both sides of the first trench 33 of the substrate cell, and the second trench 67 of the substrate cell is located on one side of the substrate cell adjacent to the termination region. The substrate source contact hole 54 penetrates through the substrate insulating medium layer 50; for the substrate source contact hole 54 on both sides of the first trench 33 of the substrate cell, the bottom of the substrate source contact hole 54 and the lining The bottom P-type base region 47 corresponds to the substrate source contact hole 54 on the outside of the second trench 67 of the substrate cell corresponds to the substrate P+ implantation region 42 . When the outer sidewall of the second trench 67 of the substrate cell adjacent to the termination region is in contact with the substrate P-type base region 47 and the substrate N+ source region 48, the substrate source outside the second trench 67 of the substrate cell The contact hole 54 needs to correspond to the substrate P-type base region 47 and the substrate N+ source region 48 .

Step 5. Perform metal deposition on the front side of the above-mentioned semiconductor substrate 31 to obtain a front side metal layer of the substrate. The front side metal layer of the substrate covers the insulating dielectric layer 50 of the substrate. After etching the front side metal layer of the substrate , the substrate front cell metal layer 66 and the substrate front terminal metal layer 55 can be obtained, the substrate front cell metal layer 66 and the substrate front terminal metal layer 55 are covered on the substrate insulating medium layer 50, and the substrate front The cell metal layer 66 is also filled in the substrate source contact hole 54; the substrate front cell metal layer 66 and the substrate P-type base region 47 and the substrate N+ source region filled in the substrate source contact hole 54 48 and the ohmic contact of the substrate P+ implantation region 42 in contact with the sidewall of the second trench 67 of the substrate cell;

Specifically, a metal layer on the front side of the substrate is deposited by using technical means commonly used in the technical field. The metal layer on the front side of the substrate covers the insulating dielectric layer 50 of the substrate, and also fills the source contact hole 54 of the substrate. The fifth photoresist layer 56 of the substrate is obtained by coating the metal layer on the front side of the substrate, and the fifth photoresist layer 56 of the substrate is photoetched by using the fifth mask plate 57 of the substrate, so as to obtain the fifth photoresist layer penetrating the substrate. The substrate fifth photoresist layer window 58 of the resist layer 56 is used to realize patterning of the substrate fifth photoresist layer 56 .

The metal layer on the front side of the substrate is etched by using the fifth photoresist layer 56 of the substrate and the window 58 of the fifth photoresist layer of the substrate to obtain a window 59 of the metal layer on the front side of the substrate penetrating the metal layer on the front side of the substrate. The bottom front metal layer window 59 can divide the substrate front metal layer to obtain the substrate front cell metal layer 66 and the substrate front terminal metal layer 55; wherein, the substrate front cell metal layer 66 is also filled in the substrate source contact Inside the hole 54; the substrate front cell metal layer 66 and the substrate P-type base region 47, the substrate N+ source region 48 and the second trench 67 side of the substrate cell filled in the substrate source contact hole 54 The wall-contacted substrate P+ implanted regions 42 are ohmic contacts.

For the second trench 67 in the substrate cell, the sidewall of the second trench 67 in the substrate cell adjacent to the terminal region is in contact with the substrate P-type base region 47, the substrate N+ source region 48 and the substrate P+ implantation region 42 At this time, the cell metal layer 66 on the front side of the substrate needs to be adjacent to the substrate P-type base region 47, the substrate N+ source region 48 and the substrate P+ implantation region 42 of the second trench 67 of the substrate cell adjacent to the sidewall of the terminal region. Ohmic contact, as shown in Figure 19. When the sidewall of the second trench 67 of the substrate cell adjacent to the terminal region only contacts the substrate P+ implantation region 42, the metal layer 66 of the substrate front cell directly contacts the sidewall of the second trench 67 of the substrate cell The substrate P+ implanted region 42 is in ohmic contact.

After the cell metal layer 66 on the front side of the substrate and the terminal metal layer 65 on the front side of the substrate are obtained, the fifth photoresist layer 56 of the substrate needs to be removed, and the terminal metal layer 65 on the front side of the substrate is located above the terminal area.

In addition, when the metal layer on the front side of the substrate is etched, a gate metal can be obtained. The gate metal is in 36 ohm contact with the substrate cell trench polysilicon, and the gate electrode of the power semiconductor device can be formed by using the gate metal.

Step 6: Deposition a passivation layer on the front side of the above-mentioned semiconductor substrate 31 to obtain a substrate metal passivation layer 60, the substrate metal passivation layer 60 covers the front cell metal layer 66 and the substrate On the front terminal metal layer 55, and the substrate metal passivation layer 60 can be used to space the substrate front cell metal layer 66 and the substrate front terminal metal layer 55;

Specifically, the passivation layer is deposited by using technical means commonly used in the technical field to obtain the substrate metal passivation layer 60. The substrate metal passivation layer 60 can be filled in the metal layer window 59 on the front side of the substrate, so as to realize The cell metal layer 66 on the front side of the substrate is separated from the terminal metal layer 55 on the front side of the substrate.

Step 7: Etch the above-mentioned base metal passivation layer 60 to obtain a base metal passivation layer window 64 penetrating the base metal passivation layer. Through the base metal passivation layer window 64, it can be The front cell metal layer 66 of the substrate corresponding to the bottom metal passivation layer window 64 is exposed;

Specifically, the sixth substrate photoresist layer 61 is obtained by coating the substrate metal passivation layer 60, and the sixth substrate photoresist layer 61 is photoetched by using the substrate sixth mask 62 to obtain a through The substrate sixth photoresist layer window 63 of the substrate sixth photoresist layer 61 . The substrate metal passivation layer 60 is etched by using the substrate sixth photoresist layer 61 and the substrate sixth photoresist layer window 63 to obtain the substrate metal passivation layer window 64, and the substrate metal passivation The layer window 64 is located in the cell region, and through the substrate metal passivation layer window 64, the cell metal layer 66 on the front side of the substrate corresponding to the substrate metal passivation layer window 64 can be exposed, as shown in FIG. 20; The bottom metal passivation layer window 64 can easily lead out the cell metal layer 66 on the front side of the substrate.

After the substrate metal passivation layer window 64 is obtained, the substrate sixth photoresist layer 61 needs to be removed from the substrate metal passivation layer 60 to complete the front-side process of the power semiconductor device, as shown in FIG. 21 .

Step 8. Perform a required backside process on the backside of the semiconductor substrate 31 to obtain a required substrate backside structure on the backside of the semiconductor substrate.

In the embodiment of the present invention, according to the type of the power semiconductor device to be prepared, the required backside process is performed to obtain the backside structure of the substrate. The specific backside process and the specific form of the backside structure of the substrate can be selected as required. The details are well known to those skilled in the art and will not be repeated here.

Claims (10)

1. A low-cost high-performance groove type power semiconductor device comprises a semiconductor substrate with a first conduction type, a cellular region arranged in the central region of the semiconductor substrate, and a terminal region arranged on the semiconductor substrate and positioned at the outer ring of the cellular region; the cells in the cell area adopt a groove structure; the method is characterized in that:

on the top plan of the power semiconductor device, the unit cells of the unit cell area comprise annular substrate unit cell second grooves and a plurality of substrate unit cell first grooves positioned at the inner rings of the annular substrate unit cell second grooves, and the terminal area is positioned at the outer rings of the annular substrate unit cell second grooves;

on the cross section of the power semiconductor device, a substrate second conduction type base region and a substrate first conduction type source region are arranged on two sides of a substrate cell first groove, the substrate second conduction type base region is located above the corresponding groove bottoms of the substrate cell first groove and the substrate cell second groove, and the substrate second conduction type base region and the substrate first conduction type source region are in contact with the corresponding side walls of the adjacent substrate cell first groove;

on the cross section of the power semiconductor device, the outer side wall of a substrate cell second groove adjacent to a substrate cell first groove is contacted with a corresponding substrate second conduction type base region and a substrate first conduction type source region, at least one substrate second conduction type injection region is arranged between the side wall of the substrate cell second groove adjacent to a terminal region and the terminal region, the outer side wall of the substrate cell second groove adjacent to the terminal region is contacted with an adjacent substrate second conduction type injection region, and the depth of the substrate second conduction type injection region in a semiconductor substrate is greater than the depth of the substrate cell first groove and the substrate cell second groove in the semiconductor substrate;

and arranging a substrate front cell metal layer above the front surface of the semiconductor substrate, wherein the substrate front cell metal layer can be in ohmic contact with the substrate second conduction type base region, the substrate first conduction type source region and the substrate second conduction type injection region which is in contact with the side wall of the substrate cell second groove.

2. The low-cost high-performance trench power semiconductor device according to claim 1, wherein: substrate cell insulating oxide layers cover the corresponding inner side walls and the bottom walls of the first substrate cell grooves and the second substrate cell grooves, and substrate cell groove polycrystalline silicon is filled in the first substrate cell grooves and the second substrate cell grooves; the substrate cell groove polysilicon filled in the substrate cell first groove is insulated and isolated from the inner side wall and the bottom wall of the filled substrate cell first groove through a substrate cell insulation oxidation layer in the filled substrate cell first groove, and the substrate cell groove polysilicon filled in the substrate cell second groove is insulated and isolated from the inner side wall and the bottom wall of the filled substrate cell second groove through a substrate cell insulation oxidation layer in the filled substrate cell second groove;

the notches corresponding to the first groove and the second groove of the substrate unit cell are covered by a substrate insulating medium layer covering the front surface of the semiconductor substrate, and the substrate unit cell groove polycrystalline silicon in the first groove of the substrate unit cell and the substrate unit cell groove polycrystalline silicon in the second groove of the substrate unit cell can be insulated and isolated from the cell metal layer on the front surface of the substrate through the substrate insulating medium layer.

3. The low-cost high-performance trench power semiconductor device according to claim 2, wherein: the substrate front side cell metal layer is supported on the substrate insulating medium layer, a substrate front side terminal metal layer is further arranged on the substrate insulating medium layer, the substrate front side terminal metal layer and the substrate front side cell metal layer are separated through a substrate metal passivation layer, and the substrate metal passivation layer is supported on the substrate front side terminal metal layer and the substrate front side cell metal layer;

the substrate passivation layer window penetrates through the substrate metal passivation layer, and the substrate front cell metal layer corresponding to the substrate passivation layer window can be exposed through the substrate passivation layer window.

4. The low-cost high-performance trench power semiconductor device according to claim 1, wherein: on the cross section of the power semiconductor device, the terminal area comprises at least one substrate terminal groove and substrate terminal second conduction type body areas positioned on two sides of the substrate terminal groove, and the substrate terminal second conduction type body areas are positioned above the groove bottoms corresponding to the substrate terminal groove, the substrate cellular first groove and the substrate cellular second groove;

arranging substrate terminal insulating oxide layers on the side wall and the bottom wall of the substrate terminal groove, filling substrate terminal groove polycrystalline silicon in the substrate terminal groove provided with the substrate terminal insulating oxide layers, and insulating and isolating the substrate terminal groove polycrystalline silicon from the side wall and the bottom wall of the substrate terminal groove through the substrate terminal insulating oxide layers; and the notch of the substrate terminal groove is covered by a substrate insulating medium layer.

5. The low-cost high-performance trench power semiconductor device according to claim 1, wherein: on the cross section of the power semiconductor device, a cell edge transition region groove is further included in the cell region, the cell edge transition region groove is located between a substrate cell second groove and a terminal region, the depth of a substrate second conduction type injection region in the semiconductor substrate is larger than that of the cell edge transition region groove in the semiconductor substrate, and the substrate second conduction type injection region in contact with the side wall of the substrate cell second groove wraps the outer side wall of the cell edge transition region groove;

the bottom of the cell edge transition region groove is located below the substrate second conduction type base region, substrate cell insulating oxide layers are arranged on the inner side wall and the bottom wall of the cell edge transition region groove, substrate cell groove polycrystalline silicon is filled in the cell edge transition region groove provided with the substrate cell insulating oxide layers, and the substrate cell groove polycrystalline silicon is insulated and isolated from the side wall and the bottom wall of the cell edge transition region groove through the substrate cell insulating oxide layers in the cell edge transition region groove.

6. A preparation method of a low-cost high-performance groove type power semiconductor device is characterized by comprising the following steps:

step 1, providing a semiconductor substrate with a first conductive type, and carrying out required groove etching on the front surface of the semiconductor substrate to obtain a first groove of a substrate cellular and a second groove of the substrate cellular in a cellular area of the semiconductor substrate, wherein the second groove of the substrate cellular is adjacent to a terminal area;

step 2, arranging substrate cell insulating oxide layers in the substrate cell first grooves and the substrate cell second grooves, and filling substrate cell groove polycrystalline silicon in the substrate cell first grooves and the substrate cell second grooves; covering the corresponding side walls and bottom walls of the first grooves and the second grooves of the substrate unit cells on the substrate unit cell insulating oxide layer;

the substrate cell groove polysilicon filled in the substrate cell first groove is insulated and isolated from the side wall and the bottom wall of the filled substrate cell first groove through a substrate cell insulation oxidation layer in the filled substrate cell first groove, and the substrate cell groove polysilicon filled in the substrate cell second groove is insulated and isolated from the side wall and the bottom wall of the filled substrate cell second groove through a substrate cell insulation oxidation layer in the filled substrate cell second groove;

step 3, preparing a substrate second conductive type base region, a substrate first conductive type source region and at least one substrate second conductive type injection region in the semiconductor substrate; the substrate second conduction type base region is positioned above the corresponding groove bottoms of the substrate cell first groove and the substrate cell second groove, the substrate first conduction type source region is positioned above the substrate second conduction type base region, the substrate second conduction type injection region is positioned between the substrate cell second groove and the terminal region, and the depth of the substrate second conduction type injection region in the semiconductor substrate is greater than that of the substrate cell first groove and the substrate cell second groove in the semiconductor substrate;

the substrate second conduction type injection region adjacent to the substrate cell second groove is contacted with the outer side wall of the substrate cell second groove adjacent to the terminal region, the outer side wall of the substrate cell second groove adjacent to the substrate cell first groove is contacted with the substrate second conduction type base region and the substrate first conduction type source region, and the outer side wall of the substrate cell first groove is contacted with the corresponding substrate second conduction type base region and the substrate first conduction type source region;

step 4, carrying out dielectric layer deposition on the front surface of the semiconductor substrate to obtain a substrate insulating dielectric layer covering the front surface of the semiconductor substrate; etching a contact hole on the substrate insulating medium layer to obtain a substrate source contact hole penetrating through the substrate insulating medium layer;

step 5, performing metal deposition on the front surface of the semiconductor substrate to obtain a substrate front surface metal layer, wherein the substrate front surface metal layer covers the substrate insulating medium layer, the substrate front surface cellular metal layer and the substrate front surface terminal metal layer can be obtained after etching the substrate front surface metal layer, the substrate front surface cellular metal layer and the substrate front surface terminal metal layer cover the substrate insulating medium layer, and the substrate front surface cellular metal layer is also filled in the substrate source electrode contact hole; the substrate front cell metal layer filled in the substrate source electrode contact hole is in ohmic contact with the substrate second conduction type base region, the substrate first conduction type source region and the substrate second conduction type injection region in contact with the side wall of the substrate cell second groove;

step 6, carrying out passivation layer deposition on the front surface of the semiconductor substrate to obtain a substrate metal passivation layer, wherein the substrate metal passivation layer covers the substrate front surface cellular metal layer and the substrate front surface terminal metal layer, and the substrate front surface cellular metal layer and the substrate front surface terminal metal layer can be separated by the substrate metal passivation layer;

step 7, etching the substrate metal passivation layer to obtain a substrate metal passivation layer window penetrating through the substrate metal passivation layer, wherein the substrate front cellular metal layer corresponding to the substrate metal passivation layer window can be exposed through the substrate metal passivation layer window;

and 8, performing a required back surface process on the back surface of the semiconductor substrate to obtain a required substrate back surface structure on the back surface of the semiconductor substrate.

7. The method of claim 6, wherein a substrate termination trench is formed in the termination region during trench etching of the semiconductor substrate, and a substrate termination insulating oxide layer and a substrate termination trench polysilicon layer filled in the substrate termination trench are formed in the substrate termination trench, wherein the substrate termination trench polysilicon layer is insulated and isolated from the inner sidewall and bottom wall of the substrate termination trench by the substrate termination insulating oxide layer;

and 3, when the substrate second conduction type base region is prepared, a substrate terminal second conduction type body region penetrating through the terminal region can be obtained at the same time, the substrate terminal second conduction type body region is positioned above the groove bottom of the substrate terminal groove, and the doping concentration of the substrate terminal second conduction type body region is smaller than that of the substrate second conduction type base region.

8. The method for manufacturing a low-cost high-performance trench power semiconductor device according to claim 7, wherein the step 3 specifically comprises the following steps:

step 3.1, injecting second conductive type impurity ions above the front surface of the semiconductor substrate to prepare at least one substrate second conductive type injection region between the substrate cellular second groove and the substrate terminal groove adjacent to the cellular region, wherein the substrate second conductive type injection region adjacent to the substrate cellular second groove is in contact with the side wall of the substrate cellular second groove adjacent to the terminal region, and the depth of the substrate second conductive type injection region in the semiconductor substrate is greater than the depth of the substrate cellular first groove, the substrate cellular second groove and the substrate terminal groove in the semiconductor substrate;

step 3.2, performing second conductive type impurity ion implantation on the front surface of the semiconductor substrate again to obtain a substrate second conductive type layer penetrating through the semiconductor substrate, wherein the substrate second conductive type layer is positioned above the corresponding groove bottoms of the substrate cellular first groove, the substrate cellular second groove and the substrate terminal groove;

step 3.3, performing first conductive type impurity ion implantation and second conductive type impurity ion implantation above the semiconductor substrate, obtaining a substrate second conductive type base region positioned in the cell region by utilizing the implanted second conductive type impurity ions and the substrate second conductive type layer in the cell region, obtaining a substrate first conductive type source region positioned above the substrate second conductive type base region by utilizing the implanted first conductive type impurity ions, and enabling the substrate first conductive type source region to be adjacent to the substrate second conductive type base region; meanwhile, a substrate terminal second conductive type body region can be obtained by utilizing the substrate second conductive type layer in the terminal region.

9. The method for manufacturing a low-cost high-performance trench power semiconductor device according to claim 7, wherein the step 3 specifically comprises the following steps:

step 3.a, performing second conductive type impurity ion implantation on the front surface of the semiconductor substrate to obtain a substrate second conductive type layer penetrating through the semiconductor substrate, wherein the substrate second conductive type layer is positioned above the corresponding groove bottoms of the substrate cellular first groove, the substrate cellular second groove and the substrate terminal groove;

step 3.b, injecting second conductive type impurity ions again above the front surface of the upper semiconductor substrate to prepare at least one substrate second conductive type injection region between the substrate cellular second groove and the substrate terminal groove adjacent to the cellular region, wherein the substrate second conductive type injection region adjacent to the substrate cellular second groove is contacted with the side wall of the substrate cellular second groove adjacent to the terminal region, and the depth of the substrate second conductive type injection region in the semiconductor substrate is greater than the depth of the substrate cellular first groove, the substrate cellular second groove and the substrate terminal groove in the semiconductor substrate;

step 3, c, performing first conductive type impurity ion implantation and second conductive type impurity ion implantation above the semiconductor substrate, obtaining a substrate second conductive type base region positioned in the cell region by utilizing the implanted second conductive type impurity ions and the substrate second conductive type layer in the cell region, obtaining a substrate first conductive type source region positioned above the substrate second conductive type base region by utilizing the implanted first conductive type impurity ions, and enabling the substrate first conductive type source region to be adjacent to the substrate second conductive type base region; meanwhile, a substrate terminal second conductive type body region can be obtained by utilizing the substrate second conductive type layer in the terminal region.

10. The method for manufacturing a low-cost high-performance trench power semiconductor device according to claim 6, wherein when a semiconductor substrate is subjected to trench etching, a cell edge transition region trench located in a cell region can be obtained, the cell edge transition region trench is located between a substrate cell second trench and a termination region, a depth of the substrate second conductivity type implantation region in the semiconductor substrate is greater than a depth of the cell edge transition region trench in the semiconductor substrate, and the substrate second conductivity type implantation region in contact with a sidewall of the substrate cell second trench covers an outer sidewall of the cell edge transition region trench;

the bottom of the cell edge transition region groove is located below the substrate second conduction type base region, substrate cell insulating oxide layers are arranged on the inner side wall and the bottom wall of the cell edge transition region groove, substrate cell groove polycrystalline silicon is filled in the cell edge transition region groove provided with the substrate cell insulating oxide layers, and the substrate cell groove polycrystalline silicon is insulated and isolated from the side wall and the bottom wall of the cell edge transition region groove through the substrate cell insulating oxide layers in the cell edge transition region groove.

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