CN111508448A - Display panel and control method thereof - Google Patents
Display panel and control method thereof Download PDFInfo
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- CN111508448A CN111508448A CN202010470085.5A CN202010470085A CN111508448A CN 111508448 A CN111508448 A CN 111508448A CN 202010470085 A CN202010470085 A CN 202010470085A CN 111508448 A CN111508448 A CN 111508448A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The embodiment of the invention provides a display panel and a control method thereof, relates to the technical field of display, and can solve the problem of poor display of a first row of sub-pixels in a large-size high-resolution display device.A time sequence controller is used for receiving a frame of image data to be displayed and judging that the scanning time of scanning each row of sub-pixels by a gate driver is the first scanning time T1 when the image data to be displayed does not comprise a plurality of rows of black image data arranged at intervals, the scanning time of at least every M rows of sequentially arranged sub-pixels is sequentially delayed and overlapped, T1 is M × H, H is 1/(f × N), f is the scanning frequency, and the time sequence controller is also used for judging that the scanning time of scanning the first row of sub-pixels by the gate driver is H and the scanning time of the plurality of sub-pixels sequentially arranged with the first row of sub-pixels is sequentially delayed and is less than or equal to the first scanning time T1 when the image data to be displayed comprises the plurality of rows of black image data arranged at intervals.
Description
Technical Field
The present application relates to the field of display technologies, and in particular, to a display panel and a control method thereof.
Background
At present, the liquid crystal display device usually adopts a progressive scanning driving mode to realize picture display. The display panel in the liquid crystal display device includes a plurality of sub-pixels defined by a plurality of rows of data lines and a plurality of rows of scanning lines crossing each other, and each of the sub-pixels includes a pixel electrode therein. The pixel driving method comprises the following steps: firstly, the scanning line of the first row is opened, the data line charges the pixel electrode of the first row, then the scanning line of the second row is opened, meanwhile, the scanning line of the first row is closed, the data line charges the pixel electrode of the second row, and so on.
Since the larger the size of the liquid crystal display device and the higher the resolution, the higher the refresh frequency will be, the shorter the time during which each row of scanning lines is turned on will be, resulting in a reduced charging time for each sub-pixel, and thus in a serious shortage of the charging rate of the pixel electrode.
In order to solve the problem, most of the existing large-size high-resolution liquid crystal display devices adopt a pre-charging mode, that is, each row of scanning lines is opened in advance, so that the pixel electrode in each sub-pixel is charged with voltage in advance, and the pre-charging mode can solve the problem of poor display caused by insufficient charging rate. However, the pre-charge mode may cause the charging rate of the first row of sub-pixels to be non-uniform with the charging rate of the remaining rows of sub-pixels, thereby causing the first row of sub-pixels to display badly.
Disclosure of Invention
The embodiment of the application provides a display panel and a control method thereof, which can solve the problem of poor display of first row sub-pixels in a large-size high-resolution display device.
In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:
the display panel is characterized by comprising a display area and a peripheral area positioned on at least one side of the display area, the display panel comprises N rows of sub-pixels positioned in the display area, the display panel further comprises a gate driver positioned in the peripheral area and electrically connected with each row of sub-pixels, the gate driver is used for scanning each row of sub-pixels, a timing controller positioned in the peripheral area and electrically connected with the gate driver, the timing controller is used for receiving a frame of image data to be displayed and judging whether scanning time for scanning each row of sub-pixels is first scanning time T1 when the image data to be displayed does not comprise a plurality of rows of black image data arranged at intervals, scanning time of at least every M rows of sub-pixels arranged in sequence is delayed and overlapped, wherein T1 is M × H, H is 1/(f × N), f is scanning frequency, the timing controller is used for judging whether the scanning time for scanning time of each row of sub-pixels except the first row of sub-pixels in the image data to be displayed is sequentially delayed and is equal to the first scanning time T1, the plurality of sub-pixels arranged at least M is sequentially, the scanning time for controlling the sub-pixels arranged in the first row of sub-pixels, and the gate driver is used for controlling the scanning time of the first scanning time T × N when the sub-pixels arranged in the next row of sub-pixels, and the first scanning time of the sub-pixels, the sub-pixel is smaller than the first scanning time of the first scanning time controller, and the sub-pixel, wherein the sub-pixel, the sub-pixel is used for controlling the sub-pixel.
In some embodiments, the timing controller includes a frame detection element configured to receive a frame of image data to be displayed and identify a display gray scale of each sub-pixel in the image data to be displayed, a determination element electrically connected to the frame detection element and configured to determine whether multiple lines of black image data are included in the image data to be displayed at intervals according to an identification result of the frame detection element, a first adjustment instruction is sent when the determination element determines that the multiple lines of black image data are not included in the image data to be displayed, a second adjustment instruction is sent when the determination element determines that the multiple lines of black image data are included in the image data to be displayed at intervals, a reference clock generation element electrically connected to the determination element and configured to generate a reference pulse signal having a first pulse width L, a clock signal generation element electrically connected to the determination element and the reference clock generation element, and the clock signal generation element is configured to calculate a first rising time, a first falling time, and a first falling time of a first clock signal of M clock signals, and generate M clock signals sequentially overlapping each other.
In some embodiments, the clock signal generating element is specifically configured to calculate a first rising time Tr1_ a and a first falling time Tf1_ a of a first clock signal of M clock signals, which have the same pulse width S and are sequentially delayed by H, according to the first adjustment command and the reference pulse signal, and generate the M clock signals, where Tr1_ a is equal to n ×L, Tf1_ a is equal to M ×L, Tf1_ a-Tr1_ a is equal to S, S is equal to M × H, n is equal to or greater than 1, M is equal to or greater than 1, and n and M are integers.
In some embodiments, the clock signal generating element is specifically configured to calculate a first rising time Tr1_ b and a first falling time Tf1_ b of a first clock signal of M clock signals according to the second adjustment command and the reference pulse signal, and generate the M clock signals, where the first clock signal has a pulse width S1, the M clock signals are sequentially delayed and sequentially increased, the M clock signal has a pulse width SM, where 0 < SM ≦ M × H, Tr1_ b ═ i ×L, Tf1_ b ═ j ×L, Tf1_ a-Tr1_ a ═ S1, 0 < S1 ≦ H, i ≧ 1, j ≧ 1, and i and j are integers.
In some embodiments, the display panel further comprises an image processor; the image processor is used for forming image data to be displayed.
In some embodiments, the display panel includes N rows of sub-pixels and a plurality of gate driving groups; the first group of the grid driving group comprises M non-cascaded shift registers which are arranged in sequence; the output end of the Q & ltth & gt shift register is electrically connected with the input end of the Q & lt + 3& gt shift register; q is not less than 1 and is an integer; the clock signal generating element is provided with M clock signal ends, the display panel further comprises a plurality of phase inverters, one clock signal end is electrically connected with the Q & ltth & gt shift register and the input end of one phase inverter, and the output end of the phase inverter is electrically connected with the Q & lt + 3& gt shift register.
The second aspect of the invention provides a control method of a display panel, which is used for controlling the display panel, wherein the display panel is provided with a display area and a peripheral area positioned on at least one side of the display area, the display panel comprises N rows of sub-pixels positioned in the display area, the control method comprises the steps of receiving image data to be displayed in one frame, controlling a grid driver to scan each row of sub-pixels for a first scanning time T1 when the number of the images to be displayed does not comprise a plurality of rows of black image data arranged at intervals, controlling the scanning time of at least every M rows of sub-pixels arranged in sequence to be delayed and overlapped, wherein T1 is M × H, H is 1/(f × N), f is a scanning frequency, controlling the scanning time of the grid driver to scan the first row of sub-pixels for H when the image data to be displayed comprises the black image data arranged at intervals except the first row of sub-pixels, controlling the scanning time of the grid driver to scan the first row of sub-pixels for H, and providing the sub-pixel data for the first row when the plurality of sub-pixels arranged in sequence except the first row of the first sub-pixels are delayed and all the scanning time of the first row of the first sub-pixels is smaller than the first scanning time T1.
In some embodiments, the method includes the steps of identifying display gray scales of sub-pixels in image data to be displayed and outputting an identification result, judging whether black image data of multiple lines arranged at intervals are included in the image data to be displayed according to the identification result, sending a first adjusting instruction when a judging element judges that the black image data of the multiple lines arranged at intervals are not included in the image data to be displayed, sending a second adjusting instruction when the judging element judges that the black image data of the multiple lines arranged at intervals are included in the image data to be displayed, generating a reference pulse signal, wherein the reference pulse signal has a first pulse width L, calculating a first rising time and a first falling time of a first clock signal in M clock signals according to the first adjusting instruction, the second adjusting instruction and the reference pulse signal, and generating the M clock signals, wherein the M clock signals are delayed and overlapped in sequence.
In some embodiments, a first rising time Tr1_ a and a first falling time Tf1_ a of a first clock signal of M clock signals are calculated according to the first adjustment command and the reference pulse signal, and the M clock signals are generated, wherein pulse widths S of the M clock signals are the same and are sequentially delayed by H, wherein Tr1_ a is equal to n ×L, Tf1_ a is equal to M ×L, Tf1_ a is equal to Tr1_ a is equal to S, S is equal to M × H, n is equal to or greater than 1, M is equal to or greater than 1, and n and M are integers.
In some embodiments, a first rising time Tr1_ b and a first falling time Tf1_ b of a first clock signal of M clock signals are calculated according to the second adjustment command and the reference pulse signal, and the M clock signals are generated, wherein the first clock signal has a pulse width S1, 0 < S1 ≤ H, the M clock signals are sequentially delayed and sequentially increased, the M clock signal has a pulse width SM, 0 < SM ≤ M × H, Tr1_ b ═ i ×L, Tf1_ b ═ j ×L, i ≥ 1, Tf1_ a-Tr1_ a ═ S1, 0 < S1 ≤ H, j ≥ 1, and i and j are integers.
The embodiment of the invention provides a display panel and a control method thereof, because a time sequence controller can judge image data to be displayed, and pre-charges first row sub-pixels when judging that the image data to be displayed does not comprise a plurality of rows of black image data arranged at intervals, and does not pre-charge the first row sub-pixels when judging that the image data to be displayed comprises the plurality of rows of black image data arranged at intervals except the first row sub-pixels, when the display panel displays different pictures, the problems of the first row sub-pixels such as dark display and bright display can be simultaneously solved, independent debugging is not needed, and the realization is easy.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1a is a schematic diagram of a display panel provided in the related art;
FIG. 1b is a timing diagram of signal terminals of a gate driver according to the related art;
FIG. 2a is a schematic view of a display screen of another display panel provided in the related art;
FIG. 2b is a timing diagram of signal terminals of a gate driver according to the related art;
fig. 3 is a schematic structural diagram of a display device according to an embodiment of the present invention;
fig. 4 is a schematic diagram illustrating region division of a display panel according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 6 is a diagram of a shift register according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a timing controller according to an embodiment of the present invention;
fig. 8 is a timing diagram of each signal terminal of a timing controller according to an embodiment of the present invention;
FIG. 9 is a timing diagram of signal terminals of another timing controller according to an embodiment of the present invention;
fig. 10 is a timing diagram of signal terminals of a gate driver according to an embodiment of the invention;
FIG. 11 is a timing diagram of signal terminals of another gate driver according to an embodiment of the present invention;
fig. 12 is a flowchart illustrating a control method of a display panel according to an embodiment of the invention;
FIG. 13 is a diagram illustrating a display screen of a display panel according to an embodiment of the present invention;
fig. 14 is a schematic view of a display screen of a display panel according to an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the embodiments of the present application, the words "first", "second", and the like are used to distinguish the same items or similar items having substantially the same functions and actions. Those skilled in the art will appreciate that the terms "first," "second," etc. do not denote any order or quantity, nor do the terms "first," "second," etc. denote any order or importance.
The related art provides a precharge mode, that is, each row of scanning lines is opened in advance to enable the pixel electrodes to be charged with voltage in advance, as shown in fig. 1a and 1b, the liquid crystal display device has a Blanking area (also called a black insertion area) between two adjacent frames, that is, after one frame of image display is finished, the liquid crystal display device is blank scanned for a period of time and then the next frame of image display is carried out, so that image quality dynamics can be improved, after the black insertion display is finished, the voltage on the pixel electrodes is maintained at a black point voltage (that is, the voltage on the pixel electrodes is zero, or the gray scale displayed by the pixel is L0). when the next frame of image display is carried out, when the first row of scanning lines is opened in advance (for example, the time of opening in advance is 2H), as can be seen with reference to fig. 1b, the voltage on the pixel electrodes of the first row of sub-pixels is zero during the time of the first row of sub-pixels, when the first row of sub-pixels needs to display a higher gray scale (for example, 255), the first row of sub-pixels starts to input data voltage to the pixel electrodes of the first row of sub-pixels, so that the first row of sub-pixels is insufficient, the gray scale display is not enough to display a dark data voltage, and accordingly, when the first row of sub-pixel needs to be displayed by the first row of the first sub-pixel, the first row of sub-pixel, the first sub-.
As shown in fig. 2a and 2b, in order to solve the above-mentioned problem of dark display of the first row of sub-pixels, the embodiment of the present invention provides a mode for precharging the first row of sub-pixels, after the black insertion display is completed, the first row of sub-pixels is turned on (for example, turned on 2H in advance), a preset data voltage is input to the pixel electrodes of the first row of sub-pixels within a time period of the previous 2H (i.e., a data voltage of a certain gray scale to be displayed by the first row of sub-pixels is input to the pixel electrodes of the first row of sub-pixels), so that after the black insertion display is completed, at the time of image display of the next frame, the pixel voltage on the pixel electrodes of the first row of sub-pixels is maintained at the pixel voltage on the pixel electrodes of the first row of sub-pixels at the time of image display, thereby improving the problem of dark display of the first row of sub-pixels.
The display device provided by the embodiment of the invention can be any product or component with a display function, such as a television, a digital camera, a mobile phone, a tablet computer, an electronic photo frame, a navigator and the like, and the embodiment of the invention is not limited to this.
As shown in fig. 3, the main structure of the display device includes a frame 1, a cover plate 2, a display panel 3, a circuit board 4, a backlight module 5, and other accessories. Here, the display panel 3 may be a flexible display panel or a rigid display panel. In the case where the display panel 3 is a flexible display panel, the display device is a flexible display device.
The longitudinal section of the frame 1 is U-shaped, the display panel 3, the circuit board 4, the backlight assembly 5 and other accessories are all arranged in the frame 1, the circuit board 4 is arranged below the display panel 3 (i.e. the back face, the side deviating from the display face of the display panel 3), the cover plate 2 is arranged on one side of the display panel 3 far away from the circuit board 4, the backlight assembly 5 is arranged below the circuit board 4, that is, the circuit board 4 is arranged between the display panel 3 and the backlight assembly 5.
It should be noted that the Circuit Board 4 is electrically connected to the display panel 3, and the Circuit Board 4 generally includes a Flexible Printed Circuit (FPC), a driver chip (IC), a Printed Circuit Board (PCB), a connection substrate, and the like; the circuit board 4 is used to supply various display screen information to the display panel 3 after power is turned on.
The embodiment of the invention provides a display panel 3. As shown in fig. 4, the display panel 3 is divided into a display area a1 and a peripheral area a2 located at least on one side of the display area a1, and fig. 4 illustrates an example in which the peripheral area a2 surrounds the display area a 1. The display area a1 includes a plurality of subpixels P.
As shown in fig. 5, the display panel 3 includes the gate driver 30, the timing controller 31, and the source driver 32 in the peripheral region a 2. The display panel 3 further includes a power supply voltage generator 33 and a gray scale voltage generator 34.
Referring to fig. 5, the gate driver 30, the timing controller 31, the source driver 32, the power voltage generator 33, and the gray scale voltage generator 34 are all connected to a system (a main board of the display device) through a system interface, and signals input from the system pass through the system interface, wherein the power signals are input to the power voltage generator 33, the digital signals are input to the timing controller 32(TCON), the digital signals input to the timing controller 32 by the system include a Sout signal (RGB data) and a clock signal C L K, and also include three control signals, which are a data enable signal, a line synchronization signal Hsync (HS for short), and a field synchronization signal Vsync (VS for short), respectively, and these signals are processed by the timing controller 32(TCON) and then transmitted to the source driver 32, so that the source driver 32 inputs a certain gray scale voltage to the display panel 3 at a certain time, thereby realizing the display of the display panel 3.
Here, the system interface may be, for example, a V-by-One (Vx 1 for short) interface, and the V-by-One interface is a signal interface technology that is commonly used at present due to its characteristics of low power consumption and supporting data transmission up to 4 Gbps. The V-by-One interface carries out high-speed serial Data transmission in a CDR (clock Data recovery) mode, fundamentally solves the problem of transmission line time lag, does not need a clock transmission line, and has strong capability of inhibiting EMI (Electromagnetic Interference).
The V-by-One interface can also reduce the wiring of the PCB. For example, UHD (Ultra High Definition) 60Hz display panels require only 18 lines; the UHD120Hz display panel only requires 34 lines.
In some embodiments, as shown in fig. 5, the display panel 3 includes N rows of sub-pixels P; the gate driver 30 includes a plurality of gate driving groups; the first group of grid driving groups comprises M non-cascaded shift registers which are arranged in sequence; the output end of the Q & ltth & gt shift register is electrically connected with the input end of the Q & lt + 3& gt shift register; wherein Q is not less than 1 and is an integer.
Alternatively, as shown in fig. 6, fig. 6 illustrates that the gate driver 30 includes two gate driving groups, and each gate driving group includes three non-cascaded shift registers arranged in sequence. For example, the INPUT terminals INPUT of the first shift register RS1, the second shift register RS2, and the third shift register RS3 in the first gate driving group are all electrically connected to the start signal terminal STV. The OUTPUT end OUTPUT of the first shift register RS1 in the first group of gate drive groups is electrically connected with the INPUT end INPUT of the first shift register RS4 in the second group of gate drive groups; the OUTPUT end OUTPUT of the second shift register RS2 in the first group of gate drive groups is electrically connected with the INPUT end INPUT of the second shift register RS5 in the second group of gate drive groups; the OUTPUT terminal OUTPUT of the third shift register RS3 in the first group of gate driving groups is electrically connected to the INPUT terminal INPUT of the third shift register RS6 in the second group of gate driving groups.
As shown in fig. 5, the display panel 3 further includes a source driver 32, the source driver 32 is electrically connected to the timing controller 31, and the source driver 32 is configured to provide the first row data voltage to the first row sub-pixels under the control of the timing controller 31 when the gate driver 30 is at least scanning the first row sub-pixels P.
It should be noted that the source driver 32 may provide the first row data voltage to the first row sub-pixels P when the gate driver 30 scans the first row sub-pixels P; the first row data voltage may be supplied to the first row subpixel P before the gate driver 30 scans the first row subpixel P.
Here, the first row data voltage is a pixel voltage required for the first row subpixel P to display a certain gray level in one frame image. I.e., when the gate driver 30 scans the first row of subpixels P; or before scanning the first row of subpixels P, the timing controller 31 controls the source driver 32 to input the first row data voltage. Thus, when the gate driver 30 scans the first row of sub-pixels P (i.e. after the first row scanning line G1 is turned on), the first row of sub-pixels P enters the charging phase, and when the gate driver 30 scans the first row of sub-pixels P in advance, the first row of sub-pixels P can be pre-charged, so as to improve the related defect caused by insufficient pixel charging rate.
In combination with the above embodiments, in a specific implementation, as shown in fig. 5, the display panel 3 further includes an image processor 35, and the image processor 35 is configured to form a frame of image data to be displayed. The image data to be displayed is multi-line black image data which is not arranged at intervals, namely the image data to be displayed is normally displayed; alternatively, the image data to be displayed includes a plurality of lines of black image data arranged at intervals, in addition to the first line of sub-pixels P, that is, the image data to be displayed is image data to be displayed when the performance of the display panel 3 is checked.
Note that, in the case where the image data to be displayed includes a plurality of lines of black image data arranged at intervals in addition to the first line of sub-pixels P, that is, the second line of sub-pixels P to the nth line of sub-pixels P include a plurality of lines of black image data arranged at intervals. In some embodiments, between the second row sub-pixel P and the nth row sub-pixel P, the even row sub-pixel P is black image data. In other embodiments, between the second row of sub-pixels P and the nth row of sub-pixels P, the odd row of sub-pixels P are black image data. Referring to fig. 2a, fig. 2a illustrates an example in which the sub-pixels P in the even-numbered rows are black image data.
Here, the black image data is image data when the subpixel P displays a gray scale of L0.
Referring again to fig. 5, the image processor 35 is electrically connected to the timing controller 31, the image processor 35 transmits the formed frame of image data to be displayed to the timing controller 31, and the timing controller 31 is configured to receive the frame of image data to be displayed and determine whether the frame of image data to be displayed includes multiple rows of black image data arranged at intervals.
The timing controller 31 receives a frame of image data to be displayed, and then determines that when the image data to be displayed does not include multiple lines of black image data arranged at intervals, the scanning time of the gate driver 30 for scanning each line of sub-pixels P is a first scanning time T1, the scanning time of at least every M lines of sub-pixels P arranged sequentially is delayed and overlapped, wherein T1 is M × H, H is 1/(f × N), and f is a scanning frequency, and the timing controller 31 is further configured to determine that when the image data to be displayed includes multiple lines of black image data arranged at intervals in addition to the first lines of sub-pixels P, the scanning time of the gate driver 30 for scanning the first lines of sub-pixels P is H, the scanning time of at least every M lines of sub-pixels arranged sequentially with the first lines of sub-pixels P is delayed sequentially, and is less than or equal to the first scanning time T1.
In conjunction with the above-described embodiment, in the case where, in the image data to be displayed, plural lines of black image data arranged at intervals are not included, since the gate driver 30 includes plural sets of gate driving groups; each gate driving group includes M non-cascaded shift registers arranged in sequence, so that when the timing controller 31 controls the scanning time of the gate driver 30 scanning each row of the sub-pixels P, the scanning signals output by the M non-cascaded shift registers arranged in sequence cause the scanning time of the sub-pixels P arranged in sequence in each M rows to be delayed and overlapped in sequence, and thus, the gate driver 30 can be ensured to scan each M rows of the sub-pixels in sequence.
It should be noted that, since H is 1/(f × N), f is a scanning frequency, and thus the value of H is determined by the scanning frequency and the number of rows N of sub-pixels included in the display panel 3, the scanning frequency f may be 60Hz, 80Hz, 120Hz, etc., the display panel 3 may include 2160 rows of sub-pixels, etc., taking the scanning frequency f as 60Hz and the display panel 3 includes 2160 rows of sub-pixels, for example, H is 1/(f × N) is 1/(60 × 2160), for example, when M is 3, T1 3 × H is 3 × 1/(60 × 2160), in the case where a plurality of rows of black image data disposed at intervals are not included in the image data to be displayed, the timing controller 31 controls the gate driver 30 to scan the first row of sub-pixels P for a scanning time of 3H, that is a pixel electrode of the first row of sub-pixels P, that is a pixel voltage of the first row of sub-pixels P is advanced, for example, the first row of sub-pixels P is charged in a time of the first row of sub-pixels P, and the first row of sub-pixels P is charged in a gray scale state, which is pre-charged in the same as the first row of sub-pixels P.
In the case where, in the image data to be displayed, a plurality of rows of black image data arranged at intervals are included in addition to the first row of sub-pixels P, the timing controller 31 controls the scanning time for the gate driver 30 to scan the first row of sub-pixels P to be H, and the scanning time for scanning a plurality of rows of sub-pixels arranged in sequence with the first row of sub-pixels P in every M rows is sequentially delayed, so that it is possible to ensure that the gate driver 30 sequentially scans every M rows of sub-pixels.
Optionally, when the scanning time of the plurality of rows of sub-pixels sequentially arranged with the first row of sub-pixels P in each M rows is sequentially delayed, whether the scanning time of the plurality of rows of sub-pixels sequentially arranged with the first row of sub-pixels P overlaps is not limited. The scanning times of the plurality of rows of subpixels sequentially arranged with the first row of subpixels P may overlap; or may not overlap. For example, when M is 3, each gate driving group includes three shift registers that are not cascaded and are arranged in sequence. In three rows of sub-pixels P, the scanning time of the first row of sub-pixels P is H, and the scanning time of the second row of sub-pixels P and the third row of sub-pixels P may be greater than H; and may also be equal to H.
In the case where the scanning times of the second and third rows of sub-pixels P are greater than H, the scanning times of the second and third rows of sub-pixels P have an overlap; in the case where the scanning times of the second and third rows of subpixels P are equal to H, there is no overlap in the scanning times of the second and third rows of subpixels P.
Based on the above, since the timing controller 31 controls the scan time for the gate driver 30 to scan the first row of sub-pixels P to be H, that is, the pixel electrodes of the first row of sub-pixels P are not precharged, in the case where a plurality of lines of black image data arranged at intervals are included in the image data to be displayed, in addition to the first row of sub-pixels P, the problem of the display luminance of the first row of sub-pixels P is solved.
In summary, in the embodiment of the present invention, since the timing controller 31 can determine the image data to be displayed, and determine that the first row of sub-pixels P is precharged when the image data to be displayed does not include the multiple rows of black image data arranged at intervals, and determine that the first row of sub-pixels P is not precharged when the image data to be displayed includes the multiple rows of black image data arranged at intervals in addition to the first row of sub-pixels P, when the display panel 3 displays different pictures, the problems of the first row of sub-pixels P such as dark display and bright display can be solved at the same time, and the present invention is not required to be separately debugged and is easy to implement.
As shown in fig. 5 and 6, the timing controller 31 is further electrically connected to the gate driver 30, and the timing controller 31 processes the clock signal C L K received from the system and transmits the processed clock signal C L K to the gate driver 30, on this basis, the gate driver 30 includes a plurality of gate driving sets, each gate driving set includes a plurality of shift registers, and one shift register is electrically connected to one scan line G, so that one clock signal C L K output by the timing controller 31 is electrically connected to one scan line G, and each scan line G is electrically connected to one row of sub-pixels P, so that the timing controller 31 can control the gate driver 30 to scan each row of sub-pixels P.
Optionally, as shown in fig. 7, the timing controller 31 includes a frame detecting element 310, a determining element 311, a reference clock generating element 312, and a clock signal generating element 313.
The image detection device 310 is used for receiving a frame of image data to be displayed and identifying display gray scales of each sub-pixel in the image data to be displayed, the display gray scales include L0-L255, when the display gray scale is L0, the image data to be displayed is black image data, namely, the displayed image is black, and when the display gray scale is L255, the image data to be displayed is white image data, namely, the displayed image is white.
The judging element 311 is electrically connected to the image detecting element 310, and the judging element 311 judges whether the image data to be displayed includes multiple lines of black image data arranged at intervals according to the result identified by the image detecting element 310; when the judgment element 311 judges that the image data to be displayed does not include a plurality of lines of black image data set at intervals, a first adjustment instruction is sent; when the judgment element 311 judges that the image data to be displayed includes a plurality of lines of black image data set at intervals, a second adjustment instruction is sent.
The reference clock generating element 312 is electrically connected to the determining element 311, and when receiving the first adjustment command and the second adjustment command sent from the determining element 311, the reference clock generating element 312 generates a reference pulse signal DE having a first pulse width L.
The reference clock generating element 312 generates the reference pulse signal DE having a reference frequency, that is, the frequency of the reference pulse signal DE is constant.
The clock signal generating element 313 is electrically connected to the judging element 311 and the reference clock generating element 312, and the clock signal generating element 313 calculates a first rising time and a first falling time of a first clock signal among the M clock signals, which are sequentially delayed and overlapped, according to the first adjustment instruction, the second adjustment instruction, and the reference pulse signal, and generates the M clock signals.
Optionally, the timing controller 31 further includes a memory, and the memory has a first rising time and a first falling time (i.e. a preset first rising time and a preset first falling time) of a first clock signal of the M clock signals stored in advance; the first adjustment instruction and the second adjustment instruction are used for controlling the clock signal generation element 313 to calculate the actual first rising time and the actual first falling time of the first clock signal in the M clock signals according to the preset first rising time and the preset first falling time so as to generate the M clock signals.
Alternatively, the memory may be a device having a memory function. For example, may be a read-only memory (ROM) or other type of static storage device that may store static information and instructions, a Random Access Memory (RAM) or other type of dynamic storage device that may store information and instructions
On this basis, the clock signal generating unit 313 may further include, for example, a processor, and the processor calculates an actual first rising time and a first falling time of the first clock signal of the M clock signals according to the first adjusting instruction and the second adjusting instruction.
Alternatively, the memory may be separate or integrated with the processor. The memory is used for storing execution instructions for executing the above embodiments. Such as a first adjustment instruction and a second adjustment instruction. The processor is used for executing the first adjusting instruction and the second adjusting instruction stored by the memory to calculate the actual first rising time and the actual first falling time of the first clock signal in the M clock signals.
Optionally, as shown in fig. 8, the clock signal generating component 313 calculates a first rising time Tr1_ a and a first falling time Tf1_ a of a first clock signal C L K1 of the M clock signals according to the first adjustment command and the reference pulse signal DE, and generates M clock signals, where pulse widths S of the M clock signals are the same and are sequentially delayed by H, where Tr1_ a is n ×L, Tf1_ a is M ×L, Tf1_ a is Tr1_ a is S, S is M × H, n is greater than or equal to 1, M is greater than or equal to 1, and n and M are integers.
As shown in fig. 8, when the processor receives the first adjustment command, the first rising time Tr1_ a and the first falling time Tf1_ a of the first clock signal C L K1 of the M clock signals are calculated according to the preset first rising time and first falling time of the first clock signal C L K1 and the first pulse width L of the reference pulse signal DE.
On the basis of this, the pulse width of the first clock signal C L K1, i.e., Tf1_ a-Tr1_ a ═ S, can be calculated from the difference between the first rising time Tr1_ a and the first falling time Tf1_ a, and therefore, the pulse width of the first falling time Tf1_ a is greater than the pulse width of the first rising time Tr1_ a.
For example, referring to fig. 8, the processor starts counting at the start position of the 1 st pulse signal of the reference pulse signal DE and finishes counting at the stop position of the 1 st pulse signal of the reference pulse signal DE according to the preset first rising time of the first clock signal C L K1, and at this time, the first rising time Tr1_ a is the distance between the start position of the 1 st pulse signal of the reference pulse signal DE and the stop position of the 1 st pulse signal, that is, the first rising time Tr1_ a is a first pulse width L of the reference pulse signal DE.
Optionally, the processor starts counting at the start position of the 1 st pulse signal of the reference pulse signal DE and finishes counting at the stop position of the 4 th pulse signal of the reference pulse signal DE according to a preset first falling time of the first clock signal C L K1, where the first falling time Tf1_ a is a distance between the start position of the 1 st pulse signal and the stop position of the 4 th pulse signal of the reference pulse signal DE, that is, the first falling time Tf1_ a is four first pulse widths L of the reference pulse signal DE.
The pulse width of the first clock signal C L K1 is calculated from the difference between the first rising time Tr1_ a and the first falling time Tf1_ a, and based on the above, the pulse width of the first clock signal C L K1 is equal to the three first pulse widths L of the reference pulse signal DE.
It should be noted that, since the reference pulse signal DE has a certain time interval between two adjacent pulses, the pulse width of the first clock signal C L K1 shown in fig. 8 is not completely equal to the three pulse widths L of the reference pulse signal DE, in a specific implementation, the pulse width of the first clock signal C L K1 is equal to the sum of the first pulse width L of the reference pulse signal DE and the interval time between two adjacent pulses of the reference pulse signal DE.
Optionally, as shown in fig. 9, the clock signal generating element 312 calculates a first rising time Tr1_ b and a first falling time Tf1_ b of a first clock signal C L K1 of the M clock signals according to the second adjustment command and the reference pulse signal DE, and generates M clock signals, wherein the first clock signal has a pulse width S1, the M clock signals are sequentially delayed and sequentially increased, and the mth clock signal has a pulse width S1M，0＜SMM × H is not more than M, Tr1_ b is not less than i ×L, Tf1_ b is not less than j ×L, Tf1_ a-Tr1_ a is not less than S1, S1 is more than 0 and not more than H, i is not less than 1, j is not less than 1, and i and j are integers.
As shown in fig. 9, when the processor receives the second adjustment command, the first rising time Tr1_ b and the first falling time Tf1_ b of the first clock signal C L K1 of the M clock signals are calculated according to the preset first rising time and first falling time of the first clock signal C L K1 and the first pulse width L of the reference pulse signal DE.
On the basis of this, the pulse width of the first clock signal C L K1, i.e., Tf1_ b-Tr1_ b is S1, can be calculated from the difference between the first rising time Tr1_ b and the first falling time Tf1_ b, so that the pulse width of the first falling time Tf1_ b is greater than the pulse width of the first rising time Tr1_ b.
For example, referring to fig. 9, the processor starts counting at the start position of the 1 st pulse signal of the reference pulse signal DE and ends counting at the end position of the 3 rd pulse signal of the reference pulse signal DE according to the first rising time of the preset first clock signal C L K1, and at this time, the first rising time Tr1_ b is the distance between the start position of the 1 st pulse signal and the end position of the 3 rd pulse signal of the reference pulse signal DE, that is, the first rising time Tr1_ b is three first pulse widths L of the reference pulse signal DE.
Optionally, the processor starts timing at a start position of a1 st pulse signal of the reference pulse signal DE and finishes timing at an off position of a 4 th pulse signal of the reference pulse signal DE according to a preset first falling time of the first clock signal C L K1, where the first falling time Tf1_ b is a distance between the start position of the 1 st pulse signal and the off position of the 4 th pulse signal of the reference pulse signal DE, that is, the first falling time Tf1_ a is four first pulse widths L of the reference pulse signal DE.
The pulse width of the first clock signal C L K1 is calculated based on the difference between the first rising time Tr1_ b and the first falling time Tf1_ b, and based on the above, the pulse width of the first clock signal C L K1 is equal to a first pulse width L of the reference pulse signal DE.
It should be noted that, since the reference pulse signal DE has a certain time interval between two adjacent pulses, the pulse width of the first clock signal C L K1 shown in fig. 9 is not completely equal to one pulse width of the reference pulse signal DE, in a specific implementation, the pulse width of the first clock signal C L K1 is equal to the sum of the first pulse width L of the reference pulse signal DE and the interval time between two adjacent pulses of the reference pulse signal DE.
The clock generating element 313 may calculate M-1 clock signals, or may calculate a first clock signal C L K1 of the M clock signals and then generate M-1 clock signals according to the first clock signal C L K1
In summary, the timing controller 31 adjusts the pulse waveform of the clock signal C L K to the pulse waveforms shown in fig. 8 and 9, so as to obtain the pulse waveforms of the scan lines shown in fig. 10 and 11, and as shown in fig. 8, 9, 10 and 11, it can be seen that the pulse waveform of the clock signal C L K is the same as the pulse waveform of the scan line.
Referring again to fig. 7, the clock signal generating element 313 has M clock signal terminals, and the display panel 3 further includes a plurality of inverters, one clock signal terminal is electrically connected to the Q-th shift register and an input terminal of one inverter, and an output terminal of the inverter is electrically connected to the Q + 3-th shift register.
As shown in fig. 6 and 7, the clock signal generating device 313 has six clock signal terminals C L K1, C L K2, C L0K 3, C L K4, C L K5, and C L K6, and the display panel 3 further includes three inverters, and based on this, the first clock signal terminal C L K1 is electrically connected to the first shift register RS1 and an input terminal of one inverter, and an output terminal of the inverter is electrically connected to the fourth shift register RS4, and at this time, an output terminal of the inverter is the fourth clock signal terminal C4, the second clock signal terminal C4K 4 is electrically connected to the second shift register RS4 and an input terminal of one inverter, and an output terminal of the inverter is electrically connected to the fifth shift register RS4, and at this time, an output terminal of the inverter is the fifth clock signal terminal C4, the third clock signal terminal C4K 4 is electrically connected to the third shift register RS4 and an input terminal of one inverter, and at this time, an output terminal of the sixth clock signal terminal C4 is electrically connected to the sixth shift register RS 4.
Since the display panel 3 further includes a plurality of inverters, a clock signal terminal is electrically connected to the Q-th shift register and an input terminal of one inverter, and an output terminal of one inverter is electrically connected to the Q + 3-th shift register, in the clock signal generated by the clock signal generating element 313, a signal output from the Q-th clock signal terminal and a signal output from the Q + 3-th clock signal terminal are inverted with respect to each other, and thus, a signal output from the Q-th shift register and a signal output from the Q + 3-th shift register are inverted with respect to each other. As shown in fig. 10 and 11, it can be seen that the pulse waveforms of G1, G2, G3 are complementary to those of G4, G5, G6.
The embodiment of the invention also provides a control method of the display panel 3, which is used for controlling the display panel 3 to realize corresponding functions. As shown in fig. 12, the control method includes:
and S10, receiving one frame of image data to be displayed.
S11, judging that when the image data to be displayed does not include a plurality of rows of black image data arranged at intervals, the scanning time of controlling the gate driver 30 to scan each row of sub-pixels P is the first scanning time T1, the scanning time of at least every M rows of sub-pixels P arranged at intervals is sequentially delayed and overlapped, wherein T1 is M × H, H is 1/(f × N), and f is the scanning frequency, and the timing controller 31 is also used for judging that when the image data to be displayed includes a plurality of rows of black image data arranged at intervals except the first row of sub-pixels P, the scanning time of controlling the gate driver 30 to scan the first row of sub-pixels P is H, the scanning time of scanning at least every M rows of sub-pixels arranged at intervals and the plurality of rows of sub-pixels arranged sequentially with the first row of sub-pixels P is sequentially delayed, and is less than or equal to the first scanning time T1.
S12, supplying the first row data voltage to the first row subpixel P at least when the first row subpixel P is scanned.
Here, after receiving one frame of image data to be displayed, step S11 includes:
s101, identifying the display gray scale of each sub-pixel in the image data to be displayed, and outputting an identification result.
S102, judging whether the image data to be displayed comprises a plurality of lines of black image data arranged at intervals or not according to the identification result; when the image data to be displayed does not comprise a plurality of lines of black image data which are arranged at intervals, sending a first adjusting instruction; and when the image data to be displayed comprises a plurality of lines of black image data which are arranged at intervals, sending a second adjusting instruction.
S103, generating a reference pulse signal DE having a first pulse width L.
And S104, calculating the first rising time and the first falling time of the first clock signal in the M clock signals according to the first adjusting instruction, the second adjusting instruction and the reference pulse signal, and generating the M clock signals, wherein the M clock signals are delayed and overlapped in sequence.
Here, calculating a first rising time and a first falling time of a first clock signal of M clock signals, and generating the M clock signals specifically includes:
s1041, calculating a first rising time Tr1_ a and a first falling time Tf1_ a of a first clock signal C L K1 in the M clock signals according to the first adjusting command and the reference pulse signal, and generating M clock signals, wherein pulse widths S of the M clock signals are the same and are sequentially delayed by H, Tr1_ a is n ×L, Tf1_ a is M ×L, Tf1_ a is Tr1_ a is S, S is M × H, n is more than or equal to 1, M is more than or equal to 1, and n and M are integers.
S1042, calculating a first rising time Tr1_ b and a first falling time Tf1_ b of a first clock signal C L K1 in the M clock signals according to a second adjusting instruction and the reference pulse signal, and generating M clock signals, wherein the first clock signal has a pulse width S1, the M clock signals are delayed in sequence and increased in sequence, and the Mth clock signal has a pulse width S1M，0＜SMM × H is not more than M, Tr1_ b is not less than i ×L, Tf1_ b is not less than j ×L, Tf1_ a-Tr1_ a is not less than S1, S1 is more than 0 and not more than H, i is not less than 1, j is not less than 1, and i and j are integers.
It should be noted that the control method of the display panel in the embodiment of the present invention may be executed by the structure in the display panel 3 provided in the foregoing embodiment. For explanation of the control method of the display panel 3, reference may be made to the foregoing embodiments, and details will not be repeated here.
In summary, according to the display panel 3 and the method for controlling the display panel 3 provided by the embodiment of the invention, by adding the determining element 311 to the timing controller 31 in the display panel 3, the determining element 311 determines whether the image data to be displayed includes multiple rows of black image data arranged at intervals; when the judgment element 311 judges that the image data to be displayed does not include a plurality of lines of black image data arranged at intervals, the subpixels P in the first line are precharged; when the judgment element 311 judges that the image data to be displayed includes a plurality of lines of black image data arranged at intervals in addition to the first line of sub-pixels P, the first line of sub-pixels P are not precharged, so that the problem of the dark and light display of the first line of sub-pixels P can be solved at the same time.
Referring to fig. 13 and 14, comparing fig. 1a and 2a with fig. 13 and 14, it is apparent that after the implementation of the scheme of the display panel 3 and the control method of the display panel 3 according to the embodiment of the present invention, the sub-pixels P in the first row of the display panel 3 display no poor bright and dark lines, and the display is normal.
Those of ordinary skill in the art will understand that: all or part of the steps for implementing the method embodiments may be implemented by hardware related to program instructions, and the program may be stored in a computer readable storage medium, and when executed, the program performs the steps including the method embodiments; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. The display panel is characterized by comprising a display area and a peripheral area positioned on at least one side of the display area; the display panel comprises N rows of sub-pixels positioned in the display area; the display panel further includes:
the grid driver is positioned in the peripheral area and is electrically connected with each row of sub-pixels; the gate driver is used for scanning each row of sub-pixels;
the time sequence controller is positioned in the peripheral area and electrically connected with the gate driver, and is used for receiving a frame of image data to be displayed and judging that when the image data to be displayed does not comprise a plurality of rows of black image data arranged at intervals, the scanning time of the gate driver for scanning each row of sub-pixels is the first scanning time T1, the scanning time of at least every M rows of sub-pixels arranged in sequence is delayed and overlapped in sequence, wherein T1 is M × H, H is 1/(f × N), f is the scanning frequency, and the time sequence controller is also used for judging that when the image data to be displayed comprises a plurality of rows of black image data arranged at intervals except the first row of sub-pixels, the scanning time of the gate driver for scanning the first row of sub-pixels is H, the scanning time of at least every M rows of sub-pixels arranged in sequence with the first row of sub-pixels is delayed in sequence, and is less than or equal to the first scanning time T1;
and the source driver is positioned in the peripheral area and electrically connected with the time sequence controller, and is used for providing a first row of data voltages for the first row of sub-pixels under the control of the time sequence controller when the gate driver at least scans the first row of sub-pixels.
2. The display panel according to claim 1, wherein the timing controller comprises:
the image detection element is used for receiving a frame of image data to be displayed and identifying the display gray scale of each sub-pixel in the image data to be displayed;
the judging element is electrically connected with the picture detecting element and is used for judging whether the image data to be displayed comprises a plurality of lines of black image data arranged at intervals according to the identification result of the picture detecting element; when the judging element judges that the image data to be displayed does not comprise a plurality of lines of black image data arranged at intervals, a first adjusting instruction is sent; when the judging element judges that the image data to be displayed comprises a plurality of lines of black image data which are arranged at intervals, a second adjusting instruction is sent;
the reference clock generating element is electrically connected with the judging element and is used for generating a reference pulse signal, and the reference pulse signal has a first pulse width L;
a clock signal generating element electrically connected to the judging element and the reference clock generating element; the clock signal generating element is configured to calculate a first rising time and a first falling time of a first clock signal of M clock signals according to the first adjustment instruction, the second adjustment instruction, and the reference pulse signal, and generate the M clock signals, where the M clock signals are sequentially delayed and overlapped.
3. The display panel of claim 2, wherein the clock signal generating element is specifically configured to calculate a first rising time Tr1_ a and a first falling time Tf1_ a of a first clock signal of M clock signals, which have the same pulse width S and are sequentially delayed by H, according to the first adjustment command and the reference pulse signal, and generate the M clock signals, wherein Tr1_ a is equal to n ×L, Tf1_ a is equal to M ×L, Tf1_ a is equal to Tr1_ a is equal to S, S is equal to M × H, n is equal to or greater than 1, M is equal to or greater than 1, and n and M are integers.
4. The display panel of claim 2, wherein the clock signal generating element is specifically configured to calculate a first rising time Tr1_ b and a first falling time Tf1_ b of a first clock signal of the M clock signals according to the second adjustment command and the reference pulse signal, and generate the M clock signals; wherein the first clock signal has a pulse width S1; the M clock signals are delayed in sequence and the pulse widths are increased in sequence, and the Mth clock signal has a pulse width SM，0＜SMM × H is not more than M, Tr1_ b is not less than i ×L, Tf1_ b is not less than j ×L, Tf1_ a-Tr1_ a is not less than S1, S1 is more than 0 and not more than H, i is not less than 1, j is not less than 1, and i and j are integers.
5. The display panel according to claim 1, wherein the display panel further comprises an image processor; the image processor is used for forming image data to be displayed.
6. The display panel according to claim 1, wherein the display panel comprises N rows of sub-pixels and a plurality of gate driving groups; the first group of the grid driving group comprises M non-cascaded shift registers which are arranged in sequence; the output end of the Q & ltth & gt shift register is electrically connected with the input end of the Q & lt + 3& gt shift register; q is not less than 1 and is an integer;
the clock signal generating element is provided with M clock signal ends, the display panel further comprises a plurality of phase inverters, one clock signal end is electrically connected with the Q & ltth & gt shift register and the input end of one phase inverter, and the output end of the phase inverter is electrically connected with the Q & lt + 3& gt shift register.
7. A control method of a display panel for controlling the display panel according to any one of claims 1 to 6; the display panel is provided with a display area and a peripheral area positioned on at least one side of the display area; the display panel comprises N rows of sub-pixels positioned in the display area; the control method is characterized by comprising the following steps:
receiving a frame of image data to be displayed;
when the image data to be displayed comprises a plurality of rows of black image data arranged at intervals, the scanning time for scanning each row of sub-pixels by the gate driver is controlled to be a first scanning time T1, and the scanning time for scanning at least every M rows of sub-pixels arranged at intervals is sequentially delayed and overlapped, wherein T1 is M × H, H is 1/(f × N), f is a scanning frequency, when the image data to be displayed comprises the plurality of rows of black image data arranged at intervals except the first row of sub-pixels, the scanning time for scanning the first row of sub-pixels by the gate driver is controlled to be H, the scanning time for scanning the plurality of sub-pixels arranged sequentially with the first row of sub-pixels is sequentially delayed, and the scanning time is less than or equal to the first scanning time T1;
providing a first row of data voltages to the first row of subpixels at least while scanning the first row of subpixels.
8. The control method according to claim 7,
identifying the display gray scale of each sub-pixel in the image data to be displayed, and outputting an identification result;
judging whether the image data to be displayed comprises a plurality of lines of black image data arranged at intervals according to the identification result; when the judging element judges that the image data to be displayed does not comprise a plurality of lines of black image data arranged at intervals, a first adjusting instruction is sent; when the judging element judges that the image data to be displayed comprises a plurality of lines of black image data which are arranged at intervals, a second adjusting instruction is sent;
generating a reference pulse signal having a first pulse width L;
and calculating the first rising time and the first falling time of the first clock signal in the M clock signals according to the first adjusting instruction, the second adjusting instruction and the reference pulse signal, and generating the M clock signals, wherein the M clock signals are delayed and overlapped in sequence.
9. The control method according to claim 8,
and calculating a first rising time Tr1_ a and a first falling time Tf1_ a of a first clock signal in M clock signals according to the first adjusting instruction and the reference pulse signal, and generating the M clock signals, wherein the pulse widths S of the M clock signals are the same, and the M clock signals are sequentially delayed by H, wherein Tr1_ a is equal to n ×L, Tf1_ a is equal to M ×L, Tf1_ a-Tr1_ a is equal to S, S is equal to M × H, n is equal to or larger than 1, M is equal to or larger than 1, and n and M are integers.
10. The control method according to claim 8,
calculating a first rising time Tr1_ b and a first falling time Tf1_ b of a first clock signal of the M clock signals according to the second adjustment command and the reference pulse signal, and generating the M clock signals; wherein the first clock signal has a pulse width S1, 0& lt S1 & lt H; the M clock signals are delayed in sequence and the pulse widths are increased in sequence, and the Mth clock signal has a pulse width SM，0＜SMM × H is not more than, Tr1_ b is i ×L, Tf1_ b is j ×L, i is not less than 1, Tf1_ a-Tr1_ a is S1, 0 is more than S1 and not more than H, j is not less than 1, and i and j are integers.
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|---|---|---|---|---|
| CN112967695A (en) * | 2021-03-19 | 2021-06-15 | 武汉京东方光电科技有限公司 | Driving device and driving method of liquid crystal display module and liquid crystal display device |
| WO2023005596A1 (en) * | 2021-07-30 | 2023-02-02 | 京东方科技集团股份有限公司 | Display panel driving method, display panel, and display apparatus |
| WO2023019866A1 (en) * | 2021-08-16 | 2023-02-23 | 惠科股份有限公司 | Driving circuit of display panel and driving device |
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| CN106898325A (en) * | 2017-04-27 | 2017-06-27 | 南京中电熊猫平板显示科技有限公司 | Liquid crystal display faceplate device and its driving method |
| CN110910834A (en) * | 2019-12-05 | 2020-03-24 | 京东方科技集团股份有限公司 | Source driver, display panel, control method of display panel and display device |
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| CN106898325A (en) * | 2017-04-27 | 2017-06-27 | 南京中电熊猫平板显示科技有限公司 | Liquid crystal display faceplate device and its driving method |
| CN110910834A (en) * | 2019-12-05 | 2020-03-24 | 京东方科技集团股份有限公司 | Source driver, display panel, control method of display panel and display device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112967695A (en) * | 2021-03-19 | 2021-06-15 | 武汉京东方光电科技有限公司 | Driving device and driving method of liquid crystal display module and liquid crystal display device |
| WO2023005596A1 (en) * | 2021-07-30 | 2023-02-02 | 京东方科技集团股份有限公司 | Display panel driving method, display panel, and display apparatus |
| US12205507B2 (en) | 2021-07-30 | 2025-01-21 | Wuhan Boe Optoelectronics Technology Co.,Ltd. | Display panel driving method, display panel, and display apparatus |
| WO2023019866A1 (en) * | 2021-08-16 | 2023-02-23 | 惠科股份有限公司 | Driving circuit of display panel and driving device |
| US11978377B2 (en) | 2021-08-16 | 2024-05-07 | HKC Corporation Limited | Driving circuit and driving device for display panel |
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| Publication number | Publication date |
|---|---|
| CN111508448B (en) | 2022-03-18 |
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