[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

CN111463263B - Low gate charge device with field plate structure and method of fabricating the same - Google Patents

Low gate charge device with field plate structure and method of fabricating the same Download PDF

Info

Publication number
CN111463263B
CN111463263B CN202010350874.5A CN202010350874A CN111463263B CN 111463263 B CN111463263 B CN 111463263B CN 202010350874 A CN202010350874 A CN 202010350874A CN 111463263 B CN111463263 B CN 111463263B
Authority
CN
China
Prior art keywords
gate
layer
oxide layer
region
field plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010350874.5A
Other languages
Chinese (zh)
Other versions
CN111463263A (en
Inventor
吴健
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Bright Power Semiconductor Co Ltd
Original Assignee
Shanghai Bright Power Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Bright Power Semiconductor Co Ltd filed Critical Shanghai Bright Power Semiconductor Co Ltd
Publication of CN111463263A publication Critical patent/CN111463263A/en
Priority to TW110101899A priority Critical patent/TWI775279B/en
Application granted granted Critical
Publication of CN111463263B publication Critical patent/CN111463263B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66689—Lateral DMOS transistors, i.e. LDMOS transistors with a step of forming an insulating sidewall spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Non-Volatile Memory (AREA)

Abstract

The invention relates to a low-grid charge device with a field plate structure and a manufacturing method thereof, belonging to the technical field of semiconductors. In the low-gate charge device with the field plate structure, the polycrystalline silicon deposition layer is divided into two parts which are separated from each other, and the first polycrystalline silicon deposition layer is used as a gate; the second polysilicon deposition layer is used as a control grid connected with the source electrode, so that the overlapping area of the grid and the drift region is reduced, and meanwhile, the control grid is used for shielding grid leakage capacitance, so that the grid leakage capacitance is reduced, and the low-grid charge device with the field plate structure is more suitable for the purpose of high-frequency application.

Description

Low gate charge device with field plate structure and method of fabricating the same
Technical Field
The invention relates to the technical field of semiconductors, in particular to the technical field of field effect transistors, and particularly relates to a low-gate charge device with a field plate structure and a manufacturing method thereof.
Background
Prior art device structures with field plate designs are shown in fig. 1 and 2, and fig. 2 is a cross-sectional view 200 of device 100 of fig. 1 taken along a-a'. The device includes a substrate 102, an N-type drift drain region (NDD)103, a P-body region 104, a P + doped region 105, an N + doped region 106, an oxide layer 107, a polysilicon layer 108, an N + doped region 109, a high voltage oxide layer 110, and a gate 112. The polysilicon layer (poly)108 on the high voltage Oxide (HV-Oxide)110 is used as a field plate structure to improve the breakdown performance; the larger polysilicon Gate (Poly Gate)112 area helps to accumulate electrons in the drift region (NDD)103 under the polysilicon region in the ON-state (ON-state), thereby reducing the drain-source ON-resistance (Rdson). However, since the overlapping area of the gate 112 and the drift region 103 is large, the miller capacitance (gate-drain capacitance Cgd) of the gate and the drain is large. The larger the gate-drain capacitance Cgd, the larger the power loss, and thus it is difficult to apply to high-frequency applications requiring the gate-drain capacitance Cgd as small as possible.
Therefore, a device with a smaller gate-to-drain capacitance Cgd must be provided to meet the requirements of high frequency applications.
Disclosure of Invention
The present invention is directed to overcoming the above-mentioned drawbacks of the prior art, and providing a low gate charge device having a field plate structure and a method for manufacturing the same, in which a polysilicon layer is divided into two parts, one part is used as a gate and the other part is used as a control gate, thereby reducing the overlapping area of the gate and a drift region to reduce a gate-to-drain capacitance Cgd, making it more suitable for high frequency applications.
In order to achieve the above object, the low gate charge device having a field plate structure of the present invention has the following configuration:
a substrate;
the N-type drift drain region covers the substrate;
the P-body region is formed in a partial region on the top of the N-type drift drain region;
the N-type drift drain region is formed in the other part of the region on the top of the N-type drift drain region;
a gate oxide layer including a first gate oxide layer covering the P-body region and a portion of the N-doped region, and a second gate oxide layer covering a portion of the N-doped region and a portion of the N-type drift drain region;
the polycrystalline silicon deposition layer comprises a first polycrystalline silicon deposition layer covering the first grid oxide layer and a second polycrystalline silicon deposition layer covering the second grid oxide layer, the first polycrystalline silicon deposition layer serves as a grid, and the second polycrystalline silicon deposition layer serves as a control grid;
the side wall layers are arranged on two sides of the first polycrystalline silicon deposition layer and two sides of the second polycrystalline silicon deposition layer;
the P + doped region and the first N + doped region are formed at the top of the P-body region and used as source electrodes;
the second N + doped region is formed at the top of the N-type drift drain region and is used as a drain;
a silicide layer comprising a first silicide layer formed over the source region, a second silicide layer over the first polysilicon deposit layer, a third silicide layer over the second polysilicon deposit layer, and a fourth silicide layer over the drain region.
The low-gate charge device with the field plate structure further comprises: and the high-voltage oxide layer is positioned between the N-type drift drain region and the second polysilicon deposition layer. Or may further include: and the silicon local oxide layer or the shallow trench isolation is formed on the top of the N-type drift drain region and is positioned below the second polysilicon deposition layer.
In the low-gate charge device with the field plate structure, the high-voltage oxide layer can be arranged on the N-type drift drain region and a part of the N-doped region, and the second gate oxide layer is not arranged.
In the low-gate charge device with the field plate structure, the first polysilicon deposition layer can be arranged on the first gate oxide layer and part of the high-voltage oxide layer.
In the low-gate charge device with the field plate structure, the gate and the control gate are physically separated, and the control gate is electrically connected to the source electrode.
In the low-grid charge device with the field plate structure, the grid electrode is connected with a grid electrode driving circuit, and the control grid is connected with a control grid driving circuit. The grid control signal is connected with the grid through the grid driving circuit, a new control signal is generated after the grid control signal passes through the voltage detection module and the voltage regulation module, and the new control signal is connected with the control grid through the control grid driving circuit.
In the low-gate charge device with the field plate structure, the polysilicon deposition layer further comprises at least one third polysilicon deposition layer used as a control gate, and the third polysilicon deposition layer covers the second gate oxide layer. And the control gates formed by the third polysilicon deposition layer are connected with respective corresponding control gate drive circuits.
The low-gate charge device with the field plate structure also comprises a silicide blocking layer which is arranged on a part of the high-voltage oxidation layer, a part of the second polysilicon deposition layer and the side wall layer on one side of the second polysilicon deposition layer.
The invention also provides a manufacturing method of the low-gate charge device with the field plate structure, which comprises the following steps:
forming an N-type drift drain region over a substrate;
forming a grid oxide layer on the N-type drift drain region, wherein the grid oxide layer comprises a first grid oxide layer and a second grid oxide layer;
respectively performing polysilicon deposition and etching on the first gate oxide layer and the second gate oxide layer to form a first polysilicon deposition layer covering the first gate oxide layer as a gate; forming a second polysilicon deposition layer covering the second gate oxide layer as a control gate;
a P-body region is formed in a part of the region on the top of the N-type drift drain region in an injection mode, and an N-doped region is formed in another part of the region on the top of the N-type drift drain region in an injection mode;
forming sidewall layers on two sides of the first polysilicon deposition layer and two sides of the second polysilicon deposition layer;
forming a P + doped region and a first N + doped region at the top of the P-body region as a source electrode;
and forming a second N + doped region on the top of the N-type drift drain region to serve as a drain.
Forming a first silicide layer on the source region, forming a second silicide layer on the first polysilicon deposition layer, forming a third silicide layer on the second polysilicon deposition layer, and forming a fourth silicide layer on the drain region.
In the manufacturing method of the low-gate charge device with the field plate structure, before the gate oxide layer is formed, the following steps are further included:
forming a high-voltage oxide layer on the N-type drift drain region or forming a silicon local oxide layer or shallow trench isolation on the top of the N-type drift drain region;
the high-voltage oxide layer, the silicon local oxide layer or the shallow trench isolation is positioned below the second polysilicon deposition layer.
The low-gate charge device with the field plate structure and the manufacturing method thereof are adopted, the polycrystalline silicon deposition layer is divided into two parts which are separated from each other, and the first polycrystalline silicon deposition layer is used as a gate; the second polysilicon deposition layer is used as a control grid connected with the source electrode, so that the overlapping area of the grid and the drift region is reduced, and meanwhile, the control grid is used for shielding grid leakage capacitance, so that the grid leakage capacitance is reduced, and the low-grid charge device with the field plate structure is more suitable for the purpose of high-frequency application.
Drawings
Fig. 1 is a schematic diagram of a device structure with a field plate design in the prior art.
Fig. 2 is a cross-sectional view of the device of fig. 1 taken along the direction a-a'.
Fig. 3 is a schematic structural view of a low gate charge device having a field plate structure according to the present invention.
Fig. 4 is a structural schematic diagram of step one of the method of fabricating a low gate charge device with a field plate structure of the present invention.
Fig. 5 is a structural diagram of step two of the method for manufacturing a low-gate charge device with a field plate structure according to the present invention.
Fig. 6 is a structural schematic diagram of step three of the method of manufacturing a low gate charge device with a field plate structure of the present invention.
Fig. 7 is a structural schematic diagram of step four of the method of manufacturing a low-gate charge device with a field plate structure of the present invention.
Fig. 8 is a schematic structural diagram of step five of the method of fabricating a low gate charge device with a field plate structure of the present invention.
Fig. 9 is a schematic diagram of a first alternative of the low gate charge device of the present invention having a field plate structure.
Fig. 10 is a schematic diagram of a second alternative of the low gate charge device of the present invention having a field plate structure.
Fig. 11 is a schematic diagram of a third alternative of the low gate charge device of the present invention having a field plate structure.
Fig. 12 is a schematic diagram of the field plate structure parasitic capacitance of a prior art device with a field plate design.
Fig. 13 is a field plate structure parasitic capacitance diagram of a low gate charge device having a field plate structure of the present invention.
Fig. 14 is a schematic diagram of a low gate charge device connection driving circuit with a field plate structure of the present invention.
Fig. 15 is a schematic diagram of an alternative driving circuit of fig. 14.
Fig. 16 is a schematic diagram of another alternative of the driving circuit of fig. 14.
Fig. 17 is a schematic of the structure of a low gate charge device of the present invention having multiple control gates.
Fig. 18 is a schematic diagram of an alternative embodiment of a low gate charge device having a field plate structure in accordance with the present invention.
Fig. 19 is a schematic diagram of an alternative embodiment of a low gate charge device having a field plate structure in accordance with the present invention.
Fig. 20 is a schematic diagram of the structure of a low gate charge device of the present invention having a silicide blocking layer.
Detailed Description
In order to clearly understand the technical contents of the present invention, the following examples are given in detail.
In the drawings, "N" or "P" is a doping type, and "-" or "+" immediately after the doping type indicates a relative doping concentration. For example, "N +" means a doping concentration higher than that of the "N" doped region, and correspondingly "N-" means a doping concentration lower than that of the "N" doped region. Doped regions having the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "N +" doped regions may have the same or different doping concentrations.
As previously mentioned, to meet the requirements of high frequency applications, the gate-drain capacitance Cgd must be reduced.
In practical application, three sets of capacitors are usually used to evaluate the AC characteristics of the device, namely, an input capacitor Ciss (Ciss + Cgd), an output capacitor Coss (Coss + Cds + Cgd) and a feedback capacitor Crss (Crss + Cgd).
In one embodiment, the structure of a low gate charge device 300 with a field plate structure of the present invention is shown in fig. 3. It includes:
a P-substrate 302;
an N-type drift drain (NDD) region 303 overlying the substrate 302;
a P-Body (P-Body)309 formed in a partial region on top of the N-type drift drain region 303;
an N-doped region 310 formed in another partial region on top of the N-type drift drain region 303;
gate oxide layers 305, 306, including a first gate oxide layer 305 overlying the P-body 309 and a portion of the N-doped region 310, and a second gate oxide layer 306 overlying a portion of the N-doped region 310 and a portion of the N-drift drain region 303;
a high voltage Oxide (HV-Oxide) layer 304 covering the N-type drift drain region 303;
polysilicon deposits 307, 308, including a first polysilicon deposit 307 overlying the first Gate oxide 305, as a Gate (Gate); and a second polysilicon deposition layer 308 covering the second Gate oxide layer 306 as a Control Gate (Control Gate);
a P + doped region 312 and a first N + doped region 313 formed on the top of the P-body 309 for serving as a Source (Source) connected to the control gate;
a second N + doped region 314 is formed on top of the N-type drift Drain region 303 as a Drain (Drain).
The method for manufacturing the low-gate charge device with the field plate structure of this embodiment is shown in fig. 4 to 8, and includes the following steps:
step one, as shown in the device 400 in fig. 4, forming an N-type drift drain region 303 over a substrate 302;
step two, as shown in the device 500 in fig. 5, forming a high voltage oxide layer 304 on the N-type drift drain region 303, and patterning the high voltage oxide layer;
step three, as shown in the device 600 in fig. 6, forming a first gate oxide layer 305 and a second gate oxide layer 306 on the partial region of the N-type drift drain region 303; respectively performing polysilicon deposition and etching on the first gate oxide layer 305, the second gate oxide layer 306 and the high-voltage oxide layer 304 to form a first polysilicon deposition layer 307 covering the first gate oxide layer 305 to serve as a gate; and forming a second polysilicon deposition layer 308 covering the second gate oxide layer 306 and the high voltage oxide layer 304 as a control gate; a P-body region 309 is formed in a partial region on the top of the N-type drift drain region 303 in an injection mode, and an N-doped region 310 is formed in another partial region on the top of the N-type drift drain region 303 in an injection mode;
step four, as shown in the device 700 in fig. 7, a P + doped region 312 and a first N + doped region 313 are formed on the top of the P-body region 309 as a source; forming a second N + doped region 314 on top of the N-type drift drain region 303 as a drain; forming sidewall layers 311a and 311b on both sides of the first polysilicon deposition layer 307, and forming sidewall layers 311c and 311d on both sides of the second polysilicon deposition layer 308;
step five, as shown in the device 800 in fig. 8, a first silicide layer 315c is formed on the source regions 312 and 313 by silicidation and a back-end process, a second silicide layer 315a is formed on the first polysilicon deposition layer 307, a third silicide layer 315b is formed on the second polysilicon deposition layer 308, and a fourth silicide layer 315d is formed on the drain region 314.
Other structures may be substituted for the high voltage oxide layer 304 for compatibility with existing process platforms.
In a first alternative, as shown in device 900 of fig. 9, the high voltage oxide layer is replaced by a Local Oxidation of Silicon (LOCOS) 901. The remainder of the device 900 is the same as the device 800 shown in fig. 8.
Accordingly, in the device manufacturing method of this alternative embodiment, step two is to form the local silicon oxide layer 901 over the N-type floating drain region 303 by using local silicon oxidation.
In a second alternative, the high voltage oxide layer is replaced by a gate oxide layer 1002, as shown in device 1000 in fig. 10. The gate oxide layer 1002 also includes the second gate oxide layer 306 that is originally disposed over the N-doped region 310 and a portion of the N-drift drain region 303. The gate oxide layer 1002 is covered with a polysilicon deposition layer 1003 to serve as a control gate. Over the polysilicon deposition layer 1003 is a silicide layer 1004. Sidewall layers 1001a and 1001b are provided on both sides of the polysilicon deposition layer 1003.
Accordingly, in the device manufacturing method of this alternative embodiment, the second step of forming the high voltage oxide layer 304 in the above embodiment is not included. Instead, in step three, a gate oxide layer 1002 is formed over a portion of the N-type drift drain region 303 and covering a majority of the N-type drift drain region 303.
In a third alternative, shown in the device 1100 of fig. 11, the high voltage oxide layer is replaced by a Shallow Trench Isolation (STI) 1101 on top of the N-type drift drain region 303. Similar to the second alternative described above, this scheme also includes a gate oxide layer 1002. The gate oxide layer 1002 includes the second gate oxide layer 306 originally disposed over the N-doped region 310 and a portion of the N-drift drain region 303, and also covers a portion of the shallow trench isolation 1101. The gate oxide layer 1002 is covered with a polysilicon deposition layer 1003 as a control gate. Over the polysilicon deposition layer 1003 is a silicide layer 1004. Sidewall layers 1001a and 1001b are provided on both sides of the polysilicon deposition layer 1003.
Accordingly, in the device manufacturing method of this alternative embodiment, step two is to dispose shallow trench isolation 1101 on top of the N-type drift drain region 303. And in step three, a gate oxide layer 1002 is formed over a portion of the N-type floating drain region 303 and covering the top of the shallow trench isolation 1101.
The field plate structure parasitic capacitance of the low-gate charge device with the field plate structure formed by the above embodiment and the corresponding alternative is shown in fig. 13. In contrast to the prior art as shown in fig. 12, since the polysilicon deposition layer is divided into two portions, a first polysilicon deposition layer 307 and a second polysilicon deposition layer 308, wherein the first polysilicon deposition layer 307 serves as a gate and the second polysilicon deposition layer 308 serves as a control gate, the gate and the control gate are physically separated, and the control gate is electrically connected to the source. Therefore, the area of the gate electrode covering the drain electrode is obviously reduced, the area of the gate-drain capacitance Cgd is directly reduced, and meanwhile, the gate-drain capacitance is shielded by the control gate. The purposes of reducing the gate-drain capacitance Cgd, reducing power loss and enabling the device to meet high-frequency application are achieved.
In a preferred embodiment, the low gate charge device with field plate structure of the present invention, as shown in fig. 14, includes a gate driving circuit 1402 connected to the gate, and a control gate driving circuit 1404 connected to the control gate. The device 1400 of fig. 14 is shown with the same structure as the device 800 of fig. 8, but it should be noted that the devices 900, 1000, 1100 of fig. 9, 10, 11 may all use the same gate driver circuit 1402 and control gate driver circuit 1404.
Further, as shown in the device structure 1500 in fig. 15, the gate control circuit 1402 and the control gate driving circuit 1404 may be derived from the same gate signal 1501, so that the gate and the control gate can be turned on or off synchronously.
Further, as shown in the device structure 1600 of fig. 16, a gate signal 1501 passes through a voltage detection module 1601 and a voltage regulation module 1602 to generate a new control signal 1603, and the new control signal 1603 is connected to the control gate through a control gate driving circuit 1404.
In the above embodiments, the control gate is connected to a corresponding driving circuit, which can be matched with the gate driving circuit to complete a specific application. For example, this driving circuit may provide a high potential to accumulate electrons to reduce drain-source ON-resistance (Rdson) in an ON-state (ON-state) and a low potential to maintain breakdown performance in an OFF-state (OFF-state).
Meanwhile, as in the above embodiment, the gate-drain capacitance Cgd is shielded by the control gate; the switching loss is mainly caused by the gate-drain capacitance Cgd; the capacitance Cdc between the control gate and the drain has no effect on the power loss.
In an alternative more preferred embodiment, to meet the requirements of higher voltage applications, more than one control gate, 3 in fig. 17, including a first control gate, a second control gate, and a third control gate may be provided as shown in device 1700 in fig. 17.
In the device 1700, there is included:
a high voltage oxide layer 1701 overlying the N-type drift drain region 303, similar to the high voltage oxide layer 304 in the device 800;
a polysilicon deposition layer 307, 1702, 1704, 1706 comprising a first polysilicon deposition layer 307 overlying the first Gate oxide layer 305 as a Gate (Gate); and a second polysilicon deposition layer 1702 covering the second gate oxide layer 306 and a portion of the high voltage oxide layer 1701 as the first control gate CG1, and third polysilicon deposition layers 1704 and 1706 covering a portion of the high voltage oxide layer 1701 as the second control gate CG2 and the third control gate CG3, respectively.
Simultaneously, still include: sidewall layers 311a and 311b disposed on both sides of the first polysilicon deposited layer 307, sidewall layers 1703a and 1703b disposed on both sides of the second polysilicon deposited layer 1702, and sidewall layers 1703c and 1703d and 1703e and 1703f disposed on both sides of the third polysilicon deposited layers 1704 and 1706, respectively; a first silicide layer 315c formed over the source regions 312 and 313, a second silicide layer 315a formed over the first polysilicon deposition layer 307, a third silicide layer 1705a formed over the second polysilicon deposition layer 1702, fourth silicide layers 1705b and 1705c formed over the third polysilicon deposition layers 1704 and 1706, respectively, and a fifth silicide layer 315d formed over the drain region 314.
The device 1700 shown in fig. 17 is shown using only the same structure as the device 800 of fig. 8, but it should be noted that the devices 900, 1000, 1100 shown in fig. 9, 10, 11 can each use the same multiple separate control gate structure.
Different control gates can adopt different control signals; these control signals may come from different control circuits. Also, some control gates may be floating; to obtain different field effects, some control gates may be connected to the source, gate or drain, as required, to improve breakdown performance.
In another alternative preferred embodiment, also to meet the requirements of higher voltage applications, a silicide blocking layer (SAB)2001 may be used to prevent silicide penetration through the high voltage oxide layer 304, as shown in device 2000 in fig. 20, to ensure that breakdown voltage characteristics are not affected.
Specifically, in the device 2000, a silicide blocking layer 2001 is further included, where the silicide blocking layer 2001 covers a portion of the high voltage oxide layer 304 not covered by the second deposited polysilicon layer 308 and also covers a portion of the second deposited polysilicon layer 308 and the sidewall layer 311d on one side thereof.
In addition, in order to adjust the electrical characteristics of the low-gate charge device with the field plate structure, the position relationship between the high-voltage oxide layer and the polysilicon deposition layer can be properly adjusted.
In an alternative embodiment, as shown in fig. 18, in the device 1800, the hving oxide 1801 extends to the gate side and is disposed on the N-type drift drain region 303 and a portion of the N-doped region 310 without the second gate oxide 306 of the previous embodiments.
In yet another alternative embodiment, shown in FIG. 19, the device 1900 is similar to the device 1800 with the high voltage oxide layer 1901 extending to the gate side. This embodiment does not have the N-doped region 310, and the high voltage oxide layer 1901 completely covers the N-type drift drain region 303. Meanwhile, a first polysilicon deposition layer 1907 covers the first gate oxide layer 305 and a portion of the high voltage oxide layer 1901.
Accordingly, the methods of fabricating the devices 1800, 1900 of the two alternative embodiments described above are similar to the method of fabricating the device 300, except that the method of fabricating the device 1800 does not include the step of forming the second gate oxide layer 306, and the method of fabricating the device 1900 does not include the step of forming the N-doped region 310.
The low-gate charge device with the field plate structure and the manufacturing method thereof are adopted, the polycrystalline silicon deposition layer is divided into two parts which are separated from each other, and the first polycrystalline silicon deposition layer is used as a gate; the second polysilicon deposition layer is used as a control grid connected with the source electrode, so that the overlapping area of the grid and the drift region is reduced, and meanwhile, the control grid is used for shielding grid leakage capacitance, so that the grid leakage capacitance is reduced, and the low-grid charge device with the field plate structure is more suitable for the purpose of high-frequency application.
In this specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims (11)

1. A low gate charge device having a field plate structure, comprising:
a substrate;
the N-type drift drain region covers the substrate;
the P-body region is formed in a partial region on the top of the N-type drift drain region;
the N-type drift drain region is formed in the other part of the region on the top of the N-type drift drain region;
a gate oxide layer including a first gate oxide layer covering the P-body region and a portion of the N-doped region, and a second gate oxide layer covering a portion of the N-doped region and a portion of the N-type drift drain region;
the polycrystalline silicon deposition layer comprises a first polycrystalline silicon deposition layer covering the first grid oxide layer and a second polycrystalline silicon deposition layer covering the second grid oxide layer, the first polycrystalline silicon deposition layer serves as a grid, and the second polycrystalline silicon deposition layer serves as a control grid;
the high-voltage oxide layer is positioned between the N-type drift drain region and the second polycrystalline silicon deposition layer;
the side wall layers are arranged on two sides of the first polycrystalline silicon deposition layer and two sides of the second polycrystalline silicon deposition layer;
the P + doped region and the first N + doped region are formed at the top of the P-body region and used as source electrodes;
the second N + doped region is formed at the top of the N-type drift drain region and is used as a drain;
a silicide layer comprising a first silicide layer formed over the source region, a second silicide layer over the first polysilicon deposit layer, a third silicide layer over the second polysilicon deposit layer, and a fourth silicide layer over the drain region.
2. The low-gate charge device with a field plate structure of claim 1,
the high-voltage oxide layer is arranged on the N-type drift drain region and a part of the N-doped region and is not provided with the second grid oxide layer.
3. The low gate charge device with field plate structure of claim 2,
the first polysilicon deposition layer is arranged on the first grid oxide layer and part of the high-voltage oxide layer.
4. A low gate charge device having a field plate structure according to any of claims 1 to 3, wherein the gate and the control gate are physically separated, the control gate being electrically connected to the source.
5. A low-gate charge device with a field plate structure according to claim 4, wherein said gate is connected to a gate drive circuit and said control gate is connected to a control gate drive circuit.
6. The low-gate charge device with a field plate structure of claim 5, wherein a gate control signal is connected to the gate through the gate driving circuit, the gate control signal generates a new control signal after passing through the voltage detection module and the voltage regulation module, and the new control signal is connected to the control gate through the control gate driving circuit.
7. The low-gate charge device with a field plate structure of claim 6,
the polysilicon deposition layer also comprises at least one third polysilicon deposition layer used as a control gate, and the third polysilicon deposition layer covers the second gate oxide layer.
8. A low gate charge device with a field plate structure as claimed in claim 7, wherein the control gates formed by said third polysilicon deposition layer are connected to respective control gate drive circuits.
9. The low gate charge device with field plate structure of claim 6, further comprising:
and the silicide barrier layer is arranged on part of the high-voltage oxidation layer, part of the second polycrystalline silicon deposition layer and the side wall layer on one side of the second polycrystalline silicon deposition layer.
10. A method of fabricating a low gate charge device having a field plate structure, comprising:
forming an N-type drift drain region over a substrate;
forming a grid oxide layer on the N-type drift drain region, wherein the grid oxide layer comprises a first grid oxide layer and a second grid oxide layer;
respectively performing polysilicon deposition and etching on the first gate oxide layer and the second gate oxide layer to form a first polysilicon deposition layer covering the first gate oxide layer as a gate; forming a second polysilicon deposition layer covering the second gate oxide layer as a control gate;
injecting and forming a P-body region in a partial region on the top of the N-type drift drain region, and injecting and forming an N-doped region in another partial region on the top of the N-type drift drain region;
forming sidewall layers on two sides of the first polysilicon deposition layer and two sides of the second polysilicon deposition layer;
forming a P + doped region and a first N + doped region at the top of the P-body region as a source electrode;
forming a second N + doped region on the top of the N-type drift drain region to serve as a drain;
forming a first silicide layer on the source region, forming a second silicide layer on the first polysilicon deposition layer, forming a third silicide layer on the second polysilicon deposition layer, and forming a fourth silicide layer on the drain region.
11. The method of claim 10, wherein the field plate structure is formed by a field plate process,
before the gate oxide layer is formed, the method further comprises the following steps:
forming a high-voltage oxide layer on the N-type drift drain region or forming a silicon local oxide layer or shallow trench isolation on the top of the N-type drift drain region;
the high-voltage oxide layer, the silicon local oxide layer or the shallow trench isolation is positioned below the second polysilicon deposition layer.
CN202010350874.5A 2020-01-22 2020-04-28 Low gate charge device with field plate structure and method of fabricating the same Active CN111463263B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW110101899A TWI775279B (en) 2020-01-22 2021-01-19 Low gate charge device with field plate structure and manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010073638 2020-01-22
CN2020100736383 2020-01-22

Publications (2)

Publication Number Publication Date
CN111463263A CN111463263A (en) 2020-07-28
CN111463263B true CN111463263B (en) 2022-07-01

Family

ID=71678610

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010350874.5A Active CN111463263B (en) 2020-01-22 2020-04-28 Low gate charge device with field plate structure and method of fabricating the same

Country Status (2)

Country Link
CN (1) CN111463263B (en)
TW (1) TWI775279B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112652665A (en) * 2020-12-22 2021-04-13 时磊 Device with fully silicided gate and method of making the same
US11374096B1 (en) * 2021-01-04 2022-06-28 Vanguard International Semiconductor Corporation High voltage semiconductor device
US20220262907A1 (en) * 2021-02-12 2022-08-18 Nuvolta Technologies (Hefei) Co., Ltd. Lateral Double Diffused MOS Device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005311208A (en) * 2004-04-23 2005-11-04 Sharp Corp Solid-state imaging element, manufacturing method therefor, and electronic information apparatus
CN108735811A (en) * 2017-04-24 2018-11-02 株式会社东芝 Semiconductor device, power circuit and computer
CN110289315A (en) * 2018-03-19 2019-09-27 旺宏电子股份有限公司 High voltage transistor device with double step field plate structure

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7910991B2 (en) * 2008-03-31 2011-03-22 Freescale Semiconductor, Inc. Dual gate lateral diffused MOS transistor
US9177953B2 (en) * 2013-10-31 2015-11-03 Taiwan Semiconductor Manufacturing Company Limited Circular semiconductor device with electrostatic discharge (ESD) device and functional device
US9443967B1 (en) * 2015-03-13 2016-09-13 Macronix International Co., Ltd. Semiconductor device having metal layer and method of fabricating same
US9905428B2 (en) * 2015-11-02 2018-02-27 Texas Instruments Incorporated Split-gate lateral extended drain MOS transistor structure and process
US10217826B2 (en) * 2016-11-20 2019-02-26 Tower Semiconductor Ltd. Apparatus of a metal-oxide-semiconductor (MOS) transistor including a multi-split gate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005311208A (en) * 2004-04-23 2005-11-04 Sharp Corp Solid-state imaging element, manufacturing method therefor, and electronic information apparatus
CN108735811A (en) * 2017-04-24 2018-11-02 株式会社东芝 Semiconductor device, power circuit and computer
CN110289315A (en) * 2018-03-19 2019-09-27 旺宏电子股份有限公司 High voltage transistor device with double step field plate structure

Also Published As

Publication number Publication date
TWI775279B (en) 2022-08-21
TW202143484A (en) 2021-11-16
CN111463263A (en) 2020-07-28

Similar Documents

Publication Publication Date Title
US10319848B2 (en) Vertical DMOS transistor
CN111463263B (en) Low gate charge device with field plate structure and method of fabricating the same
TWI509798B (en) Structure and method for forming shielded gate trench fet with multiple channels
US8889512B2 (en) Method and device including transistor component having a field electrode
US8310007B2 (en) Integrated power supplies and combined high-side plus low-side switches
TWI813734B (en) Laterally diffused mosfet with low rsp*qg product
US7109562B2 (en) High voltage laterally double-diffused metal oxide semiconductor
US8823093B2 (en) High-voltage transistor structure with reduced gate capacitance
CN1661812A (en) High voltage LDMOS transistor having an isolated structure
KR20050077015A (en) Semiconductor device
WO2010008617A1 (en) Mosfet switch with embedded electrostatic charge
CN111223930A (en) Shielded gate trench MOSFET
CN116031303B (en) Super junction device, manufacturing method thereof and electronic device
US20240204056A1 (en) Silicon carbide semiconductor device
CN114171595A (en) Semiconductor device with a plurality of semiconductor chips
CN109427882B (en) Trench gate MOSFET with shield gate and manufacturing method thereof
US9508846B2 (en) Vertical MOS semiconductor device for high-frequency applications, and related manufacturing process
EP4184590B1 (en) Semiconductor device
KR102331471B1 (en) high power semiconductor device and fabrication method therof
JPH02106973A (en) Semiconductor device
KR20120060807A (en) High-voltage transistor structure with reduced gate capacitance

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right

Effective date of registration: 20211207

Address after: 201306 building C, No. 888, Huanhu West 2nd Road, Lingang New District, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai

Applicant after: Lilaito semiconductor (Shanghai) Co.,Ltd.

Address before: 200052 No. 900, Changning District, Shanghai, West Yan'an Road

Applicant before: Wu Jian

TA01 Transfer of patent application right
TA01 Transfer of patent application right

Effective date of registration: 20220525

Address after: 201206 unit 102, floor 9-12, No.3, Lane 5005, Shenjiang Road, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai

Applicant after: SHANGHAI BRIGHT POWER SEMICONDUCTOR Co.,Ltd.

Address before: 201306 building C, No. 888, Huanhu West 2nd Road, Lingang New District, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai

Applicant before: Lilaito semiconductor (Shanghai) Co.,Ltd.

TA01 Transfer of patent application right
GR01 Patent grant
GR01 Patent grant
PE01 Entry into force of the registration of the contract for pledge of patent right

Denomination of invention: Low gate charge device with field plate structure and method of making the same

Effective date of registration: 20220829

Granted publication date: 20220701

Pledgee: CITIC Bank Limited by Share Ltd. Shanghai branch

Pledgor: SHANGHAI BRIGHT POWER SEMICONDUCTOR Co.,Ltd.

Registration number: Y2022310000210

PE01 Entry into force of the registration of the contract for pledge of patent right