CN111465147A - L ED control drive circuit with multiplexed ports - Google Patents
L ED control drive circuit with multiplexed ports Download PDFInfo
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- CN111465147A CN111465147A CN202010396637.2A CN202010396637A CN111465147A CN 111465147 A CN111465147 A CN 111465147A CN 202010396637 A CN202010396637 A CN 202010396637A CN 111465147 A CN111465147 A CN 111465147A
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- 238000004891 communication Methods 0.000 claims description 28
- 239000003381 stabilizer Substances 0.000 claims description 17
- 239000011159 matrix material Substances 0.000 claims description 6
- 238000000034 method Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 239000002985 plastic film Substances 0.000 description 1
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
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Abstract
The invention discloses a L ED control driving circuit with multiplexed ports, which belongs to the technical field of integrated circuits and comprises a L ED key array, a plurality of driving ports, a plurality of key public ports, a clock generator and a scanning control module, wherein the plurality of driving ports are arranged on the right side of the L ED key array, the plurality of key public ports are arranged on the right side of the L ED key array, the clock generator is arranged on the right side of the driving ports, and the scanning control module is arranged on the right side of the driving ports.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to an L ED control drive circuit with multiplexed ports.
Background
An integrated circuit is a microelectronic device or component. The transistor, the resistor, the capacitor, the inductor and other elements and wires required in a circuit are interconnected together by adopting a certain process, are manufactured on a small or a plurality of small semiconductor wafers or medium substrates, and are then packaged in a tube shell to form a micro structure with the required circuit function; all the elements are structurally integrated, so that the electronic elements are greatly miniaturized, low in power consumption, intelligent and high in reliability. It is denoted by the letter "IC" in the circuit. The integrated circuit inventors are the Jack-Kerr ratio (germanium (Ge) -based integrated circuits) and the Robert-Noisy (silicon (Si) -based integrated circuits). Most applications in the semiconductor industry today are silicon-based integrated circuits.
L ED is a common light-emitting device widely used in lighting, indicator lights, displays, etc. at present, plastic film keyboards or mechanical keyboards are used in a large number of electrical appliances, and L ED is used as a display panel or indicator light.
The keyboard and the L ED are used simultaneously, and the conventional method is to use two chips or different pins of the same chip to respectively control the L ED and the keyboard.
Disclosure of Invention
The invention aims to provide an L ED control driving circuit with multiplexed ports, which aims to solve the problems that a keyboard and a L ED need to be used simultaneously in the background art, and the traditional method is to use two chips or different pins of the same chip to respectively control a L ED and the keyboard.
In order to achieve the purpose, the invention provides the following technical scheme that the L ED control driving circuit with multiplexed ports comprises:
l ED key array;
a plurality of drive ports on a right side of the L ED key array, the drive ports electrically connected with the L ED key array;
a plurality of key common ports on the right side of the L ED key array, the key common ports at the lower end of the drive port, the key common ports electrically connected to the L ED key array;
a clock generator to the right of the drive port;
the scanning control module is arranged on the right side of the driving port, the scanning control module is arranged at the lower end of the clock generator, the scanning control module is electrically connected with the clock generator, and the scanning control module is electrically connected with the driving port;
a communication interface to the right of the clock generator;
the RAM module is arranged on the right side of the scanning control module, the RAM module is arranged at the lower end of the communication interface, and the RAM module is electrically connected with the communication interface;
the configuration register is arranged at the lower end of the communication interface, the configuration register is arranged on the right side of the RAM module, and the configuration register is electrically connected with the communication interface;
the current reference module is arranged at the lower end of the scanning control module, the current reference module is arranged on the right side of the driving port, and the current reference module is electrically connected with the driving port;
the constant current power supply is arranged on the right side of the L ED key array, the constant current power supply is arranged at the lower end of the driving port, the constant current power supply is electrically connected with the current reference module, and the constant current power supply is electrically connected with the common port of the keys;
a voltage reference module at a lower end of the current reference module;
the linear voltage stabilizer is arranged at the lower end of the voltage reference module, is arranged on the right side of the constant current power supply, is electrically connected with the voltage reference module and is electrically connected with the constant current power supply;
the voltage comparators are arranged at the lower end of the linear voltage stabilizer, are arranged on the right side of the key public port, are electrically connected with the key public port and are electrically connected with the linear voltage stabilizer;
the key judgment module is arranged on the right side of the voltage comparator, is electrically connected with the scanning control module, and is electrically connected with the driving port;
the key result register is arranged on the right side of the key judgment module and electrically connected with the key judgment module, and the key result register is electrically connected with the communication interface.
Preferably, the L ED key array includes a L ED matrix and a key matrix.
Preferably, two L EDs are connected in parallel between any two of the driving ports, and the two L EDs connected in parallel are opposite in polarity.
Preferably, any one of the driving ports is connected with one end of the keys with the same number as the key public port, and the other end of the key public port is connected with the key public end.
Preferably, the clock generator is electrically connected to a clock control port, and the communication interface is electrically connected to a communication control port.
Compared with the prior art, the invention has the beneficial effects that the time-sharing multiplexing method is cancelled, when the port multiplexing is L ED driving and key driving, L ED driving is always effective, L ED brightness is improved, display effect is enhanced, polarity of current driving is fixed, abnormal display problem is prevented, novel driving time sequence is adopted, and utilization rate of L ED driving port is improved, so that PCB layout difficulty is simplified, and cost is reduced.
Drawings
FIG. 1 is a schematic structural view of the present invention;
FIG. 2 is a schematic diagram of an L ED key array according to the present invention;
FIG. 3 is a schematic diagram of the structure of the driving port and the key common port according to the present invention.
In the figure, a 1L ED key array, a 2 driving port, a 3 key public port, a 4 clock generator, a 5 scanning control module, a 6 communication interface, a 7RAM module, an 8 configuration register, a 9 current reference module, a 10 constant current power supply, an 11 voltage reference module, a 12 linear voltage stabilizer, a 13 voltage comparator, a 14 key judgment module and a 15 key result register are arranged in the keyboard.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a L ED control drive circuit for port multiplexing, which cancels a time-sharing multiplexing method, wherein when the port multiplexing is L ED drive and key drive, L ED drive is always effective, L ED brightness is improved, display effect is enhanced, polarity of current drive is fixed, abnormal display problem is prevented, a novel drive time sequence is adopted, and utilization rate of a L ED drive port is improved, so that PCB layout difficulty is simplified, and cost is reduced;
l ED key array 1 includes L ED matrix and key matrix;
the plurality of driving ports 2 are arranged on the right side of the L ED key array 1, the driving ports 2 are electrically connected with the L ED key array 1, two L EDs are connected between any two driving ports 2 in parallel, the anode and the cathode of the two L EDs connected in parallel are opposite, 2L EDs connected between any two driving ports 2 in parallel are opposite, and the anode and the cathode of the 2L EDs connected in parallel are opposite, so that in a system with N driving ports 2, any one driving port 2 is connected with the anodes of (N-1) L EDs and the cathodes of the other (N-1) L EDs, and N × (N-1) L EDs are contained in the whole system;
referring to fig. 1-3, a plurality of key common ports 3 are arranged on the right side of a L ED key array 1, a key common port 3 is arranged at the lower end of a drive port 2, the key common port 3 is electrically connected with a L ED key array 1, any one drive port 2 is connected with one end of keys with the same number as the key common port 3, the other end of the key common port 3 is connected with the key common port, any one drive port 2 is connected with one end of keys with the same number as the key common port 3, and the other end of the key common port 3 is connected with the key common port, namely, any one key common port 3 is connected with keys with the same number as the drive port 2, therefore, in a system with N drive ports 2 and M key common ports 3, a total number of N × M keys in the whole system, the drive port includes two switches S1, S2 and a constant current source, in a chip based on a CMOS process, a switch S1 may use a PMOS or CMOS transmission gate design, S2 may use an NMOS or CMOS transmission gate design, and S2 has a current absorption capacity greater than that of a constant current source, a linear voltage source connected with a voltage source, a voltage output terminal of a linear voltage source connected with a switch 365, a linear voltage source connected with a linear voltage comparator connected with a voltage output terminal of a switch 363, a linear voltage regulator connected with a linear voltage source, and a linear voltage output terminal of a constant current source connected with a linear voltage regulator connected with a switch 363, wherein the linear voltage source connected with a linear voltage output of a linear voltage source connected with a linear voltage comparator 361 and a linear voltage output of a linear voltage regulator connected with a linear constant current source 3, and a linear voltage regulator connected with a linear voltage output;
the clock generator 4 is arranged on the right side of the driving port 2, and the clock generator 4 is electrically connected with a clock control port;
the scanning control module 5 is arranged at the right side of the driving port 2, the scanning control module 5 is arranged at the lower end of the clock generator 4, the scanning control module 5 is electrically connected with the clock generator 4, and the scanning control module 5 is electrically connected with the driving port 2;
the communication interface 6 is arranged on the right side of the clock generator 4, the communication interface 6 is electrically connected with a communication control port, and the communication interface 6 is used for communicating the circuit with other single-chip microcomputers, computers and other equipment. The single chip microcomputer, the computer and other equipment can set the working state of the circuit of the patent through a 2-wire or 3-wire standard serial interface, including entering a standby mode, setting the size of a constant current source of a driving port, scanning the working period of a control module, writing data into an RAM module 7 and the like;
the RAM module 7 is arranged on the right side of the scanning control module 5, the RAM module 7 is arranged at the lower end of the communication interface 6, the RAM module 7 is electrically connected with the communication interface 6, and the RAM module 7 is used for storing the brightness of each L ED in the L ED array controlled by the driving port;
the configuration register 8 is arranged at the lower end of the communication interface 6, the configuration register 8 is arranged at the right side of the RAM module 7, and the configuration register 8 is electrically connected with the communication interface 6;
the current reference module 9 is arranged at the lower end of the scanning control module 5, the current reference module 9 is arranged at the right side of the driving port 2, the current reference module 9 is electrically connected with the driving port 2, and the current reference module 9 is used for generating a reference current irrelevant to temperature and system voltage;
the constant current power supply 10 is arranged on the right side of the L ED key array 1, the constant current power supply 10 is arranged at the lower end of the driving port 2, the constant current power supply 10 is electrically connected with the current reference module 9, and the constant current power supply 10 is electrically connected with the key common port 3;
the voltage reference module 11 is arranged at the lower end of the current reference module 9, and the voltage reference module 11 is used for generating a reference potential irrelevant to temperature and system voltage;
the linear voltage stabilizer 12 is arranged at the lower end of the voltage reference module 11, the linear voltage stabilizer 12 is arranged at the right side of the constant current power supply 10, the linear voltage stabilizer 12 is electrically connected with the voltage reference module 11, and the linear voltage stabilizer 12 is electrically connected with the constant current power supply 10;
the voltage comparator 13 is arranged at the lower end of the linear voltage stabilizer 12, the voltage comparator 13 is arranged on the right side of the key public port 3, the voltage comparator 13 is electrically connected with the key public port 3, and the voltage comparator 13 is electrically connected with the linear voltage stabilizer 12;
the key judgment module 14 is arranged on the right side of the voltage comparator 13, the key judgment module 14 is electrically connected with the scanning control module 5, the key judgment module 14 is electrically connected with the driving port 2, and the key judgment module 14 judges which key in the key array is pressed according to the control time sequence of the scanning control module 5 to the driving port 2;
the key result register 15 is located on the right side of the key determination module 14, the key result register 15 is electrically connected to the communication interface 6, the key result register is used for storing the state of each key, and each bit of the register represents the state of one key. When a key is pressed down, the state of the register is changed according to the result of the key judgment module. The value of the register can be read at any time through the communication interface.
When the keyboard is in specific use, when the keyboard scans a driving port a, S of the driving port a is closed and S is open, S of the driving port B is closed and S is open, a power supply passes through a system power supply, a constant current source and a closed S in the driving port B, to an ED, to a closed S and a reference ground in the driving port a, a power supply path is formed, an ED is lit, if the voltage of the driving port a is close to 0V due to the IV characteristic of 0ED, the drain voltage range of the constant current source and the low impedance characteristic of a switch S, the voltage of the driving port a is between 1.8 to 3V, the anode voltage of 1ED is lower than the cathode voltage, therefore, the keyboard is in a reverse cut-off state and will not be lit, if the key is pressed, the keyboard common port is shorted with the driving port a, because the current of a constant current source connected inside the keyboard common port is far lower than the maximum current that S can be absorbed by the constant current source, the key is far from the terminal S, the terminal, the keyboard is far lower than the voltage of the constant current source K, the voltage source K is lower than the voltage of the voltage source K, the keyboard is lower terminal K, the voltage of the keyboard is lower terminal K, the higher voltage of the higher voltage than the voltage of the voltage source K, the voltage of the voltage source K, the voltage of the voltage source K, the voltage source K is lower voltage source K, the voltage of the voltage source K is lower voltage source K, the lower voltage of the lower voltage of the lower voltage of the.
While the invention has been described above with reference to an embodiment, various modifications may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In particular, the various features of the embodiments disclosed herein may be used in any combination, provided that there is no structural conflict, and the combinations are not exhaustively described in this specification merely for the sake of brevity and conservation of resources. Therefore, it is intended that the invention not be limited to the particular embodiments disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims (5)
1. A L ED control drive circuit with port multiplexing is characterized by comprising:
l ED key array (1);
a plurality of driving ports (2), a plurality of the driving ports (2) are arranged at the right side of the L ED key array (1), and the driving ports (2) are electrically connected with the L ED key array (1);
a plurality of key common ports (3), a plurality of the key common ports (3) being on the right side of the L ED key array (1), the key common ports (3) being at the lower end of the driving port (2), the key common ports (3) being electrically connected with the L ED key array (1);
a clock generator (4), the clock generator (4) being to the right of the drive port (2);
the scanning control module (5), the scanning control module (5) is arranged on the right side of the driving port (2), the scanning control module (5) is arranged at the lower end of the clock generator (4), the scanning control module (5) is electrically connected with the clock generator (4), and the scanning control module (5) is electrically connected with the driving port (2);
a communication interface (6), the communication interface (6) being to the right of the clock generator (4);
the RAM module (7), the RAM module (7) is arranged on the right side of the scanning control module (5), the RAM module (7) is arranged at the lower end of the communication interface (6), and the RAM module (7) is electrically connected with the communication interface (6);
a configuration register (8), wherein the configuration register (8) is arranged at the lower end of the communication interface (6), the configuration register (8) is arranged at the right side of the RAM module (7), and the configuration register (8) is electrically connected with the communication interface (6);
the current reference module (9), the current reference module (9) is arranged at the lower end of the scanning control module (5), the current reference module (9) is arranged at the right side of the driving port (2), and the current reference module (9) is electrically connected with the driving port (2);
the constant current power supply (10) is arranged on the right side of the L ED key array (1), the constant current power supply (10) is arranged at the lower end of the driving port (2), the constant current power supply (10) is electrically connected with the current reference module (9), and the constant current power supply (10) is electrically connected with the key common port (3);
a voltage reference module (11), the voltage reference module (11) being at a lower end of the current reference module (9);
the linear voltage stabilizer (12), the linear voltage stabilizer (12) is arranged at the lower end of the voltage reference module (11), the linear voltage stabilizer (12) is arranged at the right side of the constant current power supply (10), the linear voltage stabilizer (12) is electrically connected with the voltage reference module (11), and the linear voltage stabilizer (12) is electrically connected with the constant current power supply (10);
a plurality of voltage comparators (13), wherein the voltage comparators (13) are arranged at the lower end of the linear voltage stabilizer (12), the voltage comparators (13) are arranged at the right side of the key common port (3), the voltage comparators (13) are electrically connected with the key common port (3), and the voltage comparators (13) are electrically connected with the linear voltage stabilizer (12);
the key judgment module (14), the key judgment module (14) is arranged on the right side of the voltage comparator (13), the key judgment module (14) is electrically connected with the scanning control module (5), and the key judgment module (14) is electrically connected with the driving port (2);
the key result register (15), the key result register (15) is arranged on the right side of the key judgment module (14), the key result register (15) is electrically connected with the key judgment module (14), and the key result register (15) is electrically connected with the communication interface (6).
2. A port multiplexed L ED control driver circuit according to claim 1, wherein the L ED key array (1) includes L ED matrix and key matrix.
3. The L ED control driving circuit for port multiplexing of claim 1, wherein any two driving ports (2) are connected in parallel with two L ED's, and the two L ED's connected in parallel are connected with opposite polarities.
4. A L ED control driver circuit for port multiplexing according to claim 1, wherein any one of the driver ports (2) is connected to one end of a number of keys equal to the number of the key common ports (3), and the other end of the key common port (3) is connected to a key common terminal.
5. The L ED control driver circuit for port multiplexing according to claim 1, wherein the clock generator (4) is electrically connected with a clock control port, and the communication interface (6) is electrically connected with a communication control port.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010396637.2A CN111465147A (en) | 2020-05-12 | 2020-05-12 | L ED control drive circuit with multiplexed ports |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010396637.2A CN111465147A (en) | 2020-05-12 | 2020-05-12 | L ED control drive circuit with multiplexed ports |
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| CN111465147A true CN111465147A (en) | 2020-07-28 |
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| CN202010396637.2A Pending CN111465147A (en) | 2020-05-12 | 2020-05-12 | L ED control drive circuit with multiplexed ports |
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003131610A (en) * | 2001-10-25 | 2003-05-09 | Konica Corp | Display device, driving method of the device and electronic equipment |
| CN101943742A (en) * | 2010-07-23 | 2011-01-12 | 美的集团有限公司 | Key detection and display driving integrated circuit and control method thereof |
| CN103354453A (en) * | 2013-06-27 | 2013-10-16 | 杭州士兰微电子股份有限公司 | Circuit and method having port multiplexing of indication lamp and button |
| CN104077990A (en) * | 2014-07-02 | 2014-10-01 | 福州福大海矽微电子有限公司 | LED nixie tube display and key control chip using time division multiplexing technology |
| WO2016115926A1 (en) * | 2015-01-21 | 2016-07-28 | 杭州士兰微电子股份有限公司 | Led module and control method thereof, and led drive circuit |
| CN107241829A (en) * | 2017-07-04 | 2017-10-10 | 厦门芯阳科技股份有限公司 | A kind of control method of LED and button multiplexing circuit |
| CN107682951A (en) * | 2016-12-26 | 2018-02-09 | 深圳市华芯邦科技有限公司 | LED controls and key-press input time-sharing multiplex circuit and its control method |
| CN109243362A (en) * | 2018-11-13 | 2019-01-18 | 江苏沁恒股份有限公司 | LED display driving and keyboard turntable driving multiplex circuit and its driving multiplexing method |
| CN211656466U (en) * | 2020-05-12 | 2020-10-09 | 无锡中微爱芯电子有限公司 | Port-multiplexing LED control drive circuit |
-
2020
- 2020-05-12 CN CN202010396637.2A patent/CN111465147A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003131610A (en) * | 2001-10-25 | 2003-05-09 | Konica Corp | Display device, driving method of the device and electronic equipment |
| CN101943742A (en) * | 2010-07-23 | 2011-01-12 | 美的集团有限公司 | Key detection and display driving integrated circuit and control method thereof |
| CN103354453A (en) * | 2013-06-27 | 2013-10-16 | 杭州士兰微电子股份有限公司 | Circuit and method having port multiplexing of indication lamp and button |
| CN104077990A (en) * | 2014-07-02 | 2014-10-01 | 福州福大海矽微电子有限公司 | LED nixie tube display and key control chip using time division multiplexing technology |
| WO2016115926A1 (en) * | 2015-01-21 | 2016-07-28 | 杭州士兰微电子股份有限公司 | Led module and control method thereof, and led drive circuit |
| CN107682951A (en) * | 2016-12-26 | 2018-02-09 | 深圳市华芯邦科技有限公司 | LED controls and key-press input time-sharing multiplex circuit and its control method |
| CN107241829A (en) * | 2017-07-04 | 2017-10-10 | 厦门芯阳科技股份有限公司 | A kind of control method of LED and button multiplexing circuit |
| CN109243362A (en) * | 2018-11-13 | 2019-01-18 | 江苏沁恒股份有限公司 | LED display driving and keyboard turntable driving multiplex circuit and its driving multiplexing method |
| CN211656466U (en) * | 2020-05-12 | 2020-10-09 | 无锡中微爱芯电子有限公司 | Port-multiplexing LED control drive circuit |
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