[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

CN111435643B - Preparation method of three-dimensional stacked gate-all-around transistor - Google Patents

Preparation method of three-dimensional stacked gate-all-around transistor Download PDF

Info

Publication number
CN111435643B
CN111435643B CN201910027361.8A CN201910027361A CN111435643B CN 111435643 B CN111435643 B CN 111435643B CN 201910027361 A CN201910027361 A CN 201910027361A CN 111435643 B CN111435643 B CN 111435643B
Authority
CN
China
Prior art keywords
layer
semiconductor
gate
nanowire
periodic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910027361.8A
Other languages
Chinese (zh)
Other versions
CN111435643A (en
Inventor
刘强
俞文杰
任青华
陈治西
刘晨鹤
赵兰天
陈玲丽
王曦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Institute of Microsystem and Information Technology of CAS
Original Assignee
Shanghai Institute of Microsystem and Information Technology of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Institute of Microsystem and Information Technology of CAS filed Critical Shanghai Institute of Microsystem and Information Technology of CAS
Priority to CN201910027361.8A priority Critical patent/CN111435643B/en
Publication of CN111435643A publication Critical patent/CN111435643A/en
Application granted granted Critical
Publication of CN111435643B publication Critical patent/CN111435643B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Manufacturing & Machinery (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

The invention provides a preparation method of a three-dimensional stacked gate-all-around transistor, which comprises the following steps: 1) providing an SOI substrate, wherein a groove is formed in an insulating layer of the SOI substrate; 2) forming a semiconductor nanowire structure which is suspended and spans the groove and is stacked upwards; 3) rounding and thinning the semiconductor nanowire structure; 4) forming an injection blocking layer on the surface of the channel region, wherein the injection blocking layer exposes preparation regions of the source region and the drain region; 5) performing ion implantation to form a source region and a drain region; 6) forming a fully-enclosed gate dielectric layer and a gate electrode layer on the surface of the semiconductor nanowire, and imaging to form a gate structure; 7) and forming a source electrode and a drain electrode. The gate-all-around transistor is prepared by adopting a gate-last process, so that the selection range of gate materials can be effectively enlarged, and different device performance requirements can be met. When the semiconductor nanowire is etched, isotropic wet etching is not needed, and the generation of concave cavities can be effectively avoided. The invention can effectively improve the integration level of the device.

Description

Preparation method of three-dimensional stacked gate-all-around transistor
Technical Field
The invention belongs to the field of design and manufacture of semiconductor integrated circuits, and particularly relates to a preparation method of a three-dimensional stacked gate-all-around transistor.
Background
With the continuous scaling of microelectronic devices, it is expected that the existing FinFET technology will face a larger technical bottleneck at the 5 nm and 3 nm nodes, and the device performance is no longer greatly improved with the continuous reduction of the device size. There is a need for new device technologies, such as new device materials (e.g., strained silicon, silicon germanium, iii-v semiconductors, etc.), and new device structures (e.g., nanowire ring-gate transistors, etc.).
The nanowire gate-all-around transistor can limit a conducting channel to the center of the nanowire instead of the interface of the nanowire and the gate oxide layer, so that scattering of current carriers is greatly reduced, and the nanowire gate-all-around transistor is expected to be an important future development direction and further continues the development of the Mole's law.
The nanowire ring gate transistor has various preparation schemes, and one simple preparation method is to etch a hollow nanowire structure based on an SOI substrate and prepare a corresponding ring gate transistor. Fig. 1 to 12 show a method for manufacturing a representative nanowire gate-all-around transistor, in which fig. 2 shows a schematic cross-sectional structure at a-a 'of fig. 1, fig. 3 shows a schematic cross-sectional structure at B-B' of fig. 1, and fig. 4 to 12 have the same correspondence. The method mainly comprises the following steps:
as shown in fig. 1 to fig. 3, step 1) is performed to provide an SOI substrate, where the SOI substrate includes a silicon substrate 101, an oxide layer 102, and a top silicon layer 103, and a silicon nanowire 104 is etched in the top silicon layer 103 and the oxide layer 102 through a photolithography process and an etching process;
as shown in fig. 4 to 6, step 2) is performed, and the oxide layer 102 under the silicon nanowire is removed by wet etching to form a hollow hole 105;
as shown in fig. 7 to 9, step 3) is performed to thin the silicon nanowire;
as shown in fig. 10 to 12, step 4) is performed to sequentially deposit a gate dielectric layer 106 and a gate electrode 107 to form a gate-all-around transistor.
The above solution has the following disadvantages:
firstly, when the nanowire structure is etched in step 1), the top silicon of the adjacent region of the nanowire and a part of the silicon oxide under the top silicon need to be etched away. As shown in fig. 2, during the etching process, it is necessary to keep the oxide layer 102 from being etched through, and the remaining silicon oxide layer can still keep a certain thickness to prevent a large parasitic capacitance or breakdown between the gate electrode and the substrate electrode (as shown by 108 in fig. 11) as shown in fig. 11, which brings a certain requirement to the accuracy of the etching process.
Secondly, in order to prepare the silicon nanowire with the suspended structure, the oxide layer under the nanowire needs to be etched, and a wet etching is usually adopted, but since the wet etching is an isotropic etching, a part of the silicon oxide in the exposed region except under the silicon nanowire is also etched, and an unnecessary concave cavity 109 is formed, as shown in fig. 8.
This concave cavity can have the following adverse effects:
as shown in fig. 13 and 14, wherein fig. 13 is a top view of the cross section at C-C' in fig. 11, and fig. 14 is an enlarged view of the dashed box in fig. 13, the concave cavity is finally filled with the gate dielectric layer 106 and the gate electrode 107. In order to ensure good step coverage, an ALD process is generally used to prepare the gate dielectric layer 106 and the gate electrode 107. Even with ALD processes, however, when filling a semi-enclosed structure with dishing, premature contact interconnection of the film to the film occurs easily during filling of the plated film, and eventually an enclosed cavity within the gate metal is formed in the reentrant structure, rather than being completely filled.
As shown in fig. 8, 13 and 14, the corresponding concave cavity 109 in fig. 8 is also filled with the gate dielectric layer 106 and the gate electrode 107, so that the gate electrode under the nanowire is longer than the gate electrode above the nanowire. This results in: an unnecessary overlapping area is arranged between the bottom layer gate and the source drain, a silicon channel in the area is influenced by asymmetric gate potential, and current carriers in the silicon channel are scattered to a certain extent; the resistance between the gate electrode and the source-drain electrode becomes large; the source-drain parasitic capacitance becomes large, and the high-frequency characteristic of the device becomes poor; when the silicon channel of the overlapping region is heavily doped, hot electrons are easily generated between the bottom gate and the silicon channel of the overlapping region, the gate leakage current is increased, and the gate oxide is broken down.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a method for manufacturing a three-dimensionally stacked gate-all-around transistor, which is used to solve the problems of low process stability and low integration level in the prior art for manufacturing the gate-all-around transistor.
To achieve the above and other related objects, the present invention provides a method for fabricating a three-dimensionally stacked gate-all-around transistor, the method comprising: 1) providing a patterned SOI substrate, wherein the SOI substrate comprises a semiconductor substrate, an insulating layer and a top semiconductor layer, a groove is formed in the insulating layer below the top semiconductor layer, the groove does not penetrate through the insulating layer, the top semiconductor layer comprises a periodic structure of alternately laminated semiconductor layers and sacrificial layers, and the bottommost layer and the topmost layer of the top semiconductor layer are both the semiconductor layers; 2) the top semiconductor layer is etched in a patterned mode to form a periodic nanowire structure which is suspended and stretches across the groove, the periodic nanowire structure comprises periodic bosses located on two sides of the groove and a plurality of periodic nanowires connected to the periodic bosses; 3) selectively removing the sacrificial layer in the periodic nanowires to form suspended and upwards stacked semiconductor nanowires; 4) rounding and thinning the semiconductor nanowire structure; 5) forming an injection buffer layer on the surface of the semiconductor nanowire structure, defining a channel region in the semiconductor nanowire, and forming an injection barrier layer on the surface of the channel region, wherein the injection barrier layer exposes preparation regions of a source region and a drain region; 6) carrying out an ion implantation process on the preparation areas of the source region and the drain region to form the source region and the drain region, and removing the implantation barrier layer and the implantation buffer layer; 7) forming a fully-enclosed gate dielectric layer on the surface of the semiconductor nanowire, forming a gate electrode layer on the surface of the gate dielectric layer, and graphically etching the gate electrode layer and the gate dielectric layer to form a gate structure; 8) and forming a source electrode and a drain electrode in the source region and the drain region.
Optionally, step 1) comprises: step 1-1), providing a first semiconductor substrate and a second semiconductor substrate, and forming an insulating layer on the surface of the first semiconductor substrate; step 1-2), forming a periodic structure of alternately stacked sacrificial layers and semiconductor layers on the surface of the second semiconductor substrate, carrying out stripping ion implantation on the sacrificial layer at the bottommost layer, and defining a stripping interface in the sacrificial layer at the bottommost layer; step 1-3), the insulating layer is etched in a patterning mode, so that a groove is formed in the insulating layer, and the groove does not penetrate through the insulating layer; step 1-4), bonding the periodic structure and the insulating layer, wherein the groove is sealed by the periodic structure to form a cavity; and 1-5), carrying out an annealing process to strengthen the bonding strength of the insulating layer and the periodic structure, and stripping the sacrificial layer at the bottommost layer from a stripping interface, wherein the part of the periodic structure combined with the insulating layer is used as a top semiconductor layer of the SOI substrate.
Optionally, the thickness of the insulating layer is not greater than 150 nm, the thickness of the top semiconductor layer is not greater than 50nm, and the depth of the groove is not greater than 50 nm.
Optionally, the bonding atmosphere in step 1-4) includes hydrogen, a mixture of hydrogen and nitrogen, a mixture of oxygen and nitrogen, oxygen, or vacuum, and during the annealing process in step 1-5), the mixture in the cavity is absorbed by or diffused out of the top semiconductor layer to reduce the pressure in the cavity.
Optionally, the annealing process includes annealing at a first temperature to peel the sacrificial layer of the bottommost layer from the peeling interface, and annealing at a second temperature to enhance the bonding strength between the insulating layer and the periodic structure, wherein the first temperature is in a range of 200-900 ℃, and the second temperature is in a range of 400-1200 ℃.
Optionally, step 1-5) further comprises the step of performing CMP polishing on the top semiconductor surface to remove the remaining sacrificial layer of the bottommost layer.
Optionally, the thickness of the lowermost sacrificial layer is not less than 40 nm.
Optionally, the topmost layer of the periodic structure is a semiconductor layer, and step 2) further includes a step of performing planarization treatment on the topmost semiconductor layer, so that the surface roughness of the topmost semiconductor layer is less than 0.2 nm, and the thickness of the topmost semiconductor layer is equal to that of the semiconductor layer in the periodic structure.
Optionally, the planarization process includes one or a combination of chemical mechanical polishing or thermal oxidation followed by removal of the oxide layer.
Optionally, the sacrificial layer comprises a SixGe1-x layer and the semiconductor layer comprises a Si layer, wherein 0 < x ≦ 1.
Optionally, the sacrificial layer includes a 111 crystal plane Si layer, and the semiconductor layer includes a GaN layer.
Optionally, the sacrificial layer comprises a single crystal Al2O3 layer and the semiconductor layer comprises a GaN layer.
Optionally, step 4) is to oxidize the semiconductor nanowire structure to form an oxide layer on the surface thereof, and then to remove the oxide layer, so as to reduce the diameter of the semiconductor nanowire and round the semiconductor nanowire.
Optionally, the oxidizing is to perform rapid annealing in an oxygen atmosphere and control the semiconductor nanowire to perform slight oxidation so as to improve the control accuracy of the size and the shape of the nanowire, and the method for removing the oxide layer includes one of wet etching or atomic layer etching.
Optionally, in step 7), an atomic layer deposition process is used to form a fully-enclosed gate dielectric layer on the surface of the semiconductor nanowire, and an atomic layer deposition process is used to form a gate electrode layer on the surface of the gate dielectric layer.
Optionally, the step 7) of performing the patterned etching on the gate electrode layer and the gate dielectric layer includes one of reactive ion etching and atomic layer etching.
As described above, the method for manufacturing a three-dimensional stacked gate-all-around transistor of the present invention has the following beneficial effects:
1) according to the gate-all-around transistor, the gate electrode layer is used as a mask to carry out self-aligned injection of the source region and the drain region, so that the process stability and the injection precision can be effectively improved, and the process cost can be effectively reduced.
2) The invention can prepare the three-dimensional stacked ring gate transistor and is beneficial to improving the integration level of devices.
3) According to the invention, the SOI substrate with the graphical structure is firstly manufactured, the hollowed-out semiconductor nanowire can be directly prepared by the SOI substrate through dry etching, and when the semiconductor nanowire is prepared, isotropic wet etching is not required, so that the generation of an inwards concave cavity can be effectively avoided.
4) The gate-all-around transistor has the advantages of smaller subthreshold slope, smaller off-state current density, larger on-state current density, good high-frequency characteristic and good radiation resistance, and is particularly suitable for integrated circuits, sensors, memories and the like with low power consumption, high frequency and high reliability. Because the channel region is completely surrounded by the gate structure, the transistor has good single event effect resistance and total dose effect resistance at the same time, and is suitable for aerospace electronic chips.
Drawings
Fig. 1 to 14 are schematic structural diagrams showing steps of a method for manufacturing a nanowire wrap-around transistor in the prior art.
Fig. 15 to 54 are schematic structural diagrams showing steps of the method for manufacturing a three-dimensional stacked gate-all-around transistor according to the present invention.
Description of the element reference numerals
201 first silicon substrate
202 insulating layer
203 groove
204 cavity
301 second silicon substrate
302 second insulating layer
40 period structure
401 sacrificial layer
402 semiconductor layer
501 semiconductor nanowires
503 semiconductor boss
601 gate dielectric layer
602 gate electrode layer
603 source region
604 drain region
605 source electrode
606 drain electrode
607 passivation layer
701 injection buffer layer
702 implant barrier
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 15-54. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 15 to 54, the present embodiment provides a method for manufacturing a three-dimensional stacked gate-all-around transistor, where the method includes:
as shown in fig. 15, step 1) is performed to provide a first silicon substrate 201 and a second silicon substrate 301, and an insulating layer 202 is formed on a surface of the first silicon substrate 201. In other embodiments, the first silicon substrate and the second silicon substrate may be made of other semiconductor materials, for example, the material of the first semiconductor substrate and the second semiconductor substrate may be one of germanium, silicon germanium, gallium nitride, aluminum nitride, gallium arsenide, silicon carbide, zinc oxide, gallium oxide, and indium phosphide, and is not limited to the examples listed here.
For example, a thermal oxidation process is adopted to form a silicon dioxide layer on the surface of the first silicon substrate 201 as the insulating layer 202, in this embodiment, the thermal oxidation process is a dry thermal oxidation process, and the temperature range of the oxidation is 900 to 1200 ℃, and may be specifically 1000 ℃.
As shown in fig. 17 to 19, step 2) is performed to form the periodic structure 40 of the alternately stacked sacrificial layers 401 and semiconductor layers 402 on the surface of the second semiconductor substrate 301, and then the stripping ion implantation is performed to the sacrificial layer 401 at the bottom layer, so as to define the stripping interface in the sacrificial layer 401 at the bottom layer.
For example, a periodic structure 40 of alternately stacked sacrificial layers 401 and semiconductor layers 402 may be formed on the surface of the second semiconductor substrate 301 by a Chemical Vapor Deposition (CVD) process or Molecular Beam Epitaxy (MBE). For example, in the present embodiment, the sacrificial layer 401 may be a SixGe1-x layer, and the semiconductor layer 402 may be a Si layer, where 0 < x ≦ 1. Of course, according to different etching processes, the sacrificial layer may be configured as silicon, and the semiconductor layer may be configured as a SixGe1-x layer, in which case, the silicon may be selectively etched and removed by using a tetramethylammonium hydroxide solution, and the sacrificial layer and the semiconductor layer may be interchangeable if both are semiconductor materials. The sacrificial layer 401 and the semiconductor layer 402 have similar lattice parameters in principle, and have a higher etching selectivity ratio in the same etching process, for example, the etching selectivity ratio of the sacrificial layer 401 to the semiconductor layer 402 is not less than 10 to 1. For example, when the sacrificial layer 401 is a SixGe1-x layer, H may be used2O2Solutions or H2O2+NH3·H2O solution or H2O2And a solution of + HF + CH3COOH and the like is used for selectively removing the sacrificial layer 401.
For another example, in another embodiment, the sacrificial layer 401 may be a 111 crystal plane Si layer, and the semiconductor layer 402 may be a GaN layer, in which case NH may be used3·H2O solution or H2O2The + HF solution selectively removes the sacrificial layer 401.
For another example, in another embodiment, the sacrificial layer 401 may be a single crystal Al2O3 layer, and the semiconductor layer 402 may be a GaN layer, and at this time, the sacrificial layer 401 may be selectively removed using a H3PO4 solution, an HF solution, an NH3 · H2O solution, a BOE solution, or the like.
The bottom layer of the periodic structure 40 is a sacrificial layer 401, the top layer of the periodic structure 40 is a semiconductor layer 402, and after the deposition of the top semiconductor layer 402, the method further comprises the step of carrying out planarization treatment on the top semiconductor layer 402, so that the surface roughness of the top semiconductor layer 402 is less than 0.2 nanometer, and the thickness of the top semiconductor layer 402 is equal to that of the semiconductor layer 402 in the periodic structure 40. For example, the planarization process may include one or a combination of chemical mechanical polishing or thermal oxidation followed by removal of the oxide layer.
In this embodiment, the thickness of the lowermost sacrificial layer 401 is not less than 40 nm. For example, the thickness of the sacrificial layer 401 at the bottom layer can be 40-60 nanometers, and the sacrificial layer 401 at the bottom layer with the thickness can effectively ensure the process stability of the subsequent ion implantation stripping and ensure that fewer residual layers exist after the stripping, so that the removal cost of the subsequent residual layers is saved.
As an example, the stripping ions may be H ions, and the ion implantation parameters depend on the desired implantation depth. Of course, in other embodiments, He ions may be used as the stripping ions for implantation, and the examples are not limited to the examples listed here.
As shown in fig. 16, step 3) is performed to pattern etch the insulating layer 202, so as to form a groove 203 in the insulating layer 202, where the groove 203 does not penetrate through the insulating layer 202.
In this embodiment, the patterned etching is anisotropic dry etching to improve the control accuracy of the groove 203.
For example, in the present embodiment, the thickness of the insulating layer 202 is not greater than 150 nm, and the depth of the groove 203 is not greater than 50 nm. The above parameter settings may ensure that a sufficient thickness of the insulating layer is maintained below the recess 203, for example, the thickness of the insulating layer below the recess 203 is above 50 nm.
As shown in fig. 20, step 4) is then performed to bond the periodic structure 40 and the insulating layer 202, and the periodic structure 40 closes the groove 203 to form a cavity 204.
As shown in fig. 21, step 5) is performed, an annealing process is performed to enhance the bonding strength between the insulating layer 202 and the periodic structure 40, and the periodic structure 40 is peeled from the peeling interface, wherein the portion of the periodic structure 40 bonded to the insulating layer 202 serves as a top semiconductor layer of the SOI substrate; wherein, the bonding atmosphere in the step 4) includes hydrogen, a mixture of hydrogen and nitrogen, a mixture of oxygen and nitrogen, oxygen, or vacuum, and during the annealing process in the step 5), the mixture in the cavity 204 is absorbed by the top semiconductor layer or diffused out of the top semiconductor layer to reduce the pressure in the cavity 204.
In the preparation process of the invention, the atmosphere adopted in bonding is selected to be hydrogen/nitrogen or oxygen/nitrogen mixed gas, so that in the subsequent processes of intelligent stripping and high-temperature reinforced bonding, the gas in the insulating layer cavity 204 can be diffused out of silicon or absorbed by silicon, for example, the hydrogen can be diffused out of a semiconductor layer, the oxygen can be absorbed by the semiconductor layer, and the air pressure in the cavity 204 is reduced, so that the cavity 204 structure has internal pressure close to the external atmospheric pressure in the high-temperature environment, the pressure on the cavity 204 structure is smaller, and the structure is not easily damaged by the difference of the internal and external air pressures, thereby obtaining the SOI substrate with the thin-layer top semiconductor layer and the graphical structure. For example, in this embodiment, the thickness of the top semiconductor layer is not greater than 50nm, and a thinner top semiconductor layer is prepared, so that the application range of the SOI substrate with the patterned structure of the present invention can be effectively expanded, for example, the present invention can be used for etching and forming a hollowed three-dimensional stacked semiconductor nanowire, thereby reducing the etching difficulty of the semiconductor nanowire and improving the quality of the semiconductor nanowire.
Specifically, the annealing process includes annealing at a first temperature to peel the sacrificial layer 401 of the bottom layer from the peeling interface, and annealing at a second temperature to enhance the bonding strength between the insulating layer 202 and the periodic structure 40, wherein the first temperature is in a range of 200-900 ℃, and the second temperature is in a range of 400-1200 ℃.
Finally, as shown in fig. 22, CMP polishing is performed on the surface of the top semiconductor layer to remove the remaining sacrificial layer 401 of the bottom layer, so as to obtain a top semiconductor layer with a smooth surface.
The above-described manufacturing method is applicable to wafer-level manufacturing, and the structure of the SOI substrate of the wafer-level patterned structure of the present invention is shown in fig. 23.
Fig. 24 to 32 are enlarged schematic structural views of a dotted-line frame region in fig. 22, fig. 25 is a schematic structural view of a cross section at a-a 'in fig. 24, fig. 26 is a schematic structural view of a cross section at B-B' in fig. 24, and fig. 27 to 32 have the same view relationship.
As shown in fig. 24 to 26, step 6) is performed to pattern-etch the top semiconductor layer to form a periodic nanowire structure suspended in the air and crossing the groove, where the periodic nanowire structure includes periodic mesas located at two sides of the groove and a plurality of periodic nanowires connected to the periodic mesas.
Specifically, the patterned etching is anisotropic dry etching.
As shown in fig. 27 to 29, step 7) is then performed to selectively remove the sacrificial layer in the periodic nanowire to form a semiconductor nanowire 501 which is suspended and stacked upwards, and since the sacrificial layer in the periodic nanowire is much thinner than the sacrificial layer in the periodic mesa, when the sacrificial layer in the periodic nanowire is completely removed, the sacrificial layer mesa still remains in the periodic mesa, and the sacrificial layer mesa separates two adjacent semiconductor mesas 502 to allow a space between two adjacent semiconductor nanowires.
As shown in fig. 30-33, step 8) is finally performed to round and thin the semiconductor nanowire structure.
For example, the semiconductor nanowire structure may be oxidized to form an oxide layer on the surface thereof, and then the oxide layer may be removed to make the diameter of the semiconductor nanowire small and round the semiconductor nanowire. Optionally, the oxidizing is to perform rapid annealing in an oxygen atmosphere and control the semiconductor nanowire to perform slight oxidation so as to improve the control accuracy of the size and the shape of the nanowire, and the method for removing the oxide layer includes one of wet etching or atomic layer etching.
It should be noted that the above-mentioned manufacturing method is suitable for wafer-level manufacturing, as shown in fig. 33.
As shown in fig. 34 to 39, step 8) is performed to form an implantation buffer layer 701 on the surface of the semiconductor nanowire structure, define a channel region in the semiconductor nanowire, and form an implantation blocking layer 702 on the surface of the channel region, where the implantation blocking layer 702 exposes the preparation regions of the source region and the drain region.
For example, the implanted buffer layer may be silicon dioxide or the like for buffering implanted ions, and due to the thin thickness of the semiconductor nanowire, the ion implantation may effectively protect the semiconductor material of the source region and the drain region, reduce damage caused by the ion implantation, and avoid performance degradation or failure of the device due to damage of the semiconductor material. The implant block 702 may be a photoresist or the like.
As shown in fig. 37 to 42, step 9) is then performed to perform an ion implantation process on the preparation regions of the source region 603 and the drain region 604 to form a source region 603 and a drain region 604, and to remove the implantation blocking layer 702 and the implantation buffer layer 701. The source region 603 and the drain region 604 are formed at both end portions of the semiconductor nanowire and the semiconductor mesa.
It should be noted that, since the semiconductor nanowires are stacked upward, in this embodiment, multiple implantation energies are selected for sequential implantation during ion implantation, so that the peak of the implanted impurity distribution is located at the middle of each layer of semiconductor nanowires. Meanwhile, considering that a small amount of nano wires of the n-th layer can be injected into other n-1 layers of nano wires positioned above the n-th layer in the injection process, the doping concentration of each layer of semiconductor nano wire is the same after the injection is finished by reasonably setting the injection dosage of each time.
In the nanowire gate-all-around transistor, in setting the impurity species and concentration, the transistor may be set to:
1) silicon at the source region 603 and the drain region 604 and silicon at the channel respectively form PN junctions for blocking carriers, namely the doping types of the source region 603, the channel region and the drain region 604 are source region N +/channel region P-/drain region N + or source region P +/channel region N-/drain region P +;
2) the transistor may also be a junction-less transistor, that is, the silicon of the source region 603 and the drain region 604 and the silicon of the channel region are doped in the same type, without PN junction, and the doping types are: the source region N +/the channel region N-drain region/N + or the source region P +/the channel region P-/the drain region P +. Wherein the doping of the channel region can be completed by selecting a wafer meeting the doping conditions when the substrate is prepared.
As shown in fig. 43 to 51, step 10) is then performed to form a fully-enclosed gate dielectric layer 601 on the surface of the semiconductor nanowire, form a gate electrode layer 602 on the surface of the gate dielectric layer 601, and pattern-etch the gate electrode layer 602 and the gate dielectric layer 601 to form a gate structure.
For example, an atomic layer deposition process may be used to form a fully-enclosed gate dielectric layer 601 on the surface of the semiconductor nanowire, and an atomic layer deposition process may be used to form a gate electrode layer 602 on the surface of the gate dielectric layer 601. The gate dielectric layer may be a high-K dielectric layer such as an oxide or oxynitride of Ti, Zr, Hf, for example, the gate dielectric layer may be HfON, HfO2, ZrO, TiO2, etc. The gate electrode layer may be titanium, titanium nitride, aluminum, tantalum nitride, or a stack of these materials.
The patterned etching of the gate electrode layer 602 and the gate dielectric layer 601 includes one of reactive ion etching and atomic layer etching.
As shown in fig. 52 to 54, step 11) is finally performed to form a passivation layer 607, form openings in the passivation layer 607 to expose the source region 603 and the drain region 604, and form a source electrode 605 and a drain electrode 606 in the source region 603 and the drain region 604, so as to form the gate-all-around transistor.
As described above, the method for manufacturing a three-dimensional stacked gate-all-around transistor of the present invention has the following beneficial effects:
1) the gate-all-around transistor is prepared by adopting a gate-last process, can effectively improve the selection range of gate materials, and can prepare a high-K dielectric metal gate structure and the like, thereby realizing different device performance requirements.
2) The invention can prepare the three-dimensional stacked ring gate transistor and is beneficial to improving the integration level of devices.
3) According to the invention, the SOI substrate with the graphical structure is firstly manufactured, the hollowed-out semiconductor nanowire can be directly prepared by the SOI substrate through dry etching, and when the semiconductor nanowire is prepared, isotropic wet etching is not required, so that the generation of an inwards concave cavity can be effectively avoided.
4) The gate-all-around transistor has the advantages of smaller subthreshold slope, smaller off-state current density, larger on-state current density, good high-frequency characteristic and good radiation resistance, and is particularly suitable for integrated circuits, sensors, memories and the like with low power consumption, high frequency and high reliability. Because the channel region is completely surrounded by the gate structure, the transistor has good single event effect resistance and total dose effect resistance at the same time, and is suitable for aerospace electronic chips.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (16)

1. A preparation method of a three-dimensional stacked gate-all-around transistor is characterized by comprising the following steps:
1) providing a patterned SOI substrate, wherein the SOI substrate comprises a semiconductor substrate, an insulating layer and a top semiconductor layer, a groove is formed in the insulating layer below the top semiconductor layer, the groove does not penetrate through the insulating layer, the top semiconductor layer comprises a periodic structure of alternately laminated semiconductor layers and sacrificial layers, and the bottommost layer and the topmost layer of the top semiconductor layer are both the semiconductor layers;
2) the top semiconductor layer is etched in a graphical mode to form a periodic nanowire structure which is suspended and stretches across the groove, the periodic nanowire structure comprises periodic bosses located on two sides of the groove and a plurality of periodic nanowires connected to the periodic bosses, and the width of the groove is smaller than the length of the periodic nanowires;
3) selectively removing the sacrificial layer in the periodic nanowires to form suspended and upwards stacked semiconductor nanowires;
4) rounding and thinning the semiconductor nanowire;
5) forming an injection buffer layer on the surface of the semiconductor nanowire, defining a channel region in the semiconductor nanowire, and forming an injection barrier layer on the surface of the channel region, wherein the injection barrier layer exposes preparation regions of a source region and a drain region;
6) carrying out an ion implantation process on the preparation areas of the source region and the drain region to form the source region and the drain region, and removing the implantation barrier layer and the implantation buffer layer;
7) forming a fully-enclosed gate dielectric layer on the surface of the semiconductor nanowire, forming a gate electrode layer on the surface of the gate dielectric layer, and graphically etching the gate electrode layer and the gate dielectric layer to form a gate structure;
8) and forming a passivation layer on the side wall of the gate structure, wherein the projection of the passivation layer on the substrate extends to the periphery of the projection of the groove on the substrate, and forming a source electrode and a drain electrode on the source region and the drain region.
2. The method of claim 1, wherein: the step 1) comprises the following steps:
step 1-1), providing a first semiconductor substrate and a second semiconductor substrate, and forming an insulating layer on the surface of the first semiconductor substrate;
step 1-2), forming a periodic structure of alternately stacked sacrificial layers and semiconductor layers on the surface of the second semiconductor substrate, carrying out stripping ion implantation on the sacrificial layer at the bottommost layer, and defining a stripping interface in the sacrificial layer at the bottommost layer;
step 1-3), the insulating layer is etched in a patterning mode, so that a groove is formed in the insulating layer, and the groove does not penetrate through the insulating layer;
step 1-4), bonding the periodic structure and the insulating layer, wherein the groove is sealed by the periodic structure to form a cavity;
and 1-5), carrying out an annealing process to strengthen the bonding strength of the insulating layer and the periodic structure, and stripping the sacrificial layer at the bottommost layer from a stripping interface, wherein the part of the periodic structure combined with the insulating layer is used as a top semiconductor layer of the SOI substrate.
3. The method of claim 2, wherein: the thickness of the insulating layer is not more than 150 nanometers, the thickness of the top semiconductor layer is not more than 50 nanometers, and the depth of the groove is not more than 50 nanometers.
4. The method of claim 2, wherein: the bonding atmosphere of step 1-4) comprises hydrogen, a mixture of hydrogen and nitrogen, a mixture of oxygen and nitrogen, oxygen or vacuum, and during the annealing process of step 1-5), the mixture in the cavity is absorbed by or diffused out of the top semiconductor layer to reduce the pressure in the cavity.
5. The method of claim 2, wherein: the annealing process comprises annealing at a first temperature to enable the sacrificial layer at the bottommost layer to be stripped from a stripping interface, and annealing at a second temperature to enhance the bonding strength of the insulating layer and the periodic structure, wherein the first temperature ranges from 200 ℃ to 900 ℃, and the second temperature ranges from 400 ℃ to 1200 ℃.
6. The method of claim 2, wherein: steps 1-5) further include the step of CMP polishing the top semiconductor layer surface to remove the remaining sacrificial layer of the bottom most layer.
7. The method of claim 2, wherein: the thickness of the bottom sacrificial layer is not less than 40 nanometers.
8. The method of claim 2, wherein: the topmost layer of the periodic structure is a semiconductor layer, and the step 1-2) further comprises the step of carrying out planarization treatment on the topmost semiconductor layer, so that the surface roughness of the topmost semiconductor layer is smaller than 0.2 nanometer, and the thickness of the topmost semiconductor layer is equal to that of the semiconductor layer in the periodic structure.
9. The method of claim 8, wherein: the planarization treatment comprises one or two combinations of chemical mechanical polishing or thermal oxidation followed by removal of the oxide layer.
10. The method of claim 2, wherein: the sacrificial layer comprises SixGe1-xThe semiconductor layer comprises a Si layer, wherein x is more than 0 and less than or equal to 1.
11. The method of claim 2, wherein: the sacrificial layer comprises a 111 crystal plane Si layer, and the semiconductor layer comprises a GaN layer.
12. The method of claim 2, wherein: the sacrificial layer comprises single crystal Al2O3A layer, the semiconductor layer comprising a GaN layer.
13. The method of claim 1, wherein: and 4) oxidizing the semiconductor nanowire to form an oxide layer on the surface of the semiconductor nanowire, and then removing the oxide layer to reduce the diameter of the semiconductor nanowire and round the semiconductor nanowire.
14. The method of claim 13, wherein: the oxidation is to perform rapid annealing in an oxygen atmosphere and control the semiconductor nanowire to perform slight oxidation so as to improve the control precision of the size and the shape of the nanowire, and the method for removing the oxide layer comprises one of wet etching or atomic layer etching.
15. The method of claim 1, wherein: and 7) forming a fully-surrounded gate dielectric layer on the surface of the semiconductor nanowire by adopting an atomic layer deposition process, and forming a gate electrode layer on the surface of the gate dielectric layer by adopting atomic layer deposition.
16. The method of claim 1, wherein: and 7) the step of performing graphical etching on the gate electrode layer and the gate dielectric layer comprises one of reactive ion etching and atomic layer etching.
CN201910027361.8A 2019-01-11 2019-01-11 Preparation method of three-dimensional stacked gate-all-around transistor Active CN111435643B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910027361.8A CN111435643B (en) 2019-01-11 2019-01-11 Preparation method of three-dimensional stacked gate-all-around transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910027361.8A CN111435643B (en) 2019-01-11 2019-01-11 Preparation method of three-dimensional stacked gate-all-around transistor

Publications (2)

Publication Number Publication Date
CN111435643A CN111435643A (en) 2020-07-21
CN111435643B true CN111435643B (en) 2022-01-28

Family

ID=71580431

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910027361.8A Active CN111435643B (en) 2019-01-11 2019-01-11 Preparation method of three-dimensional stacked gate-all-around transistor

Country Status (1)

Country Link
CN (1) CN111435643B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113594006B (en) * 2021-07-29 2022-08-30 中国科学院上海微系统与信息技术研究所 Vacuum channel transistor and manufacturing method thereof
CN117015230A (en) * 2022-04-26 2023-11-07 长鑫存储技术有限公司 Semiconductor structure, preparation method thereof and memory
CN117580356A (en) * 2022-08-04 2024-02-20 长鑫存储技术有限公司 Semiconductor structure and forming method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103295878A (en) * 2012-02-27 2013-09-11 中芯国际集成电路制造(上海)有限公司 Manufacturing method of multilayer nanowire structure
CN105895575A (en) * 2016-05-09 2016-08-24 中国科学院上海微系统与信息技术研究所 Graphical silicon-on-insulator substrate material and preparation method thereof

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080135949A1 (en) * 2006-12-08 2008-06-12 Agency For Science, Technology And Research Stacked silicon-germanium nanowire structure and method of forming the same
US8183104B2 (en) * 2010-07-07 2012-05-22 Hobbs Christopher C Method for dual-channel nanowire FET device
US9219005B2 (en) * 2011-06-28 2015-12-22 Monolithic 3D Inc. Semiconductor system and device
CN102623382B (en) * 2012-03-31 2014-03-12 上海华力微电子有限公司 Silicon on insulator (SOI)-based manufacturing method for three-dimensional array type silicon nano-wire metal oxide semiconductor field effect transistor
CN105633001A (en) * 2015-12-29 2016-06-01 中国科学院上海微系统与信息技术研究所 Silicon-on-insulator substrate material and preparation method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103295878A (en) * 2012-02-27 2013-09-11 中芯国际集成电路制造(上海)有限公司 Manufacturing method of multilayer nanowire structure
CN105895575A (en) * 2016-05-09 2016-08-24 中国科学院上海微系统与信息技术研究所 Graphical silicon-on-insulator substrate material and preparation method thereof

Also Published As

Publication number Publication date
CN111435643A (en) 2020-07-21

Similar Documents

Publication Publication Date Title
US11145553B2 (en) Nonplanar device and strain-generating channel dielectric
US20210167218A1 (en) Gate-All-Around Structure and Methods of Forming the Same
US11710792B2 (en) Semiconductor structure with improved source drain epitaxy
TWI597846B (en) Semiconductor device and the method of forming the same
CN111435641B (en) Three-dimensional stacked gate-all-around transistor and preparation method thereof
TWI768834B (en) Semiconductor device and method for fabricating the same
CN111435643B (en) Preparation method of three-dimensional stacked gate-all-around transistor
TWI768678B (en) Semiconductor structure and method forming the same
TW201401513A (en) Methods of forming FinFET devices with alternative channel materials
CN102769033B (en) HEMT with high breakdown voltage and method of manufacturing the same
US20240312842A1 (en) Semiconductor structure and method of manufacturing the same
CN111435642B (en) Three-dimensional stacked semiconductor nanowire structure and preparation method thereof
TW201913751A (en) Semiconductor device and method of forming the same
CN108133960B (en) Vertically stacked gate-all-around nanowire tunneling field effect transistor and preparation method thereof
US9953977B1 (en) FinFET semiconductor device
CN103594513B (en) Semiconductor device and method for manufacturing the same
CN105762190B (en) Semiconductor device and method for manufacturing the same
CN111435678B (en) Preparation method of gate-all-around transistor
CN111435644B (en) Gate-all-around transistor and preparation method thereof
CN109326650A (en) Semiconductor device, method of manufacturing the same, and electronic apparatus including the same
CN112652664A (en) Semiconductor device and manufacturing method thereof, integrated circuit and electronic equipment
TWI653672B (en) Semiconductor devices and methods for forming the same
US10325811B2 (en) Field-effect transistors with fins having independently-dimensioned sections
US20050009250A1 (en) Ultra short channel field effect transistor and method of fabricating the same
CN111435666A (en) SOI substrate with graphical structure and preparation method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant