CN111435604B

CN111435604B - Decoding method, memory control circuit unit and memory storage device

Info

Publication number: CN111435604B
Application number: CN201910034821.XA
Authority: CN
Inventors: 梁鸣仁
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2019-01-15
Filing date: 2019-01-15
Publication date: 2023-05-02
Anticipated expiration: 2039-01-15
Also published as: CN111435604A

Abstract

The invention provides a decoding method, a memory control circuit unit and a memory storage device, wherein the method comprises the following steps: receiving a plurality of instructions; according to a first reading instruction in the plurality of instructions, reading a first physical programming unit by using a plurality of first reading voltage groups in a plurality of reading voltage groups to respectively obtain a plurality of first data, and executing a first decoding operation on each first data in the plurality of first data, wherein the number of the plurality of first reading voltage groups is smaller than that of the plurality of reading voltage groups; and executing other instructions of the plurality of instructions that are different from the first read instruction when failure occurs to perform the first decoding operation on each of the plurality of first data.

Description

Decoding method, memory control circuit unit and memory storage device

Technical Field

The invention relates to a decoding method, a memory control circuit unit and a memory storage device.

Background

Digital cameras, mobile phones and MP3 players have grown very rapidly over the years, such that consumer demand for storage media has also increased rapidly. Since the rewritable nonvolatile memory module (e.g., flash memory) has the characteristics of nonvolatile data, power saving, small size, no mechanical structure, etc., it is very suitable for being built in the various portable multimedia devices as exemplified above.

Generally, when a read voltage is used to read data from a rewritable nonvolatile memory module, the memory management circuit can decode the read data to obtain the data to be read. However, when decoding fails, the memory management circuit performs a re-Read (Retry-Read) mechanism to re-acquire another Read voltage, and uses the other Read voltage to Read to re-acquire the Read data and decode. The memory management circuit performs the decoding operation according to the retrieved verification bits to retrieve another decoded data composed of a plurality of decoding bits. The mechanism for re-acquiring the read voltage to re-read may be repeatedly performed until the number of times exceeds the preset number of times. When the re-read mechanism is performed more than a preset number of times, the memory management circuit may perform the decoding operation instead of other non-re-read mechanisms, for example.

It should be noted that when a decoding operation is performed on data read by one read instruction but decoding failure occurs and the decoding operation is repeatedly performed (e.g., re-read mechanism), the subsequent read instruction of the read instruction needs to wait and cannot be performed, which may result in low execution efficiency of the read instruction.

Disclosure of Invention

The invention provides a decoding method, a memory control circuit unit and a memory storage device, which can reduce the time spent by a subsequent read instruction waiting for a previous read instruction to execute a complete decoding operation.

The invention provides a decoding method, which is used for a rewritable nonvolatile memory module, the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, each entity erasing unit in the plurality of entity erasing units is provided with a plurality of entity programming units, and the decoding method comprises the following steps: receiving a plurality of instructions; according to a first reading instruction in the plurality of instructions, reading a first physical programming unit by using a plurality of first reading voltage groups in a plurality of reading voltage groups to respectively obtain a plurality of first data, and executing a first decoding operation on each first data in the plurality of first data, wherein the number of the plurality of first reading voltage groups is smaller than that of the plurality of reading voltage groups; and executing other instructions of the plurality of instructions that are different from the first read instruction when failure occurs to perform the first decoding operation on each of the plurality of first data.

In an embodiment of the invention, after the step of executing the other of the plurality of instructions than the first read instruction, the method further comprises: according to the first reading instruction, the first physical programming unit is read by using a plurality of second reading voltage groups in a plurality of reading voltage groups to respectively obtain a plurality of second data, and the first decoding operation is performed on each of the plurality of second data. Wherein the number of the plurality of second read voltage sets is less than the number of the plurality of read voltage sets and the plurality of second read voltage sets is different from the plurality of first read voltage sets.

In an embodiment of the invention, the method further comprises: executing other instructions of the plurality of instructions that are different from the first read instruction when failure occurs to perform the first decoding operation on each of the plurality of second data; and when the number of other instructions which are executed and are different from the first reading instruction reaches a threshold value, reading the first physical programming unit by using at least one residual reading voltage set except the first reading voltage set and the second reading voltage set in the plurality of reading voltage sets according to the first reading instruction in the plurality of instructions so as to obtain at least one third data, and executing the first decoding operation on the third data.

In an embodiment of the invention, the method further comprises: when the first decoding operation on the third data fails, the first physical programming unit is read to obtain fourth data, and a second decoding operation is performed on the fourth data, wherein an algorithm used by the first decoding operation is different from an algorithm used by the second decoding operation.

In an embodiment of the invention, the number of the plurality of first read voltage sets is greater than or equal to five and the number of the plurality of first read voltage sets is less than or equal to ten.

In an embodiment of the present invention, the number of the other instructions different from the first read instruction is three.

In an embodiment of the invention, the other instruction different from the first read instruction is a read instruction.

The invention provides a memory control circuit unit, which is used for a rewritable nonvolatile memory module, the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, each entity erasing unit in the plurality of entity erasing units is provided with a plurality of entity programming units, and the memory control circuit unit comprises: host interface, memory interface and memory management circuit. The host interface is used for being electrically connected to a host system. The memory interface is electrically connected to the rewritable nonvolatile memory module. The memory management circuit is electrically connected to the host interface and the memory interface. The memory management circuit is used for executing the following operations: receiving a plurality of instructions; according to a first reading instruction in the plurality of instructions, reading a first physical programming unit by using a plurality of first reading voltage groups in a plurality of reading voltage groups to respectively obtain a plurality of first data, and executing a first decoding operation on each first data in the plurality of first data, wherein the number of the plurality of first reading voltage groups is smaller than that of the plurality of reading voltage groups; and executing other instructions of the plurality of instructions that are different from the first read instruction when failure occurs to perform the first decoding operation on each of the plurality of first data.

In an embodiment of the present invention, after executing operations of other instructions of the plurality of instructions different from the first read instruction, the memory management circuit is further configured to read the first physical program unit using a plurality of second read voltage sets of a plurality of read voltage sets according to the first read instruction to obtain a plurality of second data respectively, and perform the first decoding operation on each of the plurality of second data. Wherein the number of the plurality of second read voltage sets is less than the number of the plurality of read voltage sets and the plurality of second read voltage sets is different from the plurality of first read voltage sets.

In an embodiment of the present invention, when the first decoding operation performed on each of the plurality of second data fails, the memory management circuit is further configured to execute other instructions of the plurality of instructions different from the first read instruction. When the number of the other instructions, which are executed and are different from the first read instruction, reaches a threshold value, the memory management circuit is further configured to read the first physical programming unit to obtain at least one third data according to the first read instruction of the plurality of read instructions, using at least one remaining read voltage set of the plurality of read voltage sets and other than the plurality of second read voltage sets, and performing the first decoding operation on the third data.

In an embodiment of the present invention, when the first decoding operation performed on the third data fails, the memory management circuit is further configured to read the first physical programming unit to obtain a fourth data, and perform a second decoding operation on the fourth data, wherein an algorithm used by the first decoding operation is different from an algorithm used by the second decoding operation.

The invention proposes a memory storage device comprising: the interface unit, the rewritable nonvolatile memory module and the memory control circuit unit are connected. The connection interface unit is used for being electrically connected to a host system. The rewritable nonvolatile memory module is provided with a plurality of physical erasing units, and each physical erasing unit in the plurality of physical erasing units is provided with a plurality of physical programming units. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for executing the following operations: receiving a plurality of instructions; according to a first reading instruction in the plurality of instructions, reading a first physical programming unit by using a plurality of first reading voltage groups in a plurality of reading voltage groups to respectively obtain a plurality of first data, and executing a first decoding operation on each first data in the plurality of first data, wherein the number of the plurality of first reading voltage groups is smaller than that of the plurality of reading voltage groups; and executing other instructions of the plurality of instructions that are different from the first read instruction when failure occurs to perform the first decoding operation on each of the plurality of first data.

In an embodiment of the present invention, after executing operations of other instructions of the plurality of instructions different from the first read instruction, the memory control circuit unit is further configured to read the first physical program unit using a plurality of second read voltage sets of a plurality of read voltage sets according to the first read instruction to obtain a plurality of second data respectively, and perform the first decoding operation on each of the plurality of second data. Wherein the number of the plurality of second read voltage sets is less than the number of the plurality of read voltage sets and the plurality of second read voltage sets is different from the plurality of first read voltage sets.

In an embodiment of the present invention, when the first decoding operation performed on each of the plurality of second data fails, the memory control circuit unit is further configured to execute other instructions of the plurality of instructions different from the first read instruction. When the number of the other instructions, which are executed and are different from the first read instruction, reaches a threshold value, the memory control circuit unit is further configured to read the first physical programming unit to obtain at least one third data according to the first read instruction of the plurality of instructions, using at least one remaining read voltage set out of the plurality of read voltage sets and the plurality of second read voltage sets, and performing the first decoding operation on the third data.

In an embodiment of the present invention, when the first decoding operation performed on the third data fails, the memory control circuit unit is further configured to read the first physical programming unit to obtain a fourth data, and perform a second decoding operation on the fourth data. Wherein the algorithm used by the first decoding operation is different from the algorithm used by the second decoding operation.

Based on the above, the decoding method, the memory control circuit unit and the memory storage device of the present invention can suspend the execution of the decoding corresponding to a read instruction and execute the other subsequent instructions of the read instruction when the re-reading mechanism of the data execution part read by a read instruction fails, thereby reducing the time spent by the subsequent instructions waiting for the previous read instruction to execute the complete decoding operation.

In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention.

FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another example embodiment of the invention.

FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.

FIG. 5 is a schematic block diagram of a rewritable non-volatile memory module according to an example embodiment.

FIG. 6 is a schematic diagram of a memory cell array according to an example embodiment.

FIG. 7 is a graph showing a statistical distribution of gate voltages corresponding to write data stored in a memory cell array according to an example embodiment.

FIG. 8 is a schematic diagram illustrating reading data from a memory cell according to an example embodiment.

Fig. 9 is a schematic diagram illustrating reading data from a memory cell according to another example embodiment.

FIG. 10 is an exemplary schematic diagram of a physical erase unit according to the present exemplary embodiment.

FIG. 11 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

Fig. 12 is a schematic diagram of a multi-frame encoding according to an example embodiment of the invention.

FIG. 13 is a diagram illustrating a re-read mechanism according to an example embodiment.

FIG. 14 is a schematic diagram illustrating multiple read voltage sets for a re-read mechanism according to an example embodiment.

Fig. 15 is a flowchart illustrating a decoding method according to an example embodiment.

[ symbolic description ]

10: memory storage device

11: host system

110: system bus

111: processor and method for controlling the same

112: random access memory

113: read-only memory

114: data transmission interface

12: input/output (I/O) device

20: motherboard

201: portable disk

202: memory card

203: solid state disk

204: wireless memory storage device

205: global positioning system module

206: network interface card

207: wireless transmission device

208: keyboard with keyboard body

209: screen panel

210: horn with horn body

32: SD card

33: CF card

34: embedded memory device

341: embedded multimedia card

342: embedded multi-chip packaging storage device

402: connection interface unit

404: memory control circuit unit

406: rewritable nonvolatile memory module

2202: memory cell array

2204: word line control circuit

2206: bit line control circuit

2208: line decoder

2210: data input/output buffer

2212: control circuit

502: memory cell

504: bit line

506: word line

508: common source line

512: select gate drain transistor

514: select gate source transistor

LSB: least significant bit

CSB: intermediate significant bit

MSB: most significant bit

VA, VA1, VB, VC, VD, VE, VF, VG, 1440 to 1444: reading voltage

702: memory management circuit

704: host interface

706: memory interface

708: error checking and correcting circuit

710: buffer memory

712: power management circuit

801 (1) to 801 (r): position of

820: encoding data

810 (0) to 810 (E): entity programming unit

1410. 1420: distribution of

1430: region(s)

G1 to GX: read voltage set

V1-V1N, V-V2N, V-V3N, V-V4N, V5-V5N, VX-VXN: reading voltage

S1501: step of receiving a plurality of instructions

S1503: reading the first physical programming unit by using a plurality of first read voltage sets of the plurality of read voltage sets according to a first read command of the plurality of commands to obtain a plurality of first data, and performing a first decoding operation on each of the plurality of first data

S1505: judging whether one of the plurality of first data is successfully decoded

S1507: executing the step of executing the other instructions of the plurality of instructions than the first read instruction

S1509: reading the first physical programming unit using a plurality of second read voltage sets of the plurality of read voltage sets according to the first read command to obtain a plurality of second data, and performing a first decoding operation on each of the second data

S1511: judging whether one of the plurality of second data is successfully decoded

S1513: executing the step of executing the other instructions of the plurality of instructions than the first read instruction

S1515: when the number of the other instructions which are executed and are different from the first reading instruction reaches a threshold value, reading the first physical programming unit by using the rest reading voltage groups in the plurality of reading voltage groups according to the first reading instruction to obtain third data, and executing a first decoding operation on the third data

Detailed Description

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Memory storage devices are typically used with host systems so that the host system can write data to or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another example embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a random access memory (random access memory, RAM) 112, a Read Only Memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 are electrically connected to a system bus 110.

In the present exemplary embodiment, the host system 11 is electrically connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 is electrically connected to the I/O device 12 through the system bus 110. For example, host system 11 may transmit output signals to I/O device 12 or receive input signals from I/O device 12 via system bus 110.

In the present exemplary embodiment, the processor 111, the ram 112, the rom 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 can be electrically connected to the memory storage device 10 through a wired or wireless manner via the data transmission interface 114. The memory storage device 10 may be, for example, a flash drive 201, a memory card 202, a solid state disk (Solid State Drive, SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, a near field communication (Near Field Communication, NFC) memory storage, a wireless facsimile (WiFi) memory storage, a Bluetooth (Bluetooth) memory storage, or a Bluetooth low energy memory storage (iBeacon) or the like based on a variety of wireless communication technologies. In addition, the motherboard 20 may also be electrically connected to various I/O devices such as a global positioning system (Global Positioning System, GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

In an example embodiment, the host system referred to is any system that can cooperate with substantially a memory storage device to store data. Although the host system is described in the above exemplary embodiment as a computer system, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may be a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be a variety of nonvolatile memory storage devices such as an SD card 32, a CF card 33, or an embedded storage device 34. The embedded memory device 34 includes embedded memory devices of various types, such as an embedded multimedia card (eMMC) 341 and/or an embedded multi-chip package memory device (embedded Multi Chip Package, eMCP) 342, which directly electrically connects the memory module to the substrate of the host system.

Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404, and a rewritable nonvolatile memory module 406.

In the present exemplary embodiment, the connection interface unit 402 is compatible with the serial advanced attachment (Serial Advanced Technology Attachment, SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may be a Flash Memory Card (MMC) interface standard, an embedded multimedia Memory Card (Embedded Multimedia Card, eMMC) interface standard, a universal Digital (Universal Flash Storage, UFS) interface standard, an Ultra High Speed-I (UHS-I) interface standard, a Ultra High Speed-II (UHS-II) interface standard, a Memory Stick (MS) interface standard, a Multi-Chip Package (Multi-Chip Package) interface standard, a multimedia Card (MMC) interface standard, an embedded multimedia Card (Embedded Multimedia Card, eMMC) interface standard, a universal Flash Memory (Universal Flash Storage, UFS) interface standard, an embedded Multi-Chip Package (embedded Multi Chip Package, eMMC) interface standard, a Flash Memory Card (Flash) interface standard, a Compact Flash drive (Compact Flash) interface standard, or other integrated Flash drive standard, which are compliant with the parallel advanced accessory (Parallel Advanced Technology Attachment, PATA) standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in a single chip, or the connection interface unit 402 may be disposed off-chip with the memory control circuit unit 404.

The memory control circuit unit 404 is configured to execute a plurality of logic gates or control instructions implemented in hardware or firmware and perform operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to the instructions of the host system 11.

The rewritable nonvolatile memory module 406 is electrically connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 may be a single-Level memory Cell (Single Level Cell, SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a Multi-Level memory Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a complex-Level memory Cell (Triple Level Cell, TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.

The memory cells in the rewritable nonvolatile memory module 406 are arranged in an array. The memory cell array will be described below in terms of a two-dimensional array. However, it should be noted that the following exemplary embodiment is only one example of a memory cell array, and in other exemplary embodiments, the configuration of the memory cell array may be adjusted to meet the practical requirements.

FIG. 5 is a schematic block diagram of a rewritable non-volatile memory module according to an example embodiment. FIG. 6 is a schematic diagram of a memory cell array according to an example embodiment.

Referring to fig. 5 and 6, the rewritable nonvolatile memory module 406 includes a memory cell array 2202, a word line control circuit 2204, a bit line control circuit 2206, a column decoder 2208, a data input/output buffer 2210 and a control circuit 2212.

In the present example embodiment, the memory cell array 2202 may include a plurality of memory cells 502 for storing data, a plurality of select gate drain (select gate drain, SGD) transistors 512 and a plurality of select gate source (select gate source, SGS) transistors 514, and a plurality of bit lines 504, a plurality of word lines 506, and a common source line 508 (as shown in fig. 6) connecting such memory cells. Memory cells 502 are arranged in an array (or stacked in a three-dimensional fashion) at the intersections of bit lines 504 and word lines 506. When a write command or a read command is received from the memory control circuit unit 404, the control circuit 2212 controls the word line control circuit 2204, the bit line control circuit 2206, the row decoder 2208, the data input/output buffer 2210 to write data into the memory cell array 2202 or read data from the memory cell array 2202, wherein the word line control circuit 2204 is used for controlling the voltage applied to the word line 506, the bit line control circuit 2206 is used for controlling the voltage applied to the bit line 504, the row decoder 2208 selects the corresponding bit line according to the column address in the command, and the data input/output buffer 2210 is used for temporarily storing data.

The memory cells in the rewritable nonvolatile memory module 406 store multiple bits (bits) with a change in threshold voltage. Specifically, there is a charge trapping layer between the control gate (control gate) and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This process of changing the threshold voltage is also referred to as "writing data to a memory cell" or "programming a memory cell". Each memory cell of the memory cell array 2202 has a plurality of memory states as the threshold voltage changes. And the memory cell can be judged to be in which memory state by reading the voltage, thereby obtaining the bit stored by the memory cell.

Referring to fig. 7, taking MLC NAND type flash memory as an example, each memory cell has 4 memory states along with different threshold voltages, and these memory states represent bits of "11", "10", "00", and "01", respectively. In other words, each memory state includes a least significant bit (Least Significant Bit, LSB) and a most significant bit (Most Significant Bit, MSB). In the present exemplary embodiment, the 1 st bit from the left side in the memory states (i.e., "11", "10", "00", and "01") is the LSB, and the 2 nd bit from the left side is the MSB. Thus, in this example embodiment, each memory cell may store 2 bits. It should be understood that the correspondence between the threshold voltages and the memory states shown in fig. 7 is only an example. In another exemplary embodiment of the present invention, the threshold voltage and the memory state may be arranged in the order of "11", "10", "01" and "00", or other arrangements as the threshold voltage is larger. Further, in another exemplary embodiment, the 1 st bit from the left side may be defined as the MSB, and the 2 nd bit from the left side may be defined as the LSB.

In an exemplary embodiment in which a memory cell can store multiple bits (e.g., MLC or TLC NAND flash memory modules), physical program cells belonging to the same word line can be categorized into at least a lower physical program cell and an upper physical program cell. For example, in an MLC NAND flash memory module, the least significant bit (Least Significant Bit, LSB) of a memory cell belongs to the lower physical programming cell, and the most significant bit (Most Significant Bit, MSB) of the memory cell belongs to the upper physical programming cell. In an exemplary embodiment, the lower physical programming unit is also referred to as a fast page (fast page), and the upper physical programming unit is also referred to as a slow page (slow page). In addition, in the TLC NAND flash memory module, the least significant bit (Least Significant Bit, LSB) of a memory cell belongs to the lower physical program cell, the middle significant bit (Center Significant Bit, CSB) of the memory cell belongs to the middle physical program cell, and the most significant bit (Most Significant Bit, MSB) of the memory cell belongs to the upper physical program cell.

Fig. 8 is a schematic diagram showing reading data from a memory cell according to an exemplary embodiment, which is exemplified by MLC NAND type flash memory.

Referring to FIG. 8, the read operation of the memory cells of the memory cell array 2202 is performed by applying read voltages VA-VC to the control gates to identify the data stored by the memory cells by the conductive state of the memory cell channels. The verification bit (VA) is used to indicate whether the memory cell channel is conductive when the read voltage VA is applied; the verify bit (VC) is used to indicate whether the memory cell channel is conductive or not when the read voltage VC is applied; the Verify Bit (VB) is used to indicate whether the memory cell channel is conducting or not when the read voltage VB is applied. It is assumed here that the corresponding memory cell channel is turned on when the verification bit is "1", and that the corresponding memory cell channel is not turned on when the verification bit is "0". As shown in fig. 8, the stored bits (VA) to (VC) can be obtained by determining which storage state the memory cell is in.

Referring to fig. 9, taking a TLC NAND type flash memory as an example, each memory state includes a least significant bit LSB of the 1 st bit from the left, a middle significant bit (Center Significant Bit, CSB) of the 2 nd bit from the left, and a most significant bit MSB of the 3 rd bit from the left. In this example, the memory cell has 8 memory states (i.e., "111", "110", "100", "101", "001", "000", "010" and "011") according to different threshold voltages. By applying the read voltages VA through VG to the control gates, the bits stored by the memory cells can be identified.

It should be noted that the arrangement order of the 8 storage states in fig. 9 may be defined according to the design of the manufacturer, and is not limited to the arrangement manner of the present example.

In addition, the memory cells of the rewritable nonvolatile memory module 406 form a plurality of physical program units, and the physical program units form a plurality of physical erase units. Specifically, the memory cells on the same word line in FIG. 6 constitute one or more physical programming units. For example, if the rewritable nonvolatile memory module 406 is an MLC NAND type flash memory module, the memory cells at the intersections of the same word line and the plurality of bit lines form 2 physical program units, i.e., an upper physical program unit and a lower physical program unit. And an upper physical programming unit and a lower physical programming unit may be collectively referred to as a physical programming unit group. In particular, if the data to be read is located in a lower physical program unit of a physical program unit group, the read voltage VA shown in fig. 8 can be used to identify the value of each bit in the lower physical program unit. If the data to be read is located in an upper physical program unit of a physical program unit group, the read voltage VB and the read voltage VC shown in FIG. 8 can be used to identify the value of each bit in the upper physical program unit.

Alternatively, if the rewritable nonvolatile memory module 406 is a TLC NAND flash memory module, the memory cells at the intersections of the same word line and the bit lines form 3 physical program units, i.e., an upper physical program unit, a middle physical program unit, and a lower physical program unit. And an upper physical programming unit, a middle physical programming unit, and a lower physical programming unit may be collectively referred to as a physical programming unit group. In particular, if the data to be read is located in a lower physical program unit of a physical program unit group, the read voltage VA shown in fig. 9 can be used to identify the value of each bit in the lower physical program unit. If the data to be read is located in a physical program unit of a physical program unit group, the read voltage VB and the read voltage VC shown in fig. 9 can be used to identify the value of each bit in the physical program unit. If the data to be read is located in an upper physical program unit of a physical program unit group, the read voltage VD, the read voltage VE, the read voltage VF and the read voltage VG shown in fig. 9 can be used to identify the value of each bit in the upper physical program unit.

In the present exemplary embodiment, the physical programming unit is the minimum unit of programming. That is, the physical programming unit is the smallest unit of write data. For example, the physical programming unit is a physical page (page) or a physical sector (sector). If the physical programming units are physical pages, the physical programming units typically include data bits and redundancy bits. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is for storing system data (e.g., error correction codes). In the present exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, 8, 16 or a greater or lesser number of physical fans may be included in the data bit zone, and the size of each physical fan may be greater or lesser. On the other hand, a physical erase unit is the minimum unit of erase. That is, each physically erased cell contains a minimum number of memory cells that are erased together. For example, the physical erased cells are physical blocks (blocks).

Referring to fig. 10, in the present exemplary embodiment, it is assumed that one physical erasing unit is composed of a plurality of physical programming unit groups, wherein each physical programming unit group includes a lower physical programming unit, a middle physical programming unit and an upper physical programming unit composed of a plurality of memory cells arranged on the same word line. For example, in the physical erase unit, the 0 th physical program unit belonging to the lower physical program unit, the 1 st physical program unit belonging to the middle physical program unit, and the 2 nd physical program unit belonging to the upper physical program unit are regarded as one physical program unit group. Similarly, the 3 rd, 4 th and 5 th physical programming units are considered as a physical programming unit group, and other physical programming units are also divided into a plurality of physical programming unit groups according to the method.

Referring to FIG. 11, the memory control circuit unit 404 includes a memory management circuit 702, a host interface 704, a memory interface 706, and an error checking and correcting circuit 708.

The memory management circuit 702 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 702 has a plurality of control commands, and the control commands are executed to perform writing, reading and erasing operations of data while the memory storage device 10 is in operation. The operation of the memory management circuit 702 or any of the circuit elements included in the memory control circuit unit 404 is described as follows, which is equivalent to describing the operation of the memory control circuit unit 404.

In the present exemplary embodiment, the control instructions of the memory management circuit 702 are implemented in firmware. For example, the memory management circuit 702 has a microprocessor unit (not shown) and a read-only memory (not shown), and the control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

In another example embodiment, the control instructions of the memory management circuit 702 may also be stored in program code form in a specific area of the rewritable non-volatile memory module 406 (e.g., a system area of the memory module dedicated to storing system data). In addition, the memory management circuit 702 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (boot code), and when the memory control circuit 404 is enabled, the microprocessor unit executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 702. Then, the microprocessor unit operates the control instructions to perform operations such as writing, reading and erasing of data.

Furthermore, in another example embodiment, the control instructions of the memory management circuit 702 may also be implemented in a hardware type. For example, the memory management circuit 702 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups thereof of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read instruction sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erase circuit is configured to issue an erase command sequence to the rewritable nonvolatile memory module 406 to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, read command sequence, and erase command sequence may include one or more program codes or command codes, respectively, and are used to instruct the rewritable nonvolatile memory module 406 to perform the corresponding write, read, erase, etc. In an example embodiment, the memory management circuitry 702 may also issue other types of sequences of instructions to the rewritable non-volatile memory module 406 to instruct the corresponding operations to be performed.

The host interface 704 is electrically connected to the memory management circuit 702 and is used for receiving and recognizing commands and data transmitted by the host system 11. That is, the instructions and data transmitted by the host system 11 are transmitted to the memory management circuit 702 through the host interface 704. In the present exemplary embodiment, host interface 704 is compliant with the SATA standard. However, it must be understood that the present invention is not limited thereto, and the host interface 704 may also be compatible with PATA standards, IEEE 1394 standards, PCI Express standards, USB standards, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC standards, UFS standards, CF standards, IDE standards, or other suitable data transfer standards.

The memory interface 706 is electrically connected to the memory management circuit 702 and is used to access the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format acceptable to the rewritable nonvolatile memory module 406 through the memory interface 706. Specifically, if the memory management circuit 702 is to access the rewritable nonvolatile memory module 406, the memory interface 706 transmits a corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence that indicates write data, a read instruction sequence that indicates read data, an erase instruction sequence that indicates erase data, and corresponding instruction sequences to indicate various memory operations (e.g., changing read voltage levels or performing garbage collection procedures, etc.). These sequences of instructions are, for example, generated by memory management circuitry 702 and transferred to rewritable non-volatile memory module 406 through memory interface 706. These instruction sequences may include one or more signals, or data, on a bus. Such signals or data may include instruction code or program code. For example, the read instruction sequence may include information such as a read identification code and a memory address.

The error checking and correcting circuit 708 is electrically connected to the memory management circuit 702 and is used for performing an error checking and correcting procedure to ensure the correctness of the data. Specifically, when the memory management circuit 702 receives a write command from the host system 11, the error checking and correcting circuit 708 generates a corresponding error correction code (error correcting code, ECC) and/or error checking code (error detecting code, EDC) for the data corresponding to the write command, and the memory management circuit 702 writes the data corresponding to the write command and the corresponding error correction code and/or error checking code into the rewritable nonvolatile memory module 406. Then, when the memory management circuit 702 reads data from the rewritable nonvolatile memory module 406, it reads the error correction code and/or the error check code corresponding to the data at the same time, and the error check and correction circuit 708 performs an error check and correction procedure on the read data according to the error correction code and/or the error check code.

In an exemplary embodiment, the memory control circuit unit 404 further includes a buffer memory 710 and a power management circuit 712.

The buffer memory 710 is electrically connected to the memory management circuit 702 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 712 is electrically connected to the memory management circuit 702 and is used for controlling the power of the memory storage device 10.

In the present exemplary embodiment, the error checking and correction circuit 708 may perform single-frame (single-frame) encoding for data stored in the same physical programming unit, or may perform multi-frame (multi-frame) encoding for data stored in multiple physical programming units. The single frame coding and the multi-frame coding may employ at least one of coding algorithms such as low density parity check correction codes (low density parity code, LDPC), BCH codes, convolutional codes (convolutional code), or turbo codes (turbo codes), respectively. Alternatively, in an exemplary embodiment, the multi-frame encoding may also employ a Reed-solomon codes (RS codes) algorithm or a exclusive-or (XOR) algorithm. In addition, in another exemplary embodiment, more encoding algorithms not listed above may be used, and will not be described here. Depending on the encoding algorithm employed, the error checking and correction circuit 708 may encode the data to be protected to generate a corresponding error correction code and/or error checking code. For convenience of explanation, the error correction codes and/or error check codes generated by encoding will be collectively referred to as encoded data hereinafter. Fig. 12 is a schematic diagram of a multi-frame encoding according to an example embodiment of the invention.

Referring to fig. 12, taking the example of encoding the data stored in the physical programming units 810 (0) to 810 (E) to generate the corresponding encoded data 820, at least a portion of the data stored in each of the physical programming units 810 (0) to 810 (E) can be regarded as a frame. In multi-frame encoding, the data in the physical programming units 810 (0) to 810 (E) are encoded based on the location of each bit (or byte). For example bit b located at position 801 (1) ₁₁ 、b ₂₁ 、…、b _p1 Will be encoded as bit b in encoded data 820 _o1 Bit b located at position 801 (2) ₁₂ 、b ₂₂ 、…、b _p2 Will be encoded as bit b in encoded data 820 _o2 The method comprises the steps of carrying out a first treatment on the surface of the Similarly, bit b at position 801 (r) _1r 、b _2r 、…、b _pr Will be encoded as bit b in encoded data 820 _or . The data read from the physical programming units 810 (0) to 810 (E) can then be decoded based on the encoded data 820 in an attempt to correct errors that may exist in the read data.

In addition, in another exemplary embodiment of fig. 12, the data used to generate the encoded data 820 may also include redundancy bits (redundancy bits) corresponding to data bits (data bits) in the data stored by the physical programming units 810 (0) to 810 (E). Taking the data stored in the physical programming unit 810 (0) as an example, the redundancy bits are generated by, for example, single frame encoding the data bits stored in the physical programming unit 810 (0). In the present exemplary embodiment, it is assumed that when reading the data in the physical programming unit 810 (0), the data read from the physical programming unit 810 (0) can be decoded by using the redundancy bits (e.g., the encoded data encoded by a single frame) in the physical programming unit 810 (0) for error detection and correction. However, when decoding using the redundant bits in the physical programmer 810 (0) fails (e.g., the number of erroneous bits of the data stored in the physical programmer 810 (0) after decoding is greater than a threshold), a re-Read (Retry-Read) mechanism may be used to attempt to Read the correct data from the physical programmer 810 (0). Details of the re-reading mechanism are described later. When the correct data cannot be Read from the physical programming unit 810 (0) by the re-Read mechanism, the encoded data 820 and the data of the physical programming units 810 (1) to 810 (E) can be Read, and decoding is performed according to the encoded data 820 and the data of the physical programming units 810 (1) to 810 (E), so as to attempt to correct errors in the data stored in the physical programming unit 810 (0). That is, in the present exemplary embodiment, when decoding of encoded data generated using single frame encoding fails and reading of encoded data generated using a re-Read (Retry-Read) mechanism fails, decoding is performed using encoded data generated using multi-frame encoding.

In particular, FIG. 13 is a schematic diagram illustrating a re-reading mechanism according to an example embodiment.

Referring to fig. 13, here, for example, SLC flash memory is taken as an example, distribution 1410 and distribution 1420 are used to represent the memory states of a plurality of first memory cells, and distribution 1410 and distribution 1420 respectively represent different memory states. The first memory units may belong to the same physical programming unit or different physical programming units, and the present invention is not limited thereto. It is assumed herein that when a memory cell belongs to distribution 1410, bit "1" is stored in that memory cell; when a memory cell belongs to distribution 1420, this memory cell stores bit "0". When the memory management circuit 702 reads the memory cell with the read voltage 1440, the memory management circuit 702 obtains a verification bit indicating whether the memory cell is turned on. It is assumed here that the verify bit is "1" when the memory cell is turned on, and is "0" when the memory cell is turned on, but the invention is not limited thereto. If the verification bit is "1", the memory management circuit 702 determines that the memory cell belongs to the distribution 1410, and vice versa is the distribution 1420. However, distribution 1410 overlaps with distribution 1420 in region 1430. That is, there are several memory cells that should belong to distribution 1410 but are identified as distribution 1420, and there are several memory cells that should belong to distribution 1420 but are identified as distribution 1410.

In this example embodiment, when the memory cells are to be read, the memory management circuit 702 selects a predetermined read voltage (e.g., the read voltage 1441) to read the memory cells to obtain the verification bits of the memory cells. The error checking and correction circuit 708 performs decoding operations based on the verification bits of the memory cells to generate a plurality of decoded bits, which may form a decoded data (also referred to as a codeword).

If decoding fails, it means that these memory cells store uncorrectable error bits. If the decoding fails, in the re-read scheme, the memory management circuit 702 re-retrieves another read voltage (e.g., the read voltage 1442) to read the first memory cells to re-retrieve the verification bits of the memory cells. The memory management circuit 702 performs the decoding operation according to the retrieved verification bits to retrieve another decoded data composed of a plurality of decoding bits. In an exemplary embodiment, the error checking and correcting circuit 708 determines whether the other decoded data is a valid codeword according to a syndrome corresponding to the other decoded data. If the other decoded data is not a valid codeword, the memory management circuit 702 determines that decoding has failed. If the number of times of re-fetching the read voltage does not exceed the preset number of times, the memory management circuit 702 re-fetches other read voltages (e.g., the read voltage 1443), and reads the memory cell according to the re-fetched read voltage 1443 to re-fetch the verification bit and perform the first decoding operation.

In other words, when there is an uncorrectable error bit, the verify bit of some memory cells is changed by retrieving the read voltage, thereby having the opportunity to change the decoding result of the decoding operation. Logically, the above-mentioned action of retrieving the read voltage is to flip (flip) bits in a codeword and re-decode the new codeword. In some cases, codewords that cannot be decoded before flipping (with uncorrectable error bits) may be decoded after flipping. Also, in an example embodiment, the memory management circuit 702 may attempt to decode several times until the number of attempts exceeds a predetermined number. However, the present invention is not limited to what the preset number of times is.

It should be noted that the decoding operation performed using the encoded data generated by the single frame encoding can be divided into hard bit (hard bit mode) decoding and soft bit (soft bit mode) decoding. In both the hard bit pattern decoding and soft bit pattern decoding processes, decoding is performed according to the "decoding initial value" of the memory cell. In the hard bit pattern decoding process, the decoding initial value of the memory cell is divided into two values (e.g., n and-n) according to one verification bit. For example, if the verification bit is "1", the memory management circuit 702 sets the decoding initial value of the corresponding memory cell to-n; if the verification bit is "0", the decoding initial value is n. Where n is a positive number, but the invention is not limited to what the value of the positive integer n is. That is, iterative decoding performed according to two values is also called hard bit pattern (hard bit mode) decoding. However, the above-described step of changing the read voltage may also be applied to soft bit pattern (soft bit mode) decoding, in which the decoding initial value of each memory cell is determined according to a plurality of verification bits. It is noted that the probability value of a bit is calculated in iterative decoding, whether it is in a hard bit mode or a soft bit mode, and therefore belongs to the probability decoding algorithm. The detailed implementation of the hard bit mode decoding and the soft bit mode decoding can be known from the prior art, and will not be described herein.

It should be noted that the example of SLC flash memory is illustrated in fig. 13, but the step of retrieving the read voltage may also be applied to MLC or TLC flash memory. As shown in fig. 8, changing the read voltage VA inverts the LSB of one memory cell, and changing the read voltage VB or VC inverts the MSB of one memory cell. Thus, changing the read voltage VA, VB or VC can change one codeword to another codeword. The result of changing the codeword is also applicable to the TLC flash memory of fig. 9. The invention is not limited to SLC, MLC or TLC flash memory. It should be noted that the read voltages VA to VC may be collectively referred to as a read voltage group. The memory management circuit 702 may select a set of read voltages from a plurality of sets of read voltages to read the memory cells, for example.

It should be noted that, in the present embodiment, when a physical program unit in the rewritable nonvolatile memory module 406 is to be read, the memory management circuit 702 first uses a predetermined voltage set to read the physical program unit and performs hard bit pattern decoding according to the data read by using the predetermined voltage set. When decoding fails, the re-reading mechanism described above is performed to perform hard bit pattern decoding again. When a Read failure occurs in the re-Read (Retry-Read) mechanism, the memory management circuit 702 performs soft bit pattern decoding. When the soft bit pattern decoding fails, the memory management circuit 702 decodes the encoded data generated by the multi-frame encoding.

Therefore, the present invention proposes a decoding method, when a certain read instruction (also referred to as a first read instruction) is used to read data from a physical program unit (also referred to as a first physical program unit), if the re-reading mechanism of the portion executed during the reading fails, the memory management circuit 702 will first pause to execute the decoding of the data read from the first physical program unit, and will first execute other instructions (for example, read instructions) subsequent to the first read instruction. After executing the subsequent other instructions, the memory management circuit 702 returns to executing the re-read mechanism for reading according to the first read instruction and executing another portion of the data read by the first read instruction.

In more detail, fig. 14 is a schematic diagram illustrating a plurality of read voltage sets for a re-read mechanism according to an example embodiment. Referring to fig. 14, assume that the memory management circuit 702 receives a plurality of instructions from the host system 11. It is assumed that the instructions include a first read instruction, and that other instructions than the first read instruction are also read instructions. However, in other embodiments, other instructions other than the first read instruction may be other instructions (e.g., a write instruction, an erase instruction, a garbage collection instruction, or a block wear leveling instruction, etc.), which is not limited in the present invention. Assume that a first one of the read instructions is used to read a first physical programming unit. First, the memory management circuit 702 uses a predetermined voltage set (not shown) to read the first physical programming unit and performs hard bit pattern decoding according to the data read using the predetermined voltage set. When the decoding fails, the memory management circuit 702 performs a re-reading mechanism to select the read voltage group G1 as shown in fig. 14, and reads the first physical programming unit according to the read voltages V1 to V1N in the read voltage group G1 to obtain the data read by using the read voltages V1 to V1N. The memory management circuit 702 then again performs hard bit pattern decoding on the data read using the read voltages V1-V1N.

When the hard bit pattern decoding of the data read by the read voltages V1 to V1N fails, the memory management circuit 702 performs a re-reading mechanism to select the read voltage group G2 as shown in fig. 14, and reads the first physical programming unit according to the read voltages V2 to V2N in the read voltage group G2 to obtain the data read by the read voltages V2 to V2N. The memory management circuit 702 then again performs hard bit pattern decoding on the data read using the read voltages V2-V2N.

When the hard bit pattern decoding of the data read by the read voltages V2 to V2N fails, the memory management circuit 702 selects the read voltage group G3 as shown in fig. 14, and reads the first physical programming unit according to the read voltages V3 to V3N in the read voltage group G3 to obtain the data read by the read voltages V3 to V3N. The memory management circuit 702 then again performs hard bit pattern decoding on the data read using the read voltages V3-V3N.

When the hard bit pattern decoding of the data read by the read voltages V3 to V3N fails, the memory management circuit 702 performs a re-reading mechanism to select the read voltage group G4 as shown in fig. 14, and reads the first physical programming unit according to the read voltages V4 to V4N in the read voltage group G4 to obtain the data read by the read voltages V4 to V4N. The memory management circuit 702 then again performs hard bit pattern decoding on the data read using the read voltages V4-V4N.

When the hard bit pattern decoding of the data read by the read voltages V4 to V4N fails, the memory management circuit 702 performs a re-reading mechanism to select the read voltage group G5 as shown in fig. 14, and reads the first physical programming unit according to the read voltages V5 to V5N in the read voltage group G5 to obtain the data read by the read voltages V5 to V5N. The memory management circuit 702 then again performs hard bit pattern decoding on the data read using the read voltages V5-V5N.

When the hard bit pattern decoding of the data read by the read voltages V5 to V5N fails, the memory management circuit 702 pauses the execution of the first read command and executes at least one other command (also referred to as a first other command) different from the first read command after the first read command. In this embodiment, the number of the first other instructions is three, for example. In this embodiment, it is assumed that the first read instruction is the first instruction among all the instructions, and the first other instruction is the second, third and fourth instructions among all the instructions. However, the present invention is not intended to limit the number of first other instructions.

Here, the read voltage groups G1 to G5 may be collectively referred to as "first read voltage groups". The data read from the first physical programming unit using the read voltage groups G1 to G5 and used for performing hard bit pattern decoding may be collectively referred to as "first data". The operation of hard bit pattern decoding may be referred to as a "first decoding operation". It should be noted that the number of the first read voltage sets is five in the present embodiment, however, in a preferred embodiment, the number of the first read voltage sets is greater than or equal to five and less than or equal to ten.

It is assumed that after successful execution of the first further instruction, the memory management circuit 702 returns to executing the first read instruction. More specifically, the memory management circuit 702 sequentially executes the re-read mechanism, which has not been executed before, according to the first read command to select the read voltage group G6 (not shown) in fig. 14, reads the first physical program unit according to the read voltage in the read voltage group G6, and executes the hard bit pattern decoding again according to the read data.

When decoding the data read out using the read voltage group G6 fails, the memory management circuit 702 again performs the re-read mechanism. It is assumed that in the subsequent re-read mechanism, the memory management circuit 702 may suspend the execution of the first read command and execute at least one second other command subsequent to the first other command when a failure occurs in the memory management circuit 702 to perform hard bit pattern decoding on the data (also referred to as second data) read by the read voltage sets G7 to G10 (not shown). In this embodiment, the number of the second other instructions is, for example, three. In this embodiment, it is assumed that the first other instruction refers to the instruction ordered in the second, third, and fourth among all instructions, and thus the second other instruction is the instruction ordered in the fifth, sixth, and seventh among all instructions. In addition, the read voltage groups G6 to G10 may be collectively referred to as "second read voltage groups". It should be noted that the first other instruction and the second other instruction may be collectively referred to as "other instructions different from the first read instruction".

Assume that after successfully executing the second other instruction, the memory management circuit 702 determines, for example, whether the number of instructions that were successfully executed subsequent to the first read instruction (i.e., the number of other instructions that have been executed that are different from the first read instruction) reaches a threshold value. When the number of other instructions that have been executed and are different from the first read instruction is not greater than the threshold value, if the re-reading mechanism of the memory management circuit 702 fails to execute a part of the re-reading mechanism again, the memory management circuit 702 may again suspend executing the first read instruction and execute the plurality of instructions ordered after the second other instruction.

However, when the number of other instructions than the first read instruction that have been executed is greater than the threshold, the memory management circuit 702 returns to executing the first read instruction to complete the complete decoding process (e.g., the remaining unexecuted re-read mechanism and soft bit pattern decoding). More specifically, the memory management circuit 702 sequentially executes the re-reading mechanism described above to select the set of read voltages G11 (not shown) in fig. 14 according to the first read command, reads the first physical programming unit according to the read voltages in the set of read voltages G11, and performs hard bit pattern decoding again according to the read data. When decoding the data read out using the read voltage group G11 fails, the memory management circuit 702 again performs the re-reading mechanism. It is assumed that in the subsequent re-reading mechanism, when the memory management circuit 702 fails to perform the hard bit pattern decoding on the data read using the read voltage sets G12 (not shown) to GX, the memory management circuit 702 does not suspend the execution of the first read command and performs the soft bit pattern decoding (also referred to as the second decoding operation) according to the first read command. In more detail, the memory management circuit 702 may read the first physical programming unit to obtain a data (also referred to as a fourth data) using other read voltage sets (not shown), for example, and perform soft bit pattern decoding on the fourth data.

The data read out using the read voltage groups G11 to GX may be collectively referred to as "third data".

Referring to fig. 15, in step S1501, the memory management circuit 702 receives a plurality of instructions. In step S1503, the memory management circuit 702 reads the first physical programming unit using a plurality of first read voltage sets of the plurality of read voltage sets according to a first read instruction of the plurality of instructions to obtain a plurality of first data, respectively, and performs a first decoding operation on each of the first data. In step S1505, the memory management circuit 702 determines whether one of the plurality of first data is successfully decoded. When one of the plurality of first data is successfully decoded, the flow of fig. 15 is ended. When the first decoding operation performed on each of the plurality of first data fails, the memory management circuit 702 executes other instructions of the plurality of instructions different from the first read instruction in step S1507. After executing the other instructions different from the first read instruction, in step S1509, the memory management circuit 702 reads the first physical programming unit using the plurality of second read voltage sets of the plurality of read voltage sets according to the first read instruction to obtain a plurality of second data respectively, and performs a first decoding operation on each of the second data. In step S1511, the memory management circuit 702 determines whether one of the plurality of second data is successfully decoded. When one of the plurality of second data is successfully decoded, the flow of fig. 14 is ended. When the first decoding operation performed on each of the plurality of second data fails, in step S1513, the memory management circuit 702 executes other instructions of the plurality of read instructions that are different from the first read instruction. Thereafter, in step S1515, when the number of other instructions of the plurality of instructions that have been executed other than the first read instruction reaches a threshold value, the memory management circuit 702 reads the first physical program unit to obtain third data using the remaining read voltage groups of the plurality of read voltage groups according to the first read instruction, and performs a first decoding operation on the third data.

In summary, the decoding method, the memory control circuit unit and the memory storage device according to the present invention can suspend the decoding of a read instruction and execute other subsequent instructions of the read instruction when the re-reading mechanism of the data execution portion read by a read instruction fails, thereby avoiding the time spent by the subsequent instructions waiting for the previous read instruction to execute the complete decoding operation.

Although the invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather may be modified and practiced by those skilled in the art without departing from the spirit and scope of the present invention.

Claims

1. A decoding method for a rewritable non-volatile memory module having a plurality of physical erase units, each physical erase unit of the plurality of physical erase units having a plurality of physical program units, the decoding method comprising:

receiving a plurality of instructions;

Reading a first physical programming unit by using a plurality of first read voltage groups of a plurality of read voltage groups according to a first read instruction of the plurality of instructions to obtain a plurality of first data respectively, and performing a first decoding operation on each of the plurality of first data, wherein the number of the plurality of first read voltage groups is smaller than the number of the plurality of read voltage groups;

suspending execution of the first read instruction and the first decoding operation and executing other instructions of the plurality of instructions other than the first read instruction when failure occurs to perform the first decoding operation on each of the plurality of first data; and

after executing other instructions of the plurality of instructions than the first read instruction, returning to executing the first read instruction and the first decode operation.

2. The decoding method of claim 1, wherein after the step of executing other ones of the plurality of instructions than the first read instruction, the method further comprises:

reading the first physical program unit using a plurality of second read voltage groups among a plurality of read voltage groups to obtain a plurality of second data, respectively, according to the first read command, and performing the first decoding operation on each of the plurality of second data,

Wherein the number of the plurality of second read voltage sets is less than the number of the plurality of read voltage sets and the plurality of second read voltage sets is different from the plurality of first read voltage sets.

3. The decoding method of claim 2, the method further comprising:

executing other instructions of the plurality of instructions that are different from the first read instruction when failure occurs to perform the first decoding operation on each of the plurality of second data; and

when the number of instructions of the plurality of instructions that have been executed other than the first read instruction reaches a threshold,

according to the first read command of the plurality of commands, the first physical programming unit is read by using at least one remaining read voltage set out of the plurality of read voltage sets and the plurality of first read voltage sets to obtain at least one third data, and the first decoding operation is performed on the third data.

4. The decoding method of claim 3, the method further comprising:

when the first decoding operation performed on the third data fails, reading the first physical programming unit to obtain fourth data, and performing a second decoding operation on the fourth data,

Wherein the algorithm used by the first decoding operation is different from the algorithm used by the second decoding operation.

5. The decoding method of claim 1, wherein a number of the plurality of first read voltage sets is greater than or equal to five and a number of the plurality of first read voltage sets is less than or equal to ten.

6. The decoding method of claim 1, wherein the number of other instructions than the first read instruction is three.

7. The decoding method of claim 1, wherein the other instruction than the first read instruction is a read instruction.

8. A memory control circuit unit for a rewritable non-volatile memory module having a plurality of physical erase units, each physical erase unit of the plurality of physical erase units having a plurality of physical program units, the memory control circuit unit comprising:

the host interface is used for being electrically connected to a host system;

a memory interface electrically connected to the rewritable non-volatile memory module; and

a memory management circuit electrically connected to the host interface and the memory interface,

Wherein the memory management circuit is configured to receive a plurality of instructions,

wherein the memory management circuit is further configured to read the first physical program unit using a plurality of first read voltage sets of a plurality of read voltage sets according to a first read instruction of the plurality of instructions to obtain a plurality of first data, respectively, and perform a first decoding operation on each of the plurality of first data, wherein the number of the plurality of first read voltage sets is smaller than the number of the plurality of read voltage sets,

the memory management circuit is further configured to suspend execution of the first read instruction and the first decoding operation and execute other instructions of the plurality of instructions other than the first read instruction when failure occurs in execution of the first decoding operation on each of the plurality of first data, and

after the memory management circuit executes other instructions of the plurality of instructions than the first read instruction, return to executing the first read instruction and the first decode operation.

9. The memory control circuit unit of claim 8, wherein after execution of operation of an instruction of the plurality of instructions other than the first read instruction,

The memory management circuit is further configured to read the first physical program unit using a plurality of second read voltage sets of a plurality of read voltage sets according to the first read command to obtain a plurality of second data, respectively, and perform the first decoding operation on each of the plurality of second data,

10. The memory control circuit unit of claim 9, wherein,

the memory management circuit is further configured to execute other instructions of the plurality of instructions than the first read instruction when the failure of performing the first decoding operation on each of the plurality of second data occurs, and

the memory management circuit is further configured to read the first physical programming unit to obtain at least one third data by using at least one remaining read voltage set out of the plurality of read voltage sets and the plurality of second read voltage sets according to the first read command of the plurality of commands, and perform the first decoding operation on the third data.

11. The memory control circuit unit of claim 10, wherein,

the memory management circuit is further configured to read the first physical programming unit to obtain fourth data and perform a second decoding operation on the fourth data when the first decoding operation on the third data fails,

12. The memory control circuit unit of claim 8, wherein a number of the plurality of first read voltage groups is greater than or equal to five and a number of the plurality of first read voltage groups is less than or equal to ten.

13. The memory control circuit unit of claim 8, wherein the number of other instructions than the first read instruction is three.

14. The memory control circuit unit of claim 8, wherein the other instruction than the first read instruction is a read instruction.

15. A memory storage device, comprising:

the connection interface unit is used for being electrically connected to the host system;

a rewritable non-volatile memory module having a plurality of physical erase units, each physical erase unit of the plurality of physical erase units having a plurality of physical program units; and

A memory control circuit unit electrically connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuit unit is configured to receive a plurality of instructions,

wherein the memory control circuit unit is further configured to read the first physical program unit using a plurality of first read voltage groups of a plurality of read voltage groups according to a first read instruction of the plurality of instructions to obtain a plurality of first data, respectively, and perform a first decoding operation on each of the plurality of first data, wherein the number of the plurality of first read voltage groups is smaller than the number of the plurality of read voltage groups,

the memory control circuit unit is further configured to suspend execution of the first read instruction and the first decoding operation and execute other instructions of the plurality of instructions different from the first read instruction when failure occurs in execution of the first decoding operation on each of the plurality of first data, and

after the memory control circuit unit executes the other instructions of the plurality of instructions other than the first read instruction, execution of the first read instruction and the first decoding operation are returned.

16. The memory storage device of claim 15, wherein after execution of operation of an instruction of the plurality of instructions other than the first read instruction,

the memory control circuit unit is further configured to read the first physical program unit using a plurality of second read voltage sets of a plurality of read voltage sets according to the first read command to obtain a plurality of second data, respectively, and perform the first decoding operation on each of the plurality of second data,

17. The memory storage device of claim 16, wherein,

the memory control circuit unit is further configured to execute other instructions of the plurality of instructions than the first read instruction when the failure of performing the first decoding operation on each of the plurality of second data occurs, and

The memory control circuit unit is further configured to read the first physical programming unit to obtain at least one third data by using at least one remaining read voltage set out of the plurality of read voltage sets and the plurality of second read voltage sets according to the first read command of the plurality of commands, and perform the first decoding operation on the third data.

18. The memory storage device of claim 17, wherein,

when the first decoding operation on the third data fails, the memory control circuit unit is further configured to read the first physical programming unit to obtain fourth data, and perform a second decoding operation on the fourth data,

19. The memory storage device of claim 15, wherein a number of the plurality of first read voltage sets is greater than or equal to five and a number of the plurality of first read voltage sets is less than or equal to ten.

20. The memory storage device of claim 15, wherein the number of other instructions other than the first read instruction is three.

21. The memory storage device of claim 15, wherein the other instructions than the first read instruction are read instructions.