CN111435208A - Liquid crystal display device, liquid crystal display panel and driving method thereof - Google Patents
Liquid crystal display device, liquid crystal display panel and driving method thereof Download PDFInfo
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- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 52
- 238000000034 method Methods 0.000 title claims description 14
- 239000003990 capacitor Substances 0.000 claims abstract description 78
- 239000002184 metal Substances 0.000 claims description 24
- 230000001105 regulatory effect Effects 0.000 claims description 4
- 101150037603 cst-1 gene Proteins 0.000 description 30
- 101100006548 Mus musculus Clcn2 gene Proteins 0.000 description 14
- 230000003071 parasitic effect Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 7
- 101100489584 Solanum lycopersicum TFT1 gene Proteins 0.000 description 5
- 101100214488 Solanum lycopersicum TFT2 gene Proteins 0.000 description 5
- 230000005684 electric field Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
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- 238000012423 maintenance Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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Abstract
The application belongs to the technical field of liquid crystal display, provides a liquid crystal display panel and liquid crystal display device, includes: a data line configured to transmit a data signal; a scan line configured to transmit a scan signal; and a pixel unit formed by interleaving the data line and the scan line, the pixel unit including a first sub-pixel unit and a second sub-pixel unit; the scanning line connected with the second sub-pixel unit and the pixel electrode of the first sub-pixel unit form a first storage capacitor, and the scanning line connected with the first sub-pixel unit and the pixel electrode of the second sub-pixel unit form a second storage capacitor.
Description
Technical Field
The application belongs to the technical field of liquid crystal display, and particularly relates to a liquid crystal display device, a liquid crystal display panel and a driving method thereof.
Background
In the existing pixel design of the liquid crystal display panel, because the parasitic capacitance Cgs exists between the gate electrode and the source electrode, when the element is turned off after the pixel is charged, the change of the gate voltage generates redistribution action on the liquid crystal capacitance and the storage capacitance charge of the pixel through the parasitic capacitance Cgs, so that the voltage after the original pixel is charged generates a kick back phenomenon, and the phenomenon can lead the liquid crystal panel to generate flicker.
In order to make the pixel have enough storage capacitor to maintain the pixel potential during the off period of the TFT, the storage capacitor Cst needs to be designed to store the charge and maintain the pixel potential. In order to allow enough storage capacitance to maintain the pixel potential during the off period of the TFT, the pixel charge leaks through all parasitic capacitances on the pixel before the pixel is turned on for the next charging time, causing a voltage drop in the pixel potential. The pixel potential needs to be maintained by designing the storage capacitor Cst with a large enough size to store charges, which is called voltage maintenance, and the large storage capacitor Cst needs a large area of the common electrode metal electrode, so that the effective pixel aperture ratio is reduced.
Therefore, the conventional technical scheme has the problem that the size of the storage capacitor and the aperture ratio of the effective pixel cannot be compatible.
Disclosure of Invention
In view of this, embodiments of the present disclosure provide a liquid crystal display device, a liquid crystal display panel and a driving method thereof, so as to solve the problem that the size of the storage capacitor and the aperture ratio of the effective pixel are incompatible in the conventional technical solution.
An embodiment of the present application relates to a liquid crystal display panel, including:
a data line configured to transmit a data signal;
a scan line configured to transmit a scan signal; and
the pixel unit is formed by interleaving the data line and the scanning line and comprises a first sub-pixel unit and a second sub-pixel unit;
the scanning line connected with the second sub-pixel unit and the pixel electrode of the first sub-pixel unit form a first storage capacitor, and the scanning line connected with the first sub-pixel unit and the pixel electrode of the second sub-pixel unit form a second storage capacitor.
In one embodiment, a first scanning metal line extends from a scanning line connected to the second sub-pixel unit in the extending direction of the data line, a second scanning metal line extends from a scanning line connected to the first sub-pixel unit in the extending direction of the data line, an overlapping region of the first scanning metal line and the first sub-pixel unit forms the first storage capacitor, and an overlapping region of the second scanning metal line and the second sub-pixel unit forms the second storage capacitor.
In one embodiment, the first storage capacitor has the same size as the second storage capacitor.
In one embodiment, the output voltage of the scan line includes an element on voltage, an element off voltage, and a regulation voltage, the regulation voltage being less than the element off voltage.
An embodiment of the present application provides a liquid crystal display device including:
a data line configured to transmit a data signal;
a scan line configured to transmit a scan signal; and
the pixel unit is formed by interleaving the data line and the scanning line and comprises a first sub-pixel unit and a second sub-pixel unit;
the scanning line connected with the second sub-pixel unit and the pixel electrode of the first sub-pixel unit form a first storage capacitor, and the scanning line connected with the first sub-pixel unit and the pixel electrode of the second sub-pixel unit form a second storage capacitor;
a scan driving unit configured to drive the scan lines.
In one embodiment, a first scanning metal line extends from a scanning line connected to the second sub-pixel unit in the extending direction of the data line, a second scanning metal line extends from a scanning line connected to the first sub-pixel unit in the extending direction of the data line, an overlapping region of the first scanning metal line and the first sub-pixel unit forms the first storage capacitor, and an overlapping region of the second scanning metal line and the second sub-pixel unit forms the second storage capacitor.
In one embodiment, the first storage capacitor has the same size as the second storage capacitor.
In one embodiment, the output voltage of the scan line includes an element on voltage, an element off voltage, and a regulation voltage, the regulation voltage being less than the element off voltage.
An embodiment of the present application further provides a driving method based on the above liquid crystal display panel, where the driving method includes:
inputting a starting voltage to a scanning line input element connected with the first sub-pixel unit, and inputting a regulating voltage to a scanning line connected with the second sub-pixel unit;
inputting a regulating voltage to a scanning line connected with the first sub-pixel unit, and inputting a component starting voltage to a scanning line connected with the second sub-pixel unit;
turning off voltage to a scanning line input element connected with the first sub-pixel unit, and inputting adjusting voltage to a scanning line connected with the second sub-pixel unit;
and turning off the voltage to a scanning line input element connected with the second sub-pixel unit.
In one embodiment, the time for inputting the adjustment voltage to the scan line connected with the first sub-pixel unit is equal to the time for inputting the adjustment voltage to the second sub-pixel unit and the scan line.
The liquid crystal display panel divides the pixel into the first sub-pixel unit and the second sub-pixel unit, the scanning line connected with the second sub-pixel unit and the pixel electrode of the first sub-pixel unit form a first storage capacitor, the scanning line connected with the first sub-pixel unit and the pixel electrode of the second sub-pixel unit form a second storage capacitor, the pixel opening is increased while the storage capacitor is increased, flicker caused by kick back phenomenon can be reduced by increasing the storage capacitor, the light output quantity of the liquid crystal display is increased by increasing the pixel opening, and the display effects of saving energy, saving cost and high brightness can be obtained.
Drawings
Fig. 1 is a schematic view of a pixel unit structure of a liquid crystal display panel according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a pixel unit of a liquid crystal display panel according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of voltage signals of a pixel electrode and a scan line of a first sub-pixel unit of an LCD panel according to a first embodiment of the present disclosure;
FIG. 4 is a schematic diagram of voltage signals of a pixel electrode and a scan line of a second sub-pixel unit of an LCD panel according to a first embodiment of the present disclosure;
FIG. 5 is a schematic diagram of voltage signals of a pixel electrode and a scan line of a first sub-pixel unit of an LCD panel according to a second embodiment of the present disclosure;
FIG. 6 is a schematic diagram of voltage signals of a pixel electrode and a scan line of a second sub-pixel unit of an LCD panel according to a second embodiment of the present application;
fig. 7 is a specific flowchart of a driving method of a liquid crystal display panel according to an embodiment of the present application.
Detailed Description
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "comprises" and "comprising," and any variations thereof, in the description and claims of this application and the drawings described above, are intended to cover non-exclusive inclusions. For example, a process, method, or system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus. Furthermore, the terms "first," "second," and "third," etc. are used to distinguish between different objects and are not used to describe a particular order.
As shown in fig. 1, the present embodiment provides a liquid crystal display panel, which includes data lines 11, scan lines 12, and pixel units 13. Wherein, the data lines 11 are configured to transmit data signals, the scan lines 12 are configured to transmit scan signals, and the pixel units 13 are formed by interleaving the data lines 11 and the scan lines 12.
The pixel unit 13 includes a first sub-pixel unit 131 and a second sub-pixel unit 132, the first sub-pixel unit 131 includes a first liquid crystal capacitor Clc1, a first storage capacitor Cst1, a first parasitic capacitor Cgs1, and a first switching transistor TFT 1; the first liquid crystal capacitor Clc1 is configured to provide a deflection voltage to liquid crystal molecules in the first sub-pixel unit 131, the first storage capacitor Cst1 is configured to provide a voltage sustaining charge to the first liquid crystal capacitor Clc1, a first parasitic capacitor Cgs1 is formed between the scan line 12 and a pixel electrode of the first sub-pixel unit 131, and the first switching transistor TFT1 is configured to provide a data signal to the first liquid crystal capacitor Clc1 and the first storage capacitor Cst 1. The second sub-pixel unit 132 includes a second liquid crystal capacitor Clc2, a second storage capacitor Cst2, a second parasitic capacitor Cgs2, and a second switching transistor TFT 2; the second liquid crystal capacitor Clc2 is configured to provide a deflection voltage to liquid crystal molecules in the second sub-pixel unit 132, the second storage capacitor Cst2 is configured to provide a voltage sustaining charge to the second liquid crystal capacitor Clc2, a second parasitic capacitor Cgs2 is formed between the scan line 12 and a pixel electrode of the second sub-pixel unit 132, and the second switching transistor TFT2 is configured to provide a data signal to the second liquid crystal capacitor Clc2 and the second storage capacitor Cst 2.
The scan line 12 connected to the second sub-pixel unit 132 and the pixel electrode of the first sub-pixel unit 131 form a first storage capacitor Cst1, and the scan line 12 connected to the first sub-pixel unit 131 and the pixel electrode of the second sub-pixel unit 132 form a second storage capacitor Cst 2.
As shown in fig. 2, fig. 2 is a schematic structural diagram of a display panel provided in this embodiment of the present application, where the data lines 11 and the scan lines 12 are arranged in a vertically staggered manner, the pixel electrode of the first sub-pixel unit 131 and the pixel electrode of the second sub-pixel unit 132 are disposed between adjacent scan lines 12, an overlapping region of the pixel electrode of the first sub-pixel unit 131 and the scan line 12 connected to the second sub-pixel unit 132 forms a first storage capacitor Cst1, and an overlapping region of the pixel electrode of the second sub-pixel unit 132 and the scan line 12 connected to the first sub-pixel unit 131 forms a second storage capacitor Cst 2.
In order to prevent the signal voltage on the data line 11 from affecting the pixel voltage on the pixel electrode, which may cause crosstalk and affect the image quality, a safety distance is generally designed between the pixel electrode and the data line 11 to reduce the crosstalk, but the safety distance may cause a reduction in the aperture ratio, accordingly, in the embodiment of the present invention, the scan line 12 extends a scan metal line in the extending direction of the data line 11, the scan metal line is disposed at two sides of the data line 11, so that an electric field is formed between the data line 11 and the scan metal line, and the electric field is reduced from being formed between the data line 11 and the pixel electrode, thereby reducing or eliminating the safety distance between the pixel electrode and the data line 11, and increasing the aperture ratio. In one embodiment, the scan line 12 connected to the second sub-pixel unit 132 extends to form a first scan metal line 121 in the extending direction of the data line 11, the scan line 12 connected to the first sub-pixel unit 131 extends to form a second scan metal line 122 in the extending direction of the data line 11, an overlapping region of the first scan metal line 121 and the first sub-pixel unit 131 forms a first storage capacitor Cst1, and an overlapping region of the second scan metal line 122 and the second sub-pixel unit 132 forms a second storage capacitor Cst 2.
The gate of the first switching transistor TFT1 is connected to the scan line 12, the drain of the first switching transistor TFT1 is connected to the data line 11, and the source of the first switching transistor TFT1 is connected to the pixel electrode of the first sub-pixel 131 to form the first switching transistor TFT 1; the gate of the second switching transistor TFT2 is connected to the scan line 12, the drain of the second switching transistor TFT2 is connected to the data line 11, and the source of the second switching transistor TFT2 is connected to the pixel electrode of the second sub-pixel element 132, thereby forming the second switching transistor TFT 2.
As shown in fig. 7, the present application also provides a driving method of the above liquid crystal display panel, including:
step S110, inputting an element-on voltage VGH to the scan line 12 connected to the first sub-pixel unit 131, and inputting an adjustment voltage V' G L to the scan line 12 connected to the second sub-pixel unit 132;
step S120, inputting a regulation voltage V' G L to the scan line 12 connected to the first sub-pixel unit 131, and inputting an element-on voltage VGH to the scan line 12 connected to the second sub-pixel unit 132;
step S130, inputting an element turn-off voltage VG L to the scan line 12 connected to the first sub-pixel unit 131, and inputting an adjustment voltage V' G L to the scan line 12 connected to the second sub-pixel unit 132;
in step S140, an element turn-off voltage VG L is input to the scan line 12 connected to the second sub-pixel unit 132.
In one embodiment, the time for inputting the adjustment voltage V 'G L to the scan line 12 connected to the first sub-pixel unit 131 is equal to the time for inputting the adjustment voltage V' G L to the second sub-pixel unit 132 and the scan line.
Fig. 3 to 6 are diagrams illustrating the charging timing of the pixel electrode and the voltage driving timing of the scan line 12, where the output voltage of the scan line 12 is composed of the device turn-on voltage VGH, the device turn-off voltage VG L, and the adjusting voltage V ' G L, the adjusting voltage V ' G L is between the device turn-on voltage VGH and the device turn-off voltage VG L, and the adjusting voltage V ' G L is smaller than the device turn-off voltage VG L.
The timing sequence of the scan line 12 is the device turn-off voltage VG L, the adjustment voltage V ' G L for one cycle, the device turn-on voltage VGH for one cycle, the adjustment voltage V ' G L for one cycle, and finally the adjustment voltage VG L1 for one cycle, wherein the timing sequence of the scan line 12 connected to the first sub-pixel unit 131 is later than the timing sequence of the scan line 12 connected to the second sub-pixel unit 131 by one cycle, the output device turn-on voltage VGH of the scan line 12 corresponding to the first sub-pixel unit 131 outputs the adjustment voltage V ' G592, the scan line 12 corresponding to the second sub-pixel unit 131 outputs the adjustment voltage V ' G632, the scan line 12 corresponding to the second sub-pixel unit 131 outputs the adjustment voltage Cst, the scan line 12 output adjustment voltage V ' G L corresponding to the first sub-pixel unit 131, the scan line 12 corresponding to the second sub-pixel unit 132 outputs the adjustment voltage V ' G L, the adjustment voltage V ' G L, the scan line 14 outputs the adjustment voltage VG 12, the first sub-pixel 14, the pixel charge voltage V ' G3614, the pixel storage voltage V ' G3612 corresponding to the second sub-pixel 132, the pixel 14, the pixel storage voltage vgc storage voltage VGH L, the first sub-pixel 14, the pixel charge voltage cgc storage voltage VGH, the pixel 14, the pixel storage voltage VGH, the pixel 14, the pixel charge pixel discharge voltage of the pixel 14, the pixel charge pixel, the pixel charge the pixel through the pixel charge pixel, the pixel discharge voltage of the pixel, the pixel charge the pixel, the pixel charge pixel discharge voltage VG 12, the pixel discharge voltage VG 14, the pixel discharge voltage VG 14, the pixel charge the pixel, the pixel discharge voltage VG 12, the pixel charge the pixel storage voltage VG 12, the pixel by the pixel, the pixel charge the pixel by the pixel discharge voltage VG 14, the pixel by the pixel discharge voltage VG 14, the first pixel discharge voltage VG 14, the pixel charge pixel discharge voltage VG 14, the pixel by the pixel charge pixel by the first pixel by the pixel charge pixel discharge voltage VG 14, the first pixel through the first pixel by the first pixel charge the second pixel by the.
In order to ensure the normal charging of the first sub-pixel unit 131 and the second sub-pixel unit 132, the period time of the adjusting voltage V 'G L is longer than the period time of the turn-on voltage VGH of the first switching tube TFT1 and the second switching tube TFT2, and the charging period of the adjusting voltage V' G L needs to be covered.
In principle, the larger the capacitance value of the storage capacitor, the better, but the size of the storage capacitor is also limited due to the limitation of the design area of the liquid crystal display panel and the like. In addition, for different pixel units, due to the manufacturing process, the liquid crystal capacitance, the storage capacitance, and the parasitic capacitance of the sub-pixel units in different pixel units are different, and therefore, different adjustment voltages are input to different sub-pixel units.
In one embodiment, when N is equal to 1, the size of the first storage capacitor Cst1 should satisfy the following requirement:
Vpixel＝Vdata
ΔV1＝ΔV’1+ΔV”1
ΔV’1＝(VGH-V’GL)*Cgs1/(Cgs1+Cst1+Clc1)
ΔV”1＝(V’GL-VGH)*Cst1/(Cgs1+Cst1+Clc1)
ΔV2＝ΔV’2+ΔV”2
ΔV’2＝(V’GL-VGL)*Cgs1/(Cgs1+Cst1+Clc1)
ΔV”2＝(VGH-V’GL)*Cst1/(Cgs1+Cst1+Clc1)
ΔV3＝(V’GL-VGL)*Cst1/(Cgs1+Cst1+Clc1)
the requirement that the delta V1+ delta V2+ delta V3 is 0
Cst1＝(VGH-VGL)*Cgs1/(VGL-V’GL)
Wherein Vpixel is a voltage value of a pixel electrode in the first sub-pixel unit 131, Vdata is a voltage value of the data line 11, and Clc1, Cst1, Cgs1 are capacitance values of the first liquid crystal capacitor Clc1, the first storage capacitor Cst1, and the first parasitic capacitor Cgs1, respectively.
Also, the size of the second storage capacitor Cst2 should satisfy the following requirement:
Vpixel＝Vdata
ΔV1＝ΔV’1+ΔV”1
ΔV’1＝(VGH-V’GL)*Cgs2/(Cgs2+Cst2+Clc2)
ΔV”1＝(V’GL-VGL)*Cst2/(Cgs2+Cst2+Clc2)
ΔV2＝(V’GL-VGL)*Cgs2/(Cgs2+Cst2+Clc2)
the requirement that the delta V1+ delta V2 is 0
Cst2＝(VGH-VGL)*Cgs2/(VGL-V’GL)
Wherein Vpixel is a voltage value of the pixel electrode in the second sub-pixel unit 132, Vdata is a voltage value of the data line 11, and Clc2, Cst2, Cgs2 are capacitance values of the second liquid crystal capacitor Clc2, the second storage capacitor Cst2, and the second parasitic capacitor Cgs2, respectively.
In another embodiment, when N is 2, the size of the first storage capacitor Cst1 should satisfy the following requirement:
Vpixel＝Vdata
ΔV1＝ΔV’1+ΔV”1
ΔV’1＝(VGH-V’GL)*Cgs1/(Cgs1+Cst1+Clc1)
ΔV”1＝(V’GL-VGH)*Cst1/(Cgs1+Cst1+Clc1)
ΔV2＝(VGH-V’GL)*Cst1/(Cgs1+Cst1+Clc1)
ΔV3＝(V’GL-VGL)*Cgs1/(Cgs1+Cst1+Clc1)
ΔV4＝(V’GL-VGL)*Cst1/(Cgs1+Cst1+Clc1)
the requirement that the delta V1+ delta V2+ delta V3+ delta V4 is 0
Cst1＝(VGH-VGL)*Cgs1/(VGL-V’GL)
Wherein Vpixel is a voltage value of the pixel electrode in the first sub-pixel unit 131, Vdata is a voltage value of the data line 11, Clc1, Cst1, Cgs1 are capacitance values of the first liquid crystal capacitor Clc1, the first storage capacitor Cst1, and the first parasitic capacitor Cgs1, Δ V1 is a voltage drop of the pixel electrode in the first sub-pixel unit 131, and Δ V2 is a voltage difference of the pixel electrode in the first sub-pixel unit 131.
Also, the size of the second storage capacitor Cst2 should satisfy the following requirement:
Vpixel＝Vdata
ΔV1＝(VGH-V’GL)*Cgs2/(Cgs2+Cst2+Clc2)
ΔV2＝(V’GL-VGL)*Cst2/(Cgs2+Cst2+Clc2)
ΔV3＝(V’GL-VGL)*Cgs2/(Cgs2+Cst2+Clc2)
the requirement that the delta V1+ delta V2+ delta V3 is 0
Cst2＝(VGH-VGL)*Cgs2/(VGL-V’GL)
Wherein Vpixel is a voltage value of the pixel electrode in the second sub-pixel unit 132, Vdata is a voltage value of the data line 11, and Clc2, Cst2, Cgs2 are capacitance values of the second liquid crystal capacitor Clc2, the second storage capacitor Cst2, and the second parasitic capacitor Cgs2, respectively.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. A liquid crystal display panel, comprising:
a data line configured to transmit a data signal;
a scan line configured to transmit a scan signal; and
the pixel unit is formed by interleaving the data line and the scanning line and comprises a first sub-pixel unit and a second sub-pixel unit;
the scanning line connected with the second sub-pixel unit and the pixel electrode of the first sub-pixel unit form a first storage capacitor, and the scanning line connected with the first sub-pixel unit and the pixel electrode of the second sub-pixel unit form a second storage capacitor.
2. The liquid crystal display panel according to claim 1, wherein a first scanning metal line extends in the data line extending direction of the scanning line connected to the second sub-pixel unit, a second scanning metal line extends in the data line extending direction of the scanning line connected to the first sub-pixel unit, an overlapping region of the first scanning metal line and the first sub-pixel unit forms the first storage capacitor, and an overlapping region of the second scanning metal line and the second sub-pixel unit forms the second storage capacitor.
3. The liquid crystal display panel according to claim 1, wherein a size of the first storage capacitor is the same as a size of the second storage capacitor.
4. The liquid crystal display panel according to claim 1, wherein the output voltage of the scanning line includes an element-on voltage, an element-off voltage, and a regulation voltage, the regulation voltage being smaller than the element-off voltage.
5. A liquid crystal display device, characterized in that the liquid crystal display device comprises:
a data line configured to transmit a data signal;
a scan line configured to transmit a scan signal; and
the pixel unit is formed by interleaving the data line and the scanning line and comprises a first sub-pixel unit and a second sub-pixel unit;
the scanning line connected with the second sub-pixel unit and the pixel electrode of the first sub-pixel unit form a first storage capacitor, and the scanning line connected with the first sub-pixel unit and the pixel electrode of the second sub-pixel unit form a second storage capacitor;
a scan driving unit configured to drive the scan lines.
6. The liquid crystal display device according to claim 5, wherein a first scanning metal line extends in the data line extending direction of the scanning line connected to the second sub-pixel unit, a second scanning metal line extends in the data line extending direction of the scanning line connected to the first sub-pixel unit, an overlapping region of the first scanning metal line and the first sub-pixel unit forms the first storage capacitor, and an overlapping region of the second scanning metal line and the second sub-pixel unit forms the second storage capacitor.
7. The liquid crystal display device according to claim 5, wherein a size of the first storage capacitor is the same as a size of the second storage capacitor.
8. The liquid crystal display device according to claim 5, wherein the output voltage of the scanning line includes an element-on voltage, an element-off voltage, and a regulation voltage, the regulation voltage being smaller than the element-off voltage.
9. A driving method of the liquid crystal display panel according to any one of claims 1 to 4, wherein the driving method comprises:
inputting a starting voltage to a scanning line input element connected with the first sub-pixel unit, and inputting a regulating voltage to a scanning line connected with the second sub-pixel unit;
inputting a regulating voltage to a scanning line connected with the first sub-pixel unit, and inputting a component starting voltage to a scanning line connected with the second sub-pixel unit;
turning off voltage to a scanning line input element connected with the first sub-pixel unit, and inputting adjusting voltage to a scanning line connected with the second sub-pixel unit;
and turning off the voltage to a scanning line input element connected with the second sub-pixel unit.
10. The liquid crystal display panel according to claim 9, wherein a time for inputting the adjustment voltage to the scan line connected to the first sub-pixel unit is equal to a time for inputting the adjustment voltage to the second sub-pixel unit and the scan line.
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