CN111400119B - Multi-project and multi-platform self-adaptive chip design FPGA prototype verification method and system - Google Patents
Multi-project and multi-platform self-adaptive chip design FPGA prototype verification method and system Download PDFInfo
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Abstract
The invention discloses a multi-project and multi-platform self-adaptive chip design FPGA prototype verification method and a system, wherein the method comprises the steps of executing multi-project and multi-platform initialization, determining a project code number of a chip design and a platform code number for use in testing, generating a file list and a parameter file which are required by the operation of a corresponding project library and a platform environment library, and submitting the file list and the parameter file to a version management warehouse of a corresponding testing platform; and triggering the continuous integration tool to start the client according to the script to perform compiling simulation, synthesis and realization, generating a test report and uploading the test report to the version management warehouse. The invention couples a plurality of chip design projects with a plurality of FPGA prototype verification platform environments, supports the verification developer to flexibly switch a plurality of projects and a plurality of verification platforms in one version management library, and can quickly complete the FPGA prototype verification automation flow of the appointed project appointed platform only by a small amount of configuration.
Description
Technical Field
The invention relates to a prototype verification technology of FPGA chip design, in particular to a multi-project and multi-platform self-adaptive FPGA prototype verification method and a system for chip design.
Background
With the difficulty and challenge of integrated circuit design further increased, in the stage of chip development and verification, the iterative versions of design codes are more and more, and each design version needs to be subjected to functional verification. Because actual requirements and technical indexes are different, a project group can simultaneously develop and verify a plurality of chip designs. Therefore, how to synchronously develop and accelerate the iteration of the verification process of multiple projects is a key problem to be solved in the chip design and verification stage.
For large-scale chips, the verification of the FPGA prototype has become the mainstream method in the field of the functional verification of the current integrated circuit. The running speed of the test platform is generally between several million and several hundred million, and the functional correctness and the performance of the chip design can be tested quickly. At present, a plurality of platforms in the industry can carry out FPGA prototype verification on a large-scale chip, and the emphasis of the verification of each platform is different. In order to ensure that the complete functional verification can be performed on the chip design, the functional correctness of the chip design can be ensured only by ensuring that the chip design can be correctly subjected to FPGA prototype verification based on a plurality of different verification-side-emphasis platforms.
The conventional prototype verification method is shown in fig. 1. In the traditional FPGA prototype verification process, verification developers need to respectively build verification environment libraries based on different platforms on the basis of each project, and when versions of different projects are iterated, switching needs to be performed between different project libraries and different verification environment libraries, so that the situation is limited by the number of testers and the working efficiency. Considering that when the same FPGA prototype verification platform is oriented to different projects, the operating environment and configuration can be kept in use without requiring a large amount of modification, so maintaining multiple different project libraries and verification environment libraries simultaneously is time and labor consuming, and reduces the overall efficiency of prototype verification.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: the invention couples a plurality of chip design projects and a plurality of FPGA prototype verification platform environments together, supports verification developers to flexibly switch a plurality of projects and a plurality of verification platforms in one version management library, and can quickly complete the FPGA prototype verification automation flow of a specified project specified platform by only a small amount of configuration.
In order to solve the technical problems, the invention adopts the technical scheme that:
a multi-project and multi-platform self-adaptive chip design FPGA prototype verification method comprises the following steps:
1) after the version management warehouse receives the design codes of the current design version of the chip submitted by a chip developer, a continuous integration tool is enabled at a test platform version management end, and a continuous integration automation process configuration script is constructed;
2) constructing a platform self-adaptive configuration script, wherein the platform self-adaptive configuration script is used for generating a file list required by the operation of a corresponding project library and a platform environment library and a verification operation parameter file according to an input project code and a test platform code;
3) determining the project code of the chip design to be tested and the platform code of the use test;
4) the platform self-adaptive configuration script generates a file list required by the operation of the corresponding project library and the platform environment library and a verification operation parameter file according to the determined project code of the chip design and the platform code used for testing, and submits the file list to a version management warehouse of the corresponding testing platform;
5) the version management warehouse of each test platform detects a corresponding file submission request, and if a submitted file list required by the running of the platform environment library and a verification running parameter file are detected, a continuous integration tool is triggered to start a specified client runner according to the configuration of a continuous integration automation process configuration script, and a construction task starts to run;
6) the client runner executes tasks to respectively carry out compiling simulation, synthesis, implementation and test processes, and sends a return value to the continuous integration tool through the implementation process after the implementation process;
7) after the continuous integration tool detects that the return value of the implementation process is correct, the client-side operator calls download software and a network interface, and downloads the implemented design file and the test mirror image to the FPGA board to automatically start testing;
8) and the continuous integration tool detects the test progress, automatically analyzes the test result after the test is finished, generates a test report of the current design version, and uploads the test report to the version management warehouse through the accessory.
Optionally, when the item code of the chip design to be tested currently and the platform code to be tested are determined in step 3), the item code of the chip design to be tested currently and the platform code to be tested are determined in one of the following four ways:
the first method is as follows: the project code of a single chip design and the platform code of a single use test;
the second method comprises the following steps: the project code of a single chip design and the platform codes of a plurality of use tests;
the third method comprises the following steps: the project code of a plurality of chip designs and the platform code of a single use test;
the method is as follows: the product code of a plurality of chip designs and the platform code of a plurality of use tests.
Optionally, the step 4) further includes that the platform adaptive configuration script generates a file list and a verification operation parameter file required by the operation of the corresponding item library and the platform environment library according to the determined item code of the chip design and the platform code used for testing, respectively, for a plurality of chip design versions corresponding to the item code of the chip design, and submits the file list and the verification operation parameter file to the version management warehouse of the corresponding testing platform respectively for different chip design versions, and executes the steps 5) -8 once when one chip design version is submitted to the version management warehouse of the corresponding testing platform).
Optionally, the step 6) of performing, by the client runner, compilation simulation, synthesis, implementation and test processes on the client runner execution task respectively specifically means that the client runner execution task calls simulation software, a synthesis tool and an implementation tool respectively to perform the compilation simulation, synthesis, implementation and test processes.
Optionally, step 8) further comprises the step of the persistent integration tool providing the test report of the design version to a developer and/or manager for the chip developer to analyze the test report to further optimize the chip design.
In addition, the invention also provides a multi-project and multi-platform adaptive chip design FPGA prototype verification system which comprises computer equipment, wherein the computer equipment is programmed or configured to independently or cooperatively execute the steps of the multi-project and multi-platform adaptive chip design FPGA prototype verification method.
In addition, the invention also provides a multi-project and multi-platform adaptive chip design FPGA prototype verification system, which comprises computer equipment, wherein a computer program which is programmed or configured to independently or cooperatively execute the multi-project and multi-platform adaptive chip design FPGA prototype verification method is stored on a memory of the computer equipment.
In addition, the present invention also provides a computer readable storage medium having stored thereon a computer program programmed or configured to perform the multi-project and multi-platform adaptive chip design FPGA prototyping method independently or in cooperation.
Compared with the prior art, the invention has the following advantages:
1. the invention can couple a plurality of chip design projects with a plurality of FPGA prototype verification platform environments and can simultaneously support the automatic verification of FPGA prototypes of a plurality of projects and platforms.
2. The invention combines a version management system, a continuous integration tool and a multi-project multi-platform environment together to form continuous integrated multi-project multi-platform self-adaptive FPGA prototype verification automation.
3. The invention can satisfy the parallel execution of prototype verification based on a plurality of different FPGA platforms when a plurality of projects and a plurality of versions are iterated. When a plurality of projects are carried out simultaneously, the invention supports chip testers to flexibly select the test projects and the test platform, reduces manual switching and interference between the project library and the platform library, reduces waste of manpower and energy, and improves the efficiency of prototype verification work.
Drawings
Fig. 1 is a schematic diagram illustrating a verification principle of an FPGA prototype in the prior art.
FIG. 2 is a schematic diagram of a basic flow of a method according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of a principle of verifying an FPGA prototype in the embodiment of the present invention.
Detailed Description
The multi-project and multi-platform adaptive chip design FPGA prototype verification automation platform can couple a plurality of projects with a plurality of FPGA prototype verification platform environments. The software operating environment and the hardware environment of the fixed FPGA platform can be commonly used in a plurality of projects, and only specific configuration parameters related to the projects need to be modified. When switching chip design items on a designated FPGA platform, the software operating environment of the platform does not need to be modified on a large scale, and only the chip design items and verification configuration options need to be designated. FPGA verification developers can perform FPGA prototype verification on a plurality of projects and on the basis of a plurality of platforms only by maintaining one verification version management library, so that complex switching between the project library and the verification environment library is avoided. Continuous integration can automatically build a verification flow and test before chip design codes are integrated to a backbone, and helps designers to find and correct problems as soon as possible. The continuous integration tool is efficiently combined with the version management system, the FPGA prototype verification process can be automatically constructed and operated, designers can be helped to quickly find errors, branches are prevented from being greatly separated from the backbone, and code version management and code quality assurance based on the version management system are facilitated. In order to accelerate the iteration cycle and prototype verification efficiency of chip design codes, the design iteration version needs to be automatically managed and prototype verified by means of continuous integration, so that the chip design problem can be found as soon as possible, and excessive efforts of developers are avoided. Therefore, based on the problems existing in the traditional prototype verification process of chip design, the invention provides a multi-project and multi-platform self-adaptive chip design FPGA prototype verification automation platform, which supports verification developers to flexibly switch between a plurality of chip design projects and a plurality of verification platforms, and can quickly complete the FPGA prototype verification automation process of a specified project on the specified platform only by carrying out a small amount of configuration.
The present embodiment is described by taking a common version management system Git and a persistent integration tool Git-CI as examples. The method is also suitable for other version management systems and continuous integration tools, such as SVN, Jenkins and the like.
As shown in fig. 2, the steps of the multi-project and multi-platform adaptive chip design FPGA prototype verification method of this embodiment include:
1) enabling a continuous integration tool Git-CI at a management end of a Git warehouse of a test platform after the Git warehouse receives a design code of a current design version of a chip submitted by a chip developer, and constructing a continuous integration automation process configuration script.
2) The method comprises the steps that a platform self-adaptive configuration script auto _ cfg.sh is constructed, and the platform self-adaptive configuration script auto _ cfg.sh is used for generating a file list and a verification operation parameter file, wherein the file list and the verification operation parameter file are needed by the operation of a corresponding project library and a platform environment library according to an input project code and a test platform code;
3) determining the Project code number (e.g., Project1, etc.) of the chip design currently to be tested, the Platform code number (e.g., Platform _ A, etc.) for using the test;
4) the platform self-adaptive configuration script auto _ cfg.sh generates a file list required by the operation of the corresponding project library and the platform environment library and a verification operation parameter file according to the determined project code of the chip design and the platform code used for testing, and submits the file list to a Git warehouse of the corresponding testing platform;
5) a Git warehouse of each test platform detects a corresponding file submitting request, and if a file list required by the operation of a submitted platform environment library and a verification operation parameter file are detected, a Git-CI continuous integration tool is triggered to configure a script according to a continuous integration automation process, and a specified client runner (client runner) is started through gitlab-ci.yml configuration to start to operate a construction task;
6) the client runner executes tasks to respectively carry out compiling simulation, synthesis, implementation and test processes, and sends a return value to the continuous integration tool Git-CI through the implementation process after the implementation process;
7) after the continuous integration tool Git-CI detects that the return value of the implementation process is correct, the client operator calls download software and a network interface, and downloads the implemented design file and the test mirror image to the FPGA board to automatically start testing;
8) and the continuous integration tool Git-CI detects the testing progress, automatically analyzes the testing result after the testing is finished, generates a testing report of the current design version, and uploads the testing report to the Git warehouse through the accessory.
The platform structure of the multi-project and multi-platform adaptive chip design FPGA prototype verification method of this embodiment is shown in fig. 3, and the platform includes a chip design project based on a version management system Git, a persistent integration tool Git-CI and a persistent integration automation process configuration script Git-ci.yml, a platform adaptive configuration script auto _ cfg.sh, and software environments and hardware platforms of FPGA prototype verification platforms of different configurations. Through the platform self-adaptive configuration script, after a chip project to be verified and a corresponding FPGA verification platform are selected, a file list and a verification operation parameter file are correspondingly generated, the configured chip project is submitted to a platform library, an automatic flow called by a platform library continuous integration tool Git-CI is triggered, the platform is enabled to automatically complete the flow of compiling simulation, synthesis, realization, testing, analysis of a testing result and submission of a testing report of a chip design code, and the working efficiency of simultaneously performing FPGA prototype verification on multiple projects based on multiple platforms is improved.
In this embodiment, when the item code of the chip design to be currently tested and the platform code of the test are determined in step 3), the item code of the chip design to be currently tested and the platform code of the test are determined in one of the following four ways:
the first method is as follows: the project code of a single chip design and the platform code of a single use test; for example, if the chip tester specifies that the Project code of the chip design to be tested is Project1, and the Platform code for testing is Platform _ a, the Platform adaptive configuration script auto _ cfg.sh is run, the Project code of the chip design is Project1, and the Platform code of the testing is Platform _ a, the script will generate a file list of the Project code 1 and a verification run parameter file required by the Platform _ a, and submit the file to the Git warehouse of the Platform _ a. The Platform _ A testing Platform library enables continuous integration, and after a submitted file list and a verification operation parameter file are detected, Git-CI is triggered to start a specified client operator according to the configuration of gitlab-ci.yml, and a construction task starts to operate. When the continuous integration automation process configuration script is configured, the Platform library can automatically call the file and environment configuration of the Project1 according to the settings of the file list and the verification operation parameter file after the Platform library detects that the file list and the verification operation parameter file are submitted through configuration enabling, and the Git-CI automatically triggers and starts the continuous integration.
The second method comprises the following steps: the project code of a single chip design and the platform codes of a plurality of use tests;
the third method comprises the following steps: the project code of a plurality of chip designs and the platform code of a single use test;
the method is as follows: the product code of a plurality of chip designs and the platform code of a plurality of use tests.
On the basis of the first mode, when different projects are subjected to prototype verification, the platform self-adaptive configuration script auto _ cfg.sh is modified according to the verification requirements of different chip design projects, matched script configuration is added according to different projects, and a file list of test projects and verification operation parameter files suitable for different platforms are automatically generated. And submitting the file list and the verification operation parameter file to a corresponding test platform library according to requirements. For example, the third mode can realize the verification that a plurality of chip design projects adopt a single test platform, the fourth mode can realize the verification that a plurality of chip design projects adopt a plurality of test platforms, and each submission triggers the continuous execution of the steps 5) to 8).
On the basis of the verification aiming at the single project version, when the same project has a plurality of different versions for iterative verification, file lists of the different versions of the project and verification operation parameter files suitable for different platforms can be generated by configuring a platform self-adaptive configuration script auto _ cfg. Each submission triggers a continuous execution, in which case parallel validation processes for multiple versions of the same item are guaranteed. Therefore, step 4) of this embodiment further includes a platform adaptive configuration script auto _ cfg.sh, for a plurality of chip design versions corresponding to the item code of the chip design (different versions are represented by α, β, and γ in fig. 3), generating a file list and a verification operation parameter file required for the operation of the corresponding item library and the platform environment library according to the determined item code of the chip design and the platform code used for the test, respectively, submitting the file list and the verification operation parameter file to the Git warehouse of the corresponding test platform for different chip design versions, and executing steps 5) to 8 once when submitting one chip design version to the Git warehouse of the corresponding test platform. Therefore, the multi-project and multi-platform adaptive chip design FPGA prototype verification method of the embodiment has strong platform portability and does not need debugging, and for verification of different chip design projects or verification of different iteration versions of the same project, only the platform adaptive configuration script auto _ cfg.sh needs to be modified independently, the configuration script matching the project is added, the file list matching the chip design project and the verification operation parameter files suitable for different platforms are automatically generated, and the FPGA prototype verification of the project can be automatically completed. As shown in fig. 3, the Platform adaptive configuration script auto _ cfg.sh may invoke the Platform _ a, the Platform _ B, and the Platform _ C to perform simulation, synthesis, and implementation processes as needed. Further, any test platform may be applied to any one of Project1 to Project, and may be applied to any one of the versions of Project1 to Project (different versions are denoted by α, β, and γ in the drawing) as necessary.
In this embodiment, the step 6) of performing, by the client runner, compilation simulation, synthesis, implementation and test processes on the client runner execution task respectively specifically means that the client runner execution task calls simulation software and a synthesis tool respectively, and the implementation tool performs compilation simulation, synthesis, implementation and test processes.
In this embodiment, step 8) further includes the step of providing the test report of the design version to the developer and/or manager by the persistent integration tool Git-CI, so that the chip developer can analyze the test report to further optimize the chip design.
In addition, the present embodiment further provides a multi-project and multi-platform adaptive chip design FPGA prototype verification system, which includes a computer device programmed or configured to independently or cooperatively perform the steps of the aforementioned multi-project and multi-platform adaptive chip design FPGA prototype verification method.
In addition, the embodiment further provides a multi-project and multi-platform adaptive chip design FPGA prototype verification system, which includes a computer device, where a memory of the computer device stores a computer program programmed or configured to independently or cooperatively execute the multi-project and multi-platform adaptive chip design FPGA prototype verification method.
In addition, the present embodiment also provides a computer readable storage medium, which stores thereon a computer program programmed or configured to execute the aforementioned multi-project and multi-platform adaptive chip design FPGA prototype verification method independently or cooperatively.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein. The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.
Claims (8)
1. A multi-project and multi-platform self-adaptive chip design FPGA prototype verification method is characterized by comprising the following steps:
1) after the version management warehouse receives the design codes of the current design version of the chip submitted by a chip developer, a continuous integration tool is enabled at a test platform version management end, and a continuous integration automation process configuration script is constructed;
2) constructing a platform self-adaptive configuration script, wherein the platform self-adaptive configuration script is used for generating a file list required by the operation of a corresponding project library and a platform environment library and a verification operation parameter file according to an input project code and a test platform code;
3) determining the project code of the chip design to be tested and the platform code of the use test;
4) the platform self-adaptive configuration script generates a file list required by the operation of the corresponding project library and the platform environment library and a verification operation parameter file according to the determined project code of the chip design and the platform code used for testing, and submits the file list to a version management warehouse of the corresponding testing platform;
5) the version management warehouse of each test platform detects a corresponding file submission request, and if a submitted file list required by the running of the platform environment library and a verification running parameter file are detected, a continuous integration tool is triggered to start a specified client runner according to the configuration of a continuous integration automation process configuration script, and a construction task starts to run;
6) the client runner executes tasks to respectively carry out compiling simulation, synthesis, implementation and test processes, and sends a return value to the continuous integration tool through the implementation process after the implementation process;
7) after the continuous integration tool detects that the return value of the implementation process is correct, the client-side operator calls download software and a network interface, and downloads the implemented design file and the test mirror image to the FPGA board to automatically start testing;
8) and the continuous integration tool detects the test progress, automatically analyzes the test result after the test is finished, generates a test report of the current design version, and uploads the test report to the version management warehouse through the accessory.
2. The multi-item and multi-platform adaptive chip design FPGA prototype verification method according to claim 1, wherein when determining the item code of the chip design to be tested currently and using the platform code for testing in step 3), the determined item code of the chip design to be tested currently and the platform code for using the testing are one of the following four ways:
the first method is as follows: the project code of a single chip design and the platform code of a single use test;
the second method comprises the following steps: the project code of a single chip design and the platform codes of a plurality of use tests;
the third method comprises the following steps: the project code of a plurality of chip designs and the platform code of a single use test;
the method is as follows: the product code of a plurality of chip designs and the platform code of a plurality of use tests.
3. The multi-project and multi-platform adaptive FPGA prototype verification method for chip design according to claim 1, further comprising the steps of, in step 4), generating a file list and a verification operation parameter file required by the operation of the corresponding project library and platform environment library according to the determined project code of the chip design and the platform code used for testing, respectively, for a plurality of chip design versions corresponding to the project code of the chip design by the platform adaptive configuration script, and submitting different chip design versions to the version management warehouse of the corresponding test platform, and executing one step 5) -step 8 if one chip design version is submitted to the version management warehouse of the corresponding test platform.
4. The multi-project and multi-platform adaptive chip design FPGA prototype verification method according to claim 1, wherein the step 6) of performing the compiling simulation, the synthesis, the implementation, and the test processes respectively by the client runner execution task specifically means that the client runner execution task calls the simulation software, the synthesis tool, and the implementation tool respectively to perform the compiling simulation, the synthesis, the implementation, and the test processes.
5. The multi-project and multi-platform adaptive chip design FPGA prototype verification method according to claim 1, wherein the step 8) further comprises the step of providing the test report of the design version to a developer and/or a manager by the persistent integration tool, so that the chip developer can analyze the test report to further optimize the chip design.
6. A multi-project and multi-platform adaptive chip design FPGA prototype verification system comprising computer equipment, characterized in that the computer equipment is programmed or configured to independently or cooperatively perform the steps of the multi-project and multi-platform adaptive chip design FPGA prototype verification method according to any one of claims 1 to 5.
7. A multi-project and multi-platform adaptive chip design FPGA prototype verification system comprising a computer device, wherein a memory of the computer device has stored thereon a computer program programmed or configured to independently or cooperatively perform the multi-project and multi-platform adaptive chip design FPGA prototype verification method of any one of claims 1-5.
8. A computer-readable storage medium having stored thereon a computer program programmed or configured to perform, independently or in cooperation with the method for multi-project and multi-platform adaptive chip design FPGA prototype verification according to any one of claims 1-5.
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| US8356272B2 (en) * | 2011-05-12 | 2013-01-15 | S2C Inc. | Logic verification module apparatus to serve as a hyper prototype for debugging an electronic design that exceeds the capacity of a single FPGA |
| EP3264271B1 (en) * | 2012-02-07 | 2020-09-09 | Mts Systems Corporation | Mobile or cloud communication platform for test system applications, mobile application tool and graphical user interface |
| TWI465901B (en) * | 2012-10-23 | 2014-12-21 | Taiwan Memory Qualification Ct Corp | Method and system for verification of computerized systems for cloud testing and remote monitoring of integrated circuit devices |
| CN109101680B (en) * | 2018-06-26 | 2022-11-25 | 飞腾信息技术有限公司 | FPGA prototype automatic verification method and system based on GitLab-CI |
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