CN111384160B - Manufacturing method of field effect transistor, field effect transistor and grid structure - Google Patents
Manufacturing method of field effect transistor, field effect transistor and grid structure Download PDFInfo
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- CN111384160B CN111384160B CN201811643910.6A CN201811643910A CN111384160B CN 111384160 B CN111384160 B CN 111384160B CN 201811643910 A CN201811643910 A CN 201811643910A CN 111384160 B CN111384160 B CN 111384160B
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- 230000005669 field effect Effects 0.000 title claims abstract description 73
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 51
- 238000005530 etching Methods 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 239000010410 layer Substances 0.000 claims description 173
- 238000000034 method Methods 0.000 claims description 35
- 239000002184 metal Substances 0.000 claims description 25
- 239000011229 interlayer Substances 0.000 claims description 13
- 230000004888 barrier function Effects 0.000 claims description 11
- 238000001039 wet etching Methods 0.000 claims description 11
- 238000009792 diffusion process Methods 0.000 claims description 10
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 230000006872 improvement Effects 0.000 abstract description 7
- 239000000463 material Substances 0.000 description 21
- 230000008569 process Effects 0.000 description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 229910010038 TiAl Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 241001391944 Commicarpus scandens Species 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract
The invention provides a manufacturing method of a field effect transistor, the field effect transistor and a grid structure, which increase the channel length so as to realize the further improvement of the control capability of the grid to the channel. The manufacturing method comprises the following steps: providing a semiconductor substrate, wherein at least one part of the surface of the semiconductor substrate is configured as a channel region of a field effect transistor, a pseudo gate dielectric layer is covered on the channel region, and side walls which are oppositely arranged are also arranged on the pseudo gate dielectric layers at two sides of the channel region; etching the pseudo gate dielectric layer to enable the pseudo gate dielectric layer to be recessed into the inner side wall of the side wall along the horizontal direction; and forming a grid structure covering the pseudo grid dielectric layer and the inner side wall of the side wall on the channel region.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing and processing, and more particularly, to a method for manufacturing a field effect transistor, and a gate structure.
Background
Currently, metal gate processes are widely used in semiconductor devices to obtain an ideal threshold voltage, good channel control capability, and improved device performance. However, as the feature size (CD, critical Dimension) of devices further decreases, the structure of conventional MOS field effect transistors has failed to meet the device performance requirements even with metal gate processes, and multi-gate devices have received much attention as an alternative to conventional devices.
Therefore, how to further improve the channel control capability of the field effect transistor is a problem that needs to be solved in the industry.
Disclosure of Invention
The invention solves the technical problem of providing a manufacturing method of a field effect transistor, the field effect transistor and a grid structure, and the channel length is increased so as to further improve the control capability of the grid to the channel.
In order to solve the above problems, the present invention provides a method for manufacturing a field effect transistor, including:
providing a semiconductor substrate, wherein at least one part of the surface of the semiconductor substrate is configured as a channel region of a field effect transistor, a pseudo gate dielectric layer is covered on the channel region, and side walls which are oppositely arranged are also arranged on the pseudo gate dielectric layers at two sides of the channel region;
etching the pseudo gate dielectric layer to enable the pseudo gate dielectric layer to be recessed into the inner side wall of the side wall along the horizontal direction;
and forming a grid structure covering the pseudo grid dielectric layer and the inner side wall of the side wall on the channel region.
In the technical scheme provided by the invention, after the channel region, the side wall and the pseudo gate dielectric layer are arranged on the semiconductor substrate, the pseudo gate dielectric layer is etched, so that the pseudo gate dielectric layer is recessed into the inner side wall of the side wall along the horizontal direction. Therefore, when the gate structure is formed later, the material of the gate structure is filled in the groove formed by the pseudo gate dielectric layer and the side wall, so that the bottom of the gate structure is provided with the protrusion extending to the inner side wall of the side wall along the horizontal direction. It follows that the channel length of the field effect transistor is increased, thus enabling a further improvement in the channel control capability of the gate over the prior art.
In a preferred embodiment of the present invention, the step of providing a semiconductor substrate includes: forming a pseudo gate dielectric layer on a semiconductor substrate; forming a dummy gate on the dummy gate dielectric layer, wherein the dummy gate covers the surface of the dummy gate dielectric layer; forming oppositely arranged side walls which are arranged on the pseudo gate dielectric layer and cover the two sides of the pseudo gate; and removing the dummy gate.
In the preferred technical scheme of the invention, before the step of etching the dummy gate dielectric layer to enable the dummy gate dielectric layer to be recessed into the inner side wall of the side wall, the method further comprises the following steps: and etching the side walls, and reducing the width of the side walls along the horizontal direction so as to increase the distance between the side walls at the two sides of the channel region. Therefore, the channel length of the transistor device can be conveniently adjusted in the process by changing the amount of the etched side wall so as to meet different performance requirements. And the reduction of the width of the side wall realizes the reduction of the grid-drain overlap capacitance, thereby further improving the alternating current performance of the semiconductor device.
Further, in the preferred technical solution of the present invention, the step of etching the sidewall is performed by a dry etching method and/or a wet etching method having anisotropy.
Further, in the preferred technical scheme of the present invention, the manufacturing method further comprises: forming an interlayer dielectric layer on a semiconductor substrate; flattening, namely grinding the interlayer dielectric layer and the top of the side wall to the same height; in the step of etching the side wall, the height of the side wall is reduced, so that the top of the side wall is lower than the interlayer dielectric layer; and forming a metal grid electrode covering the top of the side wall and the side wall of the interlayer dielectric layer higher than the side wall part.
Further, in the preferred technical scheme of the invention, before the step of etching the side wall, the side wall and the semiconductor substrate are covered to form a contact etching barrier layer.
Further, in the preferred technical solution of the present invention, before the step of etching the side wall and reducing the width of the side wall along the horizontal direction, the method further includes: and etching the pseudo gate dielectric layer by taking the side wall as a mask so as to expose the semiconductor substrate in the channel region.
Further, in the preferred technical scheme of the present invention, before the step of etching the dummy gate dielectric layer by using the sidewall as a mask, the method further includes: and forming an etching protective layer by using an atomic layer deposition method, wherein the etching protective layer covers the top of the pseudo gate dielectric layer and the inner side wall of the side wall. Therefore, the side wall can be protected, so that the situation that the side wall is partially too thin caused by etching of the pseudo gate dielectric layer is avoided.
In a preferred technical scheme of the invention, the step of forming the grid structure covering the pseudo-grid dielectric layer and the side wall inner side wall on the channel region comprises the following steps: forming a gate dielectric layer, wherein the gate dielectric layer covers the channel region, the pseudo gate dielectric layer and the inner side wall of the side wall; forming a work function adjusting layer on the gate dielectric layer; flattening the work function adjusting layer, and etching the work function adjusting layer to be lower than the top of the side wall through wet etching; forming a diffusion barrier layer covering the top of the work function adjusting layer and the inner side wall surface of the side wall; a metal gate is formed on the diffusion barrier.
In a preferred embodiment of the present invention, in the step of providing the semiconductor substrate, the channel region is also provided with shallow doped regions on both sides thereof.
In a preferred embodiment of the present invention, the field effect transistor is a surrounding gate field effect transistor, a fin field effect transistor or a planar field effect transistor.
In the preferred technical scheme of the invention, the field effect transistor is a field effect transistor of a chip core area, and provides a basis for improving the performance of the chip where the field effect transistor is located.
The present invention also provides a field effect transistor comprising:
a semiconductor substrate, at least a portion of the semiconductor substrate surface being configured as a channel region of a field effect transistor;
the dummy gate dielectric layer covers the channel region;
the side walls are oppositely arranged and are arranged on the pseudo gate dielectric layers at two sides of the channel region;
the grid structure is arranged on the channel region and covers the pseudo-grid dielectric layer and the inner side wall of the side wall; the dummy gate dielectric layer is recessed into the inner side wall of the side wall along the horizontal direction.
The invention also provides a grid structure, wherein the bottom of the grid structure is provided with a bulge extending to the inner side wall of the field effect transistor in the horizontal direction.
Drawings
Fig. 1 is a schematic cross-sectional structure of a field effect transistor;
fig. 2 to 9 are schematic cross-sectional structures corresponding to respective steps of a method for manufacturing a field effect transistor according to the present invention.
Detailed Description
As described in the background art, how to further improve the channel control capability of the field effect transistor is a problem that needs to be solved in the industry.
The cause of the bottleneck in development of the improvement of the channel control capability in the prior art is now analyzed in conjunction with fig. 1.
As shown in fig. 1, a semiconductor substrate 10 is provided, on which a dummy gate dielectric layer 50 is disposed opposite to each other, and a channel region is disposed in a region below the dummy gate dielectric layer 50. The dummy gate dielectric layer 50 is provided with a side wall 20, a gate structure 30 is arranged in a groove formed by the side wall 20, the dummy gate dielectric layer 50 and the semiconductor substrate 10, and an interlayer dielectric layer 40 is arranged on the outer side of the side wall 20.
The gate structure 30 may be a metal gate structure for obtaining a desirable threshold voltage and a good channel control capability. However, under the market demand of further shrinking the size of the field effect transistor, it is difficult to realize further expansion of the channel length, and thus the channel length is very limited, and further improvement of the channel control capability cannot be realized.
In order to solve the problems, the invention provides a manufacturing method of a field effect transistor, which comprises the steps of after the channel region, the side wall and the pseudo gate dielectric layer are arranged on a semiconductor substrate, etching the pseudo gate dielectric layer to enable the pseudo gate dielectric layer to be recessed into the inner side wall of the side wall along the horizontal direction. Therefore, when the gate structure is formed later, the material of the gate structure is filled in the groove formed by the pseudo gate dielectric layer and the side wall, so that the bottom of the gate structure is provided with the protrusion extending to the inner side wall of the side wall along the horizontal direction. It follows that the channel length of the field effect transistor is increased, thus enabling a further improvement in the channel control capability of the gate over the prior art.
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be understood that the relative arrangement of parts and steps, numerical expressions and numerical values set forth in these embodiments should not be construed as limiting the scope of the present invention unless it is specifically stated otherwise. Furthermore, it should be understood that the dimensions of the various elements shown in the figures are not necessarily drawn to actual scale, e.g., the thickness or width of some layers may be exaggerated relative to other layers for ease of description.
The following description of the exemplary embodiment(s) is merely illustrative, and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but where applicable, should be considered part of the present specification.
It should be noted that like reference numerals and letters refer to like items in the following figures, and thus once an item is defined or illustrated in one figure, no further discussion thereof will be necessary in the description of the subsequent figures.
A preferred embodiment of the present invention provides a method for manufacturing a field effect transistor. The field effect transistor may be a surrounding gate field effect transistor, a fin field effect transistor or a planar field effect transistor, and the following method for manufacturing the field effect transistor is specifically described below:
referring to fig. 2, a semiconductor substrate 11 is provided, at least a portion of the surface of the semiconductor substrate 11 is configured as a channel region 61 of a field effect transistor, the channel region 61 is covered with a dummy gate dielectric layer 51, and opposite side walls 21 are disposed on the dummy gate dielectric layers 51 on both sides of the channel region 61.
The semiconductor substrate 11 may be polysilicon as a process base for forming a semiconductor device. In one embodiment of the present invention, the semiconductor substrate 11 further includes other structures, such as: the structures of the metal plug, the metal connection layer, the shallow doped region oppositely disposed at both sides of the channel region, and the like are not particularly limited herein.
The side walls 21 serve as insulation for isolating the different structures in the device. In the embodiment of the invention, the side wall 21 is formed on the surface of the dummy gate dielectric layer 51, and the material of the side wall 21 is SiO 2 。
In this embodiment, the semiconductor substrate 11 is required to be obtained in the following manner: a dummy gate dielectric layer 51 is formed on the semiconductor substrate 11. A dummy gate is formed on the dummy gate dielectric layer 51, and covers the surface of the dummy gate dielectric layer. Then, opposite side walls 21 are formed, and the side walls 21 are arranged on the dummy gate dielectric layer 51 and cover the two sides of the dummy gate. Thus, after the dummy gate is removed, the structure shown in fig. 2 can be obtained.
The dummy gate may be a polysilicon gate or a germanium-silicon gate, and in particular, in the embodiment of the present invention, the dummy gate is a polysilicon gate.
Thereafter, the dummy gate dielectric layer 51 is etched, so that the dummy gate dielectric layer 51 is recessed into the inner sidewall of the sidewall 21 along the horizontal direction, as shown in fig. 3. In this embodiment, the etching of the dummy gate dielectric layer 51 may be performed by a wet etching method until the surface of the semiconductor substrate 11 is exposed, as shown in fig. 4. Then, an anisotropic dry etching method is adopted to perform the lateral etching of the dummy gate dielectric layer 51. In the wet etching or dry etching process, the reaction night and the reaction gas with high selectivity to the dummy gate dielectric layer 51 are adopted, and the morphology of the side wall 21 is hardly affected while the dummy gate dielectric layer 51 is etched.
As can be seen from fig. 3, the inner sidewall of the sidewall 21 is the groove sidewall of the groove formed by the dummy gate dielectric layer 51 and the sidewall 21. The recess is used for the arrangement of the gate structure, so that the dummy gate dielectric layer 51 is recessed into the inner sidewall of the sidewall 21 in the horizontal direction, which not only increases the channel length, but also expands the arrangement space of the gate structure.
In another embodiment of the present invention, after the wet etching is performed on the dummy gate dielectric layer 51 to expose the surface of the semiconductor substrate 11, the side walls 21 are further etched to reduce the width of the side walls 21, so as to increase the distance between the side walls 21 on both sides of the channel region 61, so that the performance of the field effect transistor is further improved, as shown in fig. 5.
Thereafter, wet etching is performed on the dummy gate dielectric layer 51, so that the dummy gate dielectric layer 51 is recessed into the inner sidewall of the sidewall 21 along the horizontal direction, as shown in fig. 6. In this way, an increase in the channel length is realized again in the longitudinal direction, enabling further improvement in the channel control capability of the field effect transistor. And, by changing the amount of the etched side wall 21, the channel length of the transistor device can be conveniently adjusted in the process to cope with different performance requirements.
In this embodiment, when wet etching of the dummy gate dielectric layer 51 is performed to recess the dummy gate dielectric layer 51 into the inner sidewall of the sidewall 21 along the horizontal direction, the dummy gate dielectric layer 51 is etched with the sidewall 21 as a mask until the semiconductor substrate in the channel region is exposed.
In another embodiment of the present invention, an atomic layer deposition method is further used to form an etching protection layer, where the etching protection layer covers the top of the dummy gate dielectric layer 51 and the inner sidewall of the sidewall 21, so as to protect the sidewall 21 when the sidewall 21 is used as a mask to etch the dummy gate dielectric layer 51, and avoid that the sidewall 21 is slowly etched when the dummy gate dielectric layer 51 is etched, and the effect of the field effect transistor is affected by the local excessive thinning of the sidewall 21.
That is, after the etching protection layer is formed, when the dummy gate dielectric layer 51 is etched, the etching protection layer is etched first, and then the dummy gate dielectric layer 51 is etched. Since the etching protection layer covers the top of the dummy gate dielectric layer 51 and the inner sidewall of the sidewall 21, in this embodiment, in the step of etching the dummy gate dielectric layer 51, the etching protection layer and the dummy gate dielectric layer 51 are sequentially etched until the semiconductor substrate is exposed. In this case, as the etching protection layer will have residues in the etching process, as shown in fig. 7, the small sharp corner 71 higher than the portion of the dummy gate dielectric layer 51 is the etching residue of the etching protection layer. In this way, when the dummy gate dielectric layer 51 is etched after the subsequent etching of the side wall 21, not only the small sharp corner 71 can be etched and removed, but also the dummy gate dielectric layer 51 can be recessed into the inner side wall of the side wall 21.
It should be noted that the width of the side wall 21 is reduced, so that the gate-drain overlap capacitance is reduced, and the ac performance of the semiconductor device is further improved.
Finally, the gate structure is set. Referring to fig. 8 or 9, a gate structure 31 is formed on the channel region 61 to cover the dummy gate dielectric layer 51 and the inner sidewall of the sidewall 21.
The gate structure 31 may be a polysilicon gate or a high-k metal gate. In this embodiment, the gate structure 31 is a high-k metal gate, so that the semiconductor device can obtain an ideal threshold voltage and better channel control capability. That is, in the process of setting the gate structure, a gate dielectric layer is formed first, the gate dielectric layer is a high-k gate dielectric layer, and the gate dielectric layer covers the channel region, the dummy gate dielectric layer and the inner side walls of the side walls. Then, a work function adjusting layer is formed on the gate dielectric layer, the work function adjusting layer is flattened, and the work function adjusting layer is etched to be lower than the top of the side wall 21 through wet etching. Finally, a diffusion barrier layer is formed to cover the top of the work function adjusting layer and the inner side wall surface of the side wall 21, and a metal gate is formed on the diffusion barrier layer.
The high-k gate dielectric layer has high insulating property, can generate higher field effect, reduces the electric leakage quantity and assists the metal gate to better control the semiconductor device. The material for forming the high-k gate dielectric layer comprises the following components: hfO (HfO) 2 、ZrO 2 、Y2O 3 、TaO 2 And the like. Specifically, in the embodiment of the present invention, the material of the high-k gate dielectric layer is HfO 2 。
The material forming the work function material layer includes: tiN, taN, tiAl, etc., without specific limitation herein. Specifically, in the embodiment of the present invention, the work function material layer is made of TiAl.
Specifically, in the embodiment of the invention, the material SiO of the diffusion barrier layer 2 。
The material forming the metal gate includes: w and/or Al. Specifically, in the embodiment of the present invention, the material of the metal gate is W.
Thus, the grid structure is formed, and the process of replacing the pseudo grid by the grid structure is realized. In addition, in the embodiment, the channel length is increased, and the arrangement space of the gate structure is expanded, so that the control capability of the gate of the field effect transistor on the channel is further improved, and the capacitance value of the field effect transistor is higher.
Note that in the embodiment of the present invention, after the gate structure is formed, an interlayer dielectric layer 41 is also formed on the semiconductor substrate 11. Then, a planarization (e.g., chemical Mechanical Planarization (CMP)) process is performed to polish the top of the interlayer dielectric 41 and the sidewall 21 to the same height.
In another embodiment of the present invention, the height of the side wall 21 may be reduced, so that the top of the side wall 21 is lower than the interlayer dielectric layer 41, and a metal gate covering the top of the side wall 21 and the side wall of the interlayer dielectric layer 41 higher than the side wall 21 is formed, so as to expand the arrangement space of the metal gate as much as possible, and prompt the performance of the field effect transistor.
The inventor finds that the gate structure is not easy to break down due to lower voltage of the chip core region, so that the field effect transistor provided by the embodiment can be mainly applied to the chip core region and can realize improvement of chip performance.
The preferred embodiment of the present invention also provides a field effect transistor, as shown in fig. 8 or 9, comprising: the semiconductor substrate 11, the dummy gate dielectric layer 51, the oppositely arranged side wall 21 and the gate structure 31.
In the present embodiment, at least a part of the surface of the semiconductor substrate 11 is configured as a channel region 61 of a field effect transistor. The dummy gate dielectric layer 51 covers the channel region 61, and the opposite side walls 21 are arranged on the dummy gate dielectric layer 51 at two sides of the channel region 61. The gate structure 31 is disposed on the channel region 61 and covers the dummy gate dielectric layer 51 and the inner sidewall of the sidewall 21. Wherein the dummy gate dielectric layer 51 is recessed into the inner sidewall of the sidewall 21 in the horizontal direction.
In this embodiment, the field effect transistor may be a surrounding gate field effect transistor, a fin field effect transistor, or a planar field effect transistor. The semiconductor substrate 11 may be polysilicon as a material which is a process basis for forming a semiconductor device. In one embodiment of the present invention, the semiconductor substrate 11 further includes other structures, such as: the structures of the metal plug, the metal connection layer, the shallow doped region oppositely disposed at both sides of the channel region, and the like are not particularly limited herein.
The side walls 21 serve as insulation for isolating the different structures in the device. In the embodiment of the invention, the side wall 21 is formed on the surface of the dummy gate dielectric layer 51, and the material of the side wall 21 is SiO 2 。
The gate structure 31 may be a polysilicon gate or a high-k metal gate. In this embodiment, the gate structure 31 is a high-k metal gate, so that the semiconductor device can obtain an ideal threshold voltage and better channel control capability. That is, in the process of setting the gate structure, a gate dielectric layer is formed first, the gate dielectric layer is a high-k gate dielectric layer, and the gate dielectric layer covers the channel region, the dummy gate dielectric layer and the inner side walls of the side walls. Then, a work function adjusting layer is formed on the gate dielectric layer, the work function adjusting layer is flattened, and the work function adjusting layer is etched to be lower than the top of the side wall 21 through wet etching. Finally, a diffusion barrier layer is formed to cover the top of the work function adjusting layer and the inner side wall surface of the side wall 21, and a metal gate is formed on the diffusion barrier layer.
The high-k gate dielectric layer has high insulating property, can generate higher field effect, reduces the electric leakage quantity and assists the metal gate to better control the semiconductor device. The material for forming the high-k gate dielectric layer comprises the following components: hfO (HfO) 2 、ZrO 2 、Y2O 3 、TaO 2 And the like. Specifically, in the embodiment of the present invention, the material of the high-k gate dielectric layer is HfO 2 。
The material forming the work function material layer includes: tiN, taN, tiAl, etc., without specific limitation herein. Specifically, in the embodiment of the present invention, the work function material layer is made of TiAl.
Specifically, in the embodiment of the invention, the material SiO of the diffusion barrier layer 2 。
The material forming the metal gate includes: w and/or Al. Specifically, in the embodiment of the present invention, the material of the metal gate is W.
It can be seen that the process of replacing the dummy gate with the gate structure is implemented in this embodiment. In addition, in the embodiment, the channel length is increased, and the arrangement space of the gate structure is expanded, so that the control capability of the gate of the field effect transistor on the channel is further improved, and the capacitance value of the field effect transistor is higher.
The preferred embodiment of the invention also provides a grid structure, wherein the bottom of the grid structure is provided with a bulge which extends to the inner side wall of the field effect transistor in the horizontal direction. The gate structure in the present embodiment can be applied to the above-described embodiments.
Thus far, the technical solution of the present invention has been described in connection with the accompanying drawings, but it is easily understood by those skilled in the art that the scope of protection of the present invention is not limited to these specific embodiments. Equivalent modifications and substitutions for related technical features may be made by those skilled in the art without departing from the principles of the present invention, and such modifications and substitutions will fall within the scope of the present invention.
Claims (13)
1. A method of fabricating a field effect transistor, comprising:
providing a semiconductor substrate, wherein at least a part of the surface of the semiconductor substrate is configured as a channel region of the field effect transistor, a pseudo gate dielectric layer is covered on the channel region, and side walls which are oppositely arranged are also arranged on the pseudo gate dielectric layers at two sides of the channel region;
etching the pseudo gate dielectric layer to enable the pseudo gate dielectric layer to be recessed into the inner side wall of the side wall along the horizontal direction;
and forming a grid structure covering the pseudo grid dielectric layer and the inner side wall of the side wall on the channel region.
2. The method of manufacturing a field effect transistor according to claim 1, wherein in the step of providing a semiconductor substrate, comprising:
forming a pseudo gate dielectric layer on a semiconductor substrate;
forming a dummy gate on the dummy gate dielectric layer, wherein the dummy gate covers the surface of the dummy gate dielectric layer;
forming oppositely arranged side walls which are arranged on the pseudo gate dielectric layer and cover the two sides of the pseudo gate;
and removing the dummy gate.
3. The method of claim 1, wherein before the step of etching the dummy gate dielectric layer to recess the dummy gate dielectric layer into the inner sidewall of the sidewall, further comprising:
and etching the side walls, and reducing the width of the side walls along the horizontal direction so as to increase the distance between the side walls at the two sides of the channel region.
4. A method of manufacturing a field effect transistor according to claim 3, wherein the step of etching the sidewall is performed using a dry and/or wet etching method having anisotropy.
5. The method of manufacturing a field effect transistor according to claim 3, further comprising:
forming an interlayer dielectric layer on the semiconductor substrate;
flattening, namely grinding the interlayer dielectric layer and the top of the side wall to the same height;
in the step of etching the side wall, the height of the side wall is reduced, so that the top of the side wall is lower than the interlayer dielectric layer;
and forming a metal grid electrode which covers the top of the side wall and the side wall of the interlayer dielectric layer higher than the side wall part.
6. The method of claim 3, wherein a contact etch stop layer is formed overlying the sidewall and the semiconductor substrate prior to the step of etching the sidewall.
7. The method of manufacturing a field effect transistor according to claim 3, further comprising, before the step of etching the sidewall to reduce the width thereof in the horizontal direction:
and etching the pseudo gate dielectric layer by taking the side wall as a mask so as to expose the semiconductor substrate of the channel region.
8. The method of manufacturing a field effect transistor according to claim 7, wherein before the step of etching the dummy gate dielectric layer using the sidewall as a mask, further comprising:
and forming an etching protection layer by using an atomic layer deposition method, wherein the etching protection layer covers the top of the pseudo gate dielectric layer and the inner side wall of the side wall.
9. The method of manufacturing a field effect transistor according to any one of claims 1 to 8, wherein the step of forming a gate structure on the channel region covering the dummy gate dielectric layer and the sidewall of the sidewall comprises:
forming a gate dielectric layer, wherein the gate dielectric layer covers the channel region, the dummy gate dielectric layer and the inner side wall of the side wall;
forming a work function adjusting layer on the gate dielectric layer;
flattening the work function adjusting layer, and etching the work function adjusting layer to be lower than the top of the side wall through wet etching;
forming a diffusion barrier layer covering the top of the work function adjusting layer and the inner side wall surface of the side wall;
and forming a metal gate on the diffusion barrier layer.
10. The method of manufacturing a field effect transistor according to any one of claims 1 to 8, wherein in the step of providing a semiconductor substrate, shallow doped regions are also oppositely provided on both sides of the channel region.
11. The method of any one of claims 1-8, wherein the field effect transistor is a surrounding gate field effect transistor, a fin field effect transistor, or a planar field effect transistor.
12. The method of any one of claims 1-8, wherein the field effect transistor is a chip core field effect transistor.
13. A field effect transistor, comprising:
a semiconductor substrate, at least a portion of the semiconductor substrate surface being configured as a channel region of the field effect transistor;
the pseudo gate dielectric layer covers the channel region;
the side walls are oppositely arranged and are arranged on the pseudo gate dielectric layers at two sides of the channel region;
the grid structure is arranged on the channel region and covers the pseudo-grid dielectric layer and the inner side wall of the side wall;
and the dummy gate dielectric layer is recessed into the inner side wall of the side wall along the horizontal direction.
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| CN1149198A (en) * | 1995-10-24 | 1997-05-07 | 台湾茂矽电子股份有限公司 | Method for manufacturing MOS transistor with low dosed drain and upside-down T shape grid and its structure |
| CN104183473A (en) * | 2013-05-21 | 2014-12-03 | 中芯国际集成电路制造(上海)有限公司 | Metal gate transistor forming method and semiconductor device |
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| CN1149198A (en) * | 1995-10-24 | 1997-05-07 | 台湾茂矽电子股份有限公司 | Method for manufacturing MOS transistor with low dosed drain and upside-down T shape grid and its structure |
| CN104183473A (en) * | 2013-05-21 | 2014-12-03 | 中芯国际集成电路制造(上海)有限公司 | Metal gate transistor forming method and semiconductor device |
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