CN111384148A - Semiconductor component and method of manufacturing the same - Google Patents

Abstract

The invention discloses a semiconductor component and a manufacturing method thereof. The manufacturing method of the semiconductor component includes at least the following steps. An epitaxial layer is formed on a substrate, and the epitaxial layer is divided into at least one component area and an electrostatic protection area. A first base area is formed in the component area, and a second base area is formed in the electrostatic protection area. A stacked structure is formed on the surface of the epitaxial layer in the electrostatic protection region. The stacked structure includes an insulating layer and a semiconductor layer on the insulating layer, wherein the semiconductor layer has a first heavily doped region, and then formed At least one second heavily doped region, both of which together form an electrostatic protection layer, wherein the electrostatic protection layer is located above the second base region, and the electrostatic protection layer completely overlaps within the range of the second base region.

Description

Semiconductor component and method of manufacturing the same

technical field

The present invention relates to a semiconductor component and its manufacturing method, in particular to a semiconductor component with an electrostatic protection layer and its manufacturing method.

Background technique

In the application field of semiconductor power components, the ability of semiconductor power components to protect against electrostatic discharge has become an important indicator. Some small-signal semiconductor power components have poor ESD protection capability due to their small chip size, and even cannot reach the minimum standard of ESD protection. Although some semiconductor power components have a large chip size and can have a large electrostatic discharge protection capability, they may need to be used in a harsh environment (such as: a dry environment with a relative humidity <65%, or an environment with more dust) Therefore, there are higher requirements for the electrostatic discharge protection capability of semiconductor power components.

Therefore, in the prior art, ESD protection structures are integrated into semiconductor power components to increase the withstand capability of the semiconductor power components against ESD. However, in the existing process, due to the limitation of process conditions and process window, the position of the ESD protection structure is easily shifted from the predetermined position. In addition, in the conventional semiconductor power device, the ESD protection structure directly connects the drift region and the base region, and an arc-shaped interface extending along the thickness direction of the epitaxial layer is formed between the drift region and the base region.

Therefore, when the semiconductor power device operates, the electric field strength at the arc interface between the drift region and the base region is strong, which causes the collapse phenomenon to occur frequently in the region near the arc interface, and reduces the withstand voltage of the semiconductor power device itself.

On the other hand, for the existing semiconductor power components, the breakdown voltage and on-resistance are more important parameters, wherein the on-resistance will affect the conduction loss of the semiconductor power component ( conducting loss). Currently, the industry tends to further reduce the on-resistance of semiconductor power components by increasing the doping concentration of the drift region. However, after integrating the electrostatic discharge protection structure, the existing semiconductor power components already have a relatively low withstand voltage, which is more difficult to meet the current industry trend.

SUMMARY OF THE INVENTION

One of the technical problems to be solved by the present invention is to overcome the problem of low withstand voltage of the semiconductor device with the electrostatic discharge protection structure.

In order to solve the above technical problems, one of the technical solutions adopted by the present invention is to provide a method for manufacturing a semiconductor device. The aforementioned manufacturing method includes the following steps. An epitaxial layer is formed on a substrate, and the epitaxial layer is divided into at least one component area and an electrostatic protection area. A first base region is formed in the component region and a second base region is formed in the electrostatic protection region. A stacked structure is formed on the surface of the epitaxial layer, the stacked structure is located in the electrostatic protection area, and includes an insulating layer and a semiconductor layer on the insulating layer, and the semiconductor layer has a first heavily doped region. At least one second heavily doped region is formed in the semiconductor layer, and the second heavily doped region and the first heavily doped region together form an electrostatic protection layer. The electrostatic protection layer is located above the second base region, and the electrostatic protection layer completely overlaps within the range of the second base region.

Another technical solution adopted by the present invention is to provide a semiconductor device, which is divided into a device region and an electrostatic protection region, and the semiconductor device includes an epitaxial layer, a gate structure and an electrostatic protection layer . The epitaxial layer includes a first base region located in the device region and a second base region located in the electrostatic protection region. The gate structure is arranged in the device region and connected to at least the first base region. The electrostatic protection layer is disposed on a surface of the epitaxial layer and is isolated from the epitaxial layer. The electrostatic protection layer is located above the second base region, and the electrostatic protection layer completely overlaps within the range of the second base region.

The beneficial effect of the present invention is that, in the semiconductor device and the manufacturing method thereof provided by the present invention, the semiconductor device with the electrostatic protection layer can be made by the technical means of "the electrostatic protection layer completely overlaps the second base region". Meet the electrostatic discharge protection standard, but also have a higher withstand voltage.

For further understanding of the features and technical content of the present invention, please refer to the following detailed description and accompanying drawings of the present invention. However, the accompanying drawings are only for reference and description, not for limiting the present invention.

Description of drawings

FIG. 1 is a flowchart illustrating a semiconductor device according to an embodiment of the present invention. 2A is a partial cross-sectional schematic diagram of a semiconductor device in a manufacturing process according to an embodiment of the present invention.

FIG. 2B is a partial cross-sectional schematic diagram of the semiconductor device in the manufacturing process according to the embodiment of the present invention.

FIG. 2C is a schematic partial cross-sectional view of the semiconductor device in the manufacturing process according to the embodiment of the present invention.

FIG. 2D is a schematic partial cross-sectional view of the semiconductor device in the manufacturing process according to the embodiment of the present invention.

FIG. 2E is a partial cross-sectional schematic diagram of the semiconductor device in the manufacturing process according to the embodiment of the present invention.

FIG. 2F is a partial cross-sectional schematic diagram of the semiconductor device in the manufacturing process according to the embodiment of the present invention.

2G is a partial cross-sectional schematic diagram of the semiconductor device in the manufacturing process according to the embodiment of the present invention.

3 is a schematic partial cross-sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a partial cross-sectional schematic diagram of a semiconductor device in a manufacturing process according to another embodiment of the present invention.

FIG. 5 is a partial cross-sectional schematic diagram of a semiconductor device in a manufacturing process according to another embodiment of the present invention.

6 is a schematic partial cross-sectional view of a semiconductor device according to an embodiment of the present invention.

Detailed ways

See Figure 1. FIG. 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Specifically, the present invention provides a method for manufacturing a semiconductor device with an electrostatic protection layer, which includes at least the following steps.

In step S100, an epitaxial layer is formed on a substrate, wherein the epitaxial layer is divided into at least one component area and an electrostatic protection area. In step S110, a first base area and a second base area are formed in the component area and the electrostatic protection area, respectively. In step S120, a stacked structure is formed on the surface of the epitaxial layer in the electrostatic protection region, the stacked structure includes an insulating layer and a semiconductor layer on the insulating layer, wherein the semiconductor layer has a first re-doping Miscellaneous area. In step S130, at least one second heavily doped region is formed in the semiconductor layer, and the second heavily doped region and the first heavily doped region together form an electrostatic protection layer. The electrostatic protection layer is located above the second base region, and the electrostatic protection layer completely overlaps the second base region.

The specific steps in the manufacturing method of the semiconductor component will be described in detail below. In this embodiment, a trench-type semiconductor power device is taken as an example to describe the manufacturing method of the embodiment of the present invention in detail.

Please refer to FIG. 2A , which shows a partial cross-sectional schematic diagram of a semiconductor device in a manufacturing process according to an embodiment of the present invention. An epitaxial layer 11 has been formed on the substrate 10 . The substrate 10 is, for example, a silicon substrate, which has a first-type conductivity impurity with a high doping concentration, and is used as a drain of a semiconductor power device.

The aforementioned first conductivity type impurities may be N-type or P-type conductivity impurities. Assuming that the substrate 10 is a silicon substrate, the N-type conductivity impurities are pentavalent element ions, such as phosphorus ions or arsenic ions, and the P-type conductivity impurities are trivalent element ions, such as boron ions, aluminum ions, or gallium ions.

If the channel-type power semiconductor device is an N-type power MOSFET, the substrate 10 is doped with N-type conductive impurities. On the other hand, if the channel-type power semiconductor device is a P-type channel-type power MOSFET, the substrate 10 is doped with P-type conductivity impurities.

The epitaxial layer 11 ″ is formed on the substrate 10 and has a low concentration of first-type conductivity impurities. Taking an NMOS transistor as an example, the substrate 10 is doped with a high concentration of N-type (N ⁺ ), and the epitaxial layer is 11" is a low concentration of N ^- type doping (N-). On the contrary, taking a PMOS transistor as an example, the substrate 10 is P-type doping with a high concentration (P ⁺ doping), and the epitaxial layer 11 ″ is P ^- doping with a low concentration.

In this embodiment, the epitaxial layer 11" has a surface 11s, and the epitaxial layer 11" is divided into a component region R1 and an electrostatic protection region R2. It should be noted that although FIG. 2A shows that the electrostatic protection area R2 is surrounded by the component area R1 , the present invention does not limit the arrangement positions of the electrostatic protection area R2 and the component area R1 . In another embodiment, the component region R1 may be located on one side of the electrostatic protection region R2. In yet another embodiment, the component region R1 may be surrounded by the electrostatic protection region R2. That is to say, the configuration positions and shapes of the electrostatic protection area R2 and the component area R1 can be changed according to actual needs, which is not limited in the present invention.

As shown in FIG. 2A , at least one gate structure 12 (a plurality of which are shown in FIG. 2A as an example) has been formed in the device region R1 , and the gate structure 12 includes a gate insulating layer 120 and a gate electrode 121 . In addition, the gate structure 12 may be a planar gate structure or a trench gate structure.

In this embodiment, the gate structure 12 is a trench gate structure. In the step of forming the gate structure 12 , a plurality of channels 11h in the device region R1 are firstly formed in the epitaxial layer 11 ″, and then a gate insulating layer 120 is sequentially formed in the channels 11h to connect with the gate 121 .

As shown in FIG. 2A , a base doping step 20 is performed on the epitaxial layer 11 ″ to form a first preliminary base doping region 111 ′ in the device region R1 and a second preliminary base doping region in the ESD protection region R2 District 112'.

2B, an initial insulating layer 13' and an undoped semiconductor layer 14P are sequentially formed on the surface 11s of the epitaxial layer 11". The initial insulating layer 13' covers the entire surface 11s of the epitaxial layer 11". The material of the initial insulating layer 13' can be selected from oxide or nitride, such as silicon oxide or silicon nitride.

In addition, the thickness of the initial insulating layer 13' is adjusted according to the magnitude of the gate-source bias (Vgs) of the semiconductor power device. When the gate-source voltage (Vgs) of the semiconductor power device is larger, the thickness of the initial insulating layer 13' is thicker.

The undoped semiconductor layer 14P is formed on the initial insulating layer 13' to be isolated from the epitaxial layer 11". The undoped semiconductor layer 14P may be an undoped polysilicon layer. After that, the undoped semiconductor layer 14P is subjected to A heavy doping step 30 .

Referring to FIG. 2C, a step of thermally immersing a body is performed to form a first body region 111 and a second body region 112 in the epitaxial layer 11'. On the other hand, in the step of thermally immersing the substrate, the first heavily doped region 140' is also formed in the undoped semiconductor layer 14P simultaneously to form an initial semiconductor layer 14".

In this embodiment, impurities with the same conductivity type are used in the heavy doping step 30 and the base doping step 20 . That is to say, the first heavily doped region 140', the first body region 111 and the second body region 112 all have the same conductivity type, but this is only an example and does not limit the present invention. In other embodiments, the first heavily doped region 140', the first base region 111 and the second base region 112 can also be subjected to different conductivity types by adding additional process steps to achieve doping results.

It should be noted that, in this embodiment, the step of forming the initial semiconductor layer 14 ″ is completed before the step of thermally entering the substrate. However, in other embodiments, the step of thermally entering the substrate may also be performed first to The first body region 111 and the second body region 112 are formed. After that, another thermal infiltration step is performed to form the initial semiconductor layer 14" having the first heavily doped region 140'.

In other embodiments, the first base region 111 and the second base region 112 may be formed in the epitaxial layer 11 ″ first, and then the gate structure 12 in the device region R1 may be formed.

As shown in FIG. 2C , the first base region 111 is located in the device region R1 of the epitaxial layer 11 ′ and surrounds the gate structure 12 . Other regions in the epitaxial layer 11' form the drift region 110' of the channel semiconductor device. The second base region 112 is located in the electrostatic protection region R2 and is connected to the initial insulating layer 13'.

Referring to FIG. 2D, a part of the initial insulating layer 13' and a part of the initial semiconductor layer 14" in the device region R1 are removed to form a stacked structure P1' in the electrostatic protection region R2.

Specifically, a photoresist layer PR can be formed on the initial semiconductor layer 14'' to define the position of the stacked structure P1', and then an etching step is performed to remove a part of the initial semiconductor layer 14'' and a part of the initial semiconductor layer 14'' located in the device region R1. insulating layer 13'. The other part of the initial semiconductor layer 14'' and the initial insulating layer 13' covered by the photoresist layer PR will remain to form the stacked structure P1' in the electrostatic protection region R2.

Accordingly, the stacked structure P1' includes a semiconductor layer 14' and an insulating layer 13 in the electrostatic protection region R2, and the semiconductor layer 14' has a first heavily doped region 140'. By forming the stacked structure P1' through the above steps, the positional displacement of the stacked structure P1' can be avoided, resulting in direct contact between the semiconductor layer 14' and the epitaxial layer 11'. In this embodiment, the lateral width of the semiconductor layer 14' is approximately the same as the lateral width of the insulating layer 13. Specifically, the difference between the width of the semiconductor layer 14' and the width of the insulating layer 13 is less than 0.5um.

Referring to FIG. 2E, at least one second heavily doped region 141 is further formed in the semiconductor layer 14', so that the at least one second heavily doped region 141 and the first heavily doped region 140 together form an electrostatic protection layer 14. The electrostatic protection layer 14 is disposed on the insulating layer 13 , and the electrostatic protection layer 14 and the insulating layer 13 together form an electrostatic protection stack P1 .

In detail, a mask pattern layer (not shown) may be pre-formed on the semiconductor layer 14' to define the position of the second heavily doped region 141. Afterwards, a second heavily doped region 141 can be formed in the semiconductor layer 14' by sequentially performing a doping step and a thermal sinking step.

The second heavily doped region 141 and the first heavily doped region 140 have opposite conductivity types, respectively. Therefore, a PN junction is formed at the interface between the second heavily doped region 141 and the first heavily doped region 140 .

In the embodiment of FIG. 2E , two second heavily doped regions 141 separated from each other are formed in the semiconductor layer 14 ′, and the first heavily doped region 140 is located between the two second heavily doped regions 141 , and A bipolar diode is formed, such as a PNP triode or an NPN triode.

In addition, in the step of forming the second heavily doped region 141, at least one first source region 113a (a plurality of which are shown in FIG. 2E) can be simultaneously formed in the device region R1. Accordingly, the first source region 113a and the second heavily doped region 141 have the same conductivity type.

It should be noted that the position of the second heavily doped region 141 can be adjusted by changing the shielding pattern layer to form different electrostatic protection layers 14 . Please refer to FIG. 4 , which shows a schematic cross-sectional view of a semiconductor device in a manufacturing process according to another embodiment of the present invention, and the steps of FIG. 2D can be continued.

In the embodiment of FIG. 4, only a second heavily doped region 141 is formed in the semiconductor layer 14' to form a PN junction diode. Therefore, as long as the effect of electrostatic discharge protection can be achieved, the electrostatic protection layer 14 can be a triode, a PN diode, or other components.

Please refer to FIG. 5 again, which shows a schematic cross-sectional view of a semiconductor device in a manufacturing process according to another embodiment of the present invention, and the steps of FIG. 2D can be continued. In the step of forming the second heavily doped region 141, at least one first source region 113a (a plurality of which are shown in FIG. 5) and at least one second source region can be formed in the device region R1 simultaneously in the device region R1 The pole regions 113b (two are shown in FIG. 5 ).

In the embodiment of FIG. 5 , the first source region 113 a is located above the first body region 111 and is connected to at least one gate structure 12 . In addition, the second base region 112 has an extension portion 112a, and the extension portion 112a is connected to the gate structure 12 closest to the electrostatic protection region R2. The second source region 113b is formed on the upper portion of the extension portion 112a, and is connected to the gate structure 12 closest to the ESD protection region R2.

It is worth noting that, through the above steps, the transistor structure can be formed in the element R1 and the electrostatic protection stack P1 can be formed in the electrostatic protection region R2. Accordingly, in the process steps of the embodiment of the present invention, the step of forming the electrostatic protection stack P1 can be integrated with the step of forming the transistor structure, thereby reducing the manufacturing cost.

Referring to FIGS. 2F , 2G and 3 , a redistribution circuit structure is formed, so that the transistor structure and the electrostatic protection stack P1 can be electrically connected to an external control circuit. In detail, as shown in FIG. 2F , an interlayer dielectric layer 15' is formed on the electrostatic protection layer 14 and the surface 11s of the epitaxial layer 11. Next, as shown in FIG. 2G , a plurality of contact windows 15h are formed in the interlayer dielectric layer 15, and a plurality of conductive structures 16 are formed in the plurality of contact windows 15h.

The conductive structure 16 includes a plurality of first conductive pillars 161 and a plurality of second conductive pillars 162 . Each of the first conductive pillars 161 is electrically connected to the corresponding first source region 113a through the corresponding contact window 15h. Each of the second conductive pillars 162 is electrically connected to the first heavily doped region 140 or the second heavily doped region 141 of the electrostatic protection layer 14 through the corresponding contact window 15h. In addition, the first heavily doped regions 140 may or may not be connected to the second conductive pillars 162, depending on the application requirements.

Referring to FIG. 3 , a partial cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention is shown. In this embodiment, a pad group 17 is further formed on the interlayer dielectric layer 15 . The pad set 17 includes a plurality of first pads 171 and a plurality of second pads 172 . The first pads 171 are electrically connected to the first source region 113 a and the second source region 113 b through the corresponding first conductive pillars 161 . The second pad 172 is electrically connected to the first heavily doped region 140 or the second heavily doped region 141 through the corresponding second conductive pillar 162 .

After that, a protective layer 18 is formed on the pad group 17 . The protective layer 18 has a plurality of openings, and each opening exposes a corresponding first pad 171 (or a second pad 172 ), so that the plurality of first pads 171 and the plurality of second pads 172 can be electrically connected to the external control circuit.

Accordingly, as shown in FIG. 3 , an embodiment of the present invention provides a semiconductor device M1 integrating the electrostatic protection layer 14 . The semiconductor component M1 is, for example, a channel type metal oxide field effect transistor, a laterally diffused metal oxide field effect transistor, or a planar metal oxide field effect transistor, or the like.

The semiconductor device M1 can be divided into a device region R1 and an electrostatic protection region R2. The area of the electrostatic protection area R2 can be adjusted according to the actual application requirements. If the semiconductor component M1 needs to meet higher electrostatic discharge protection specifications, that is, has a greater electrostatic discharge withstand capability, the area of the electrostatic protection area R2 will be larger.

The semiconductor device M1 includes a substrate 10 , an epitaxial layer 11 , a gate structure 12 and an electrostatic protection stack P1 . The epitaxial layer 11 is disposed on the substrate 10 and has a drift region 110 , a first body region 111 , a second body region 112 and a first source region 113 a. The drift region 110 is located on a side of the epitaxial layer 11 close to the substrate 10 , and extends from the device region R1 to the electrostatic protection region R2 .

The first base region 111 is located in the component region R1 and is located on a side away from the substrate 10 . That is, the first base region 111 is located above the drift region 110 . In addition, the first source region 113 a is located above the first body region 111 and is connected to the surface 11 s of the epitaxial layer 11 .

The second base region 112 is located in the electrostatic protection region R2 and is located on the side of the epitaxial layer 11 away from the substrate 10 , that is, located above the drift region 110 .

When the semiconductor device M1 is a channel-type MOSFET, the epitaxial layer 11 further includes at least one channel 11h in the device region R1, and the gate structure 12 is disposed in the channel 11h.

As shown in FIG. 3 , the gate structure 12 includes a gate insulating layer 120 and a gate 121 . The gate insulating layer 120 covers the inner wall surface of the channel 11 h to electrically insulate the gate 121 from the epitaxial layer 11 . The gate structure 12 in the device region R1 is connected to the first base region 111 and the first source region 113a.

In this embodiment, the second base region 112 is connected to the gate structure 12 closest to the ESD protection region R2.

The electrostatic protection stack P1 is disposed on the epitaxial layer 11 and located in the electrostatic protection region R2 for protecting the semiconductor device M1 from damage caused by electrostatic discharge. The electrostatic protection stack P1 includes an insulating layer 13 and an electrostatic protection layer 14 , and the insulating layer 13 is located between the electrostatic protection layer 14 and the epitaxial layer 11 to isolate the electrostatic protection layer 14 from the second base region 112 . Accordingly, the insulating layer 13 is directly connected to the second base region 112 .

In addition, since one terminal of the electrostatic protection layer 14 is at the same potential as the gate electrode 121 , the thickness of the insulating layer 13 can be determined according to the source-gate bias voltage (Vgs) applied to the semiconductor device M1 . When the source gate bias voltage (Vgs) is larger, the thickness of the insulating layer 13 needs to be thicker.

The electrostatic protection layer 14 includes at least one first heavily doped region 140 and at least one second heavily doped region 141 . In one embodiment, the first heavily doped region 140 has the same conductivity type as the first body region 111 and the second body region 112 , for example, all of them are P-type doped regions. The second heavily doped region 141 and the first source region 113a have the same conductivity type, for example, both are N-type doped regions, but the invention is not limited. Different conductivity types can also be added to add additional process steps to achieve doping results.

In addition, the lateral width of the electrostatic protection layer 14 is substantially the same as the lateral width of the insulating layer 13 . Further, the difference between the width of the electrostatic protection layer 14 and the width of the insulating layer 13 is less than 0.5um. In one embodiment, the electrostatic protection layer 14 is located above the second base region 112 , and the electrostatic protection layer 14 completely overlaps within the range of the second base region 112 .

It should be noted that the electrostatic protection layer 14 of the embodiment of the present invention is located above the second base region, and the electrostatic protection layer completely overlaps the second base region. Compared with the conventional semiconductor power device, The bottom of the electrostatic protection stack P1 in the embodiment of the present invention is not directly connected to the drift region 110 , but is only connected to the second base region 112 . Therefore, in the electrostatic protection region R2, the interface formed between the second base region 112 and the drift region 110 extends substantially along the direction of the parallel surface 11s.

In the semiconductor device M1 provided by the present invention, the electrostatic protection stack P1 is only connected to the second body region 112 , so when the semiconductor device M1 operates, the electric field strength at the interface between the second body region 112 and the drift region 110 is relatively high. uniform, so that the semiconductor component M1 of the embodiment of the present invention has a higher withstand voltage. Accordingly, compared with the existing semiconductor power components, the semiconductor component M1 of the embodiment of the present invention not only has the electrostatic discharge protection capability, but also has a certain voltage withstand capability.

Referring to FIG. 6 , a partial cross-sectional schematic diagram of a semiconductor device according to another embodiment of the present invention is shown. The same components in this embodiment as those in the embodiment in FIG. 3 have the same reference numerals, and the same parts will not be described again.

The difference between this embodiment and the embodiment of FIG. 3 is that in the semiconductor device M2 of this embodiment, the gate structure 12 is a planar gate structure. That is, the gate structure 12 is disposed on the surface 11s of the epitaxial layer 11 . In addition, in the device region R1 , the epitaxial layer 11 includes a plurality of first base regions 111 separated from each other, and each of the first source regions 113 a is respectively surrounded by the corresponding first base region 111 .

In addition, in this embodiment, the second base region 112 is connected to the gate structure 12 closest to the electrostatic protection region R2. Specifically, the second body region 112 is connected to the gate insulating layer 120 of the gate structure 12 .

The manufacturing method of the embodiment of the present invention can also be used to form the semiconductor device M2. Specifically, the gate structure 12 may be formed on the surface 11s of the epitaxial layer 11 in the device region R1 after the first base region 111 and the second base region 112 are formed.

Accordingly, in the manufacturing method of the semiconductor device of the present invention, as long as the second base region 112 can be formed under the electrostatic protection stack P1 completely overlapping with the second base region 112, the sequence of steps can be determined according to the structure of the semiconductor device itself or the requirements of the process. Adjustment.

To sum up the above, the beneficial effect of the present invention lies in the semiconductor device and the manufacturing method thereof provided by the technical solution of the present invention. The base region 112" and the technical means of "the electrostatic protection layer completely overlaps the second base region" can make the semiconductor device with the electrostatic protection stack P1 comply with the electrostatic discharge protection standard, and can also have a higher withstand voltage .

In addition, in the semiconductor device manufacturing method of the embodiment of the present invention, the step of forming the electrostatic protection stack P1 in the electrostatic protection region R2 can be integrated with the step of forming the transistor structure in the device R1, thereby reducing the manufacturing cost.

The contents disclosed above are only preferred feasible embodiments of the present invention, and are not intended to limit the scope of the present invention. Therefore, any equivalent technical changes made by using the contents of the description and drawings of the present invention are included in the application of the present invention. within the scope of the patent.

Symbol Description

Semiconductor components M1, M2

Substrate 10

Epitaxial layers 11, 11', 11"

Component area R1

Static protection zone R2

Channel 11h

Surface 11s

Drift Zone 110, 110’

first substrate region 111

second base region 112

Extension 112a

The first source region 113a

The second source region 113b

Gate Structure 12

Gate insulating layer 120

Gate 121

Initial insulating layer 13'

Undoped semiconductor layer 14P

Laminated structure P1’

Initial semiconductor layer 14"

Semiconductor layer 14'

ESD Protection Laminate P1

Insulation layer 13

Static Protection Layer 14

The first heavily doped regions 140, 140'

Second heavily doped region 141

Interlayer dielectric layer 15, 15'

Contact window 15h

Conductive Structure 16

The first conductive column 161

The second conductive column 162

Pad Set 17

first pad 171

second pad 172

protective layer 18

Base Doping Step 20

Heavy Doping Step 30

The first initial base doping region 111'

second initial base doping region 112'

Photoresist layer PR

Process steps S100～S130

Claims (15)

1. A method for manufacturing a semiconductor component, wherein the method for manufacturing the semiconductor component comprises: forming an epitaxial layer on a substrate, wherein the epitaxial layer is divided into at least one component area and an electrostatic protection area; forming a first base area in the component area, and forming a second base area in the electrostatic protection area; A stacked structure is formed on the surface of the epitaxial layer, the stacked structure is located in the electrostatic protection area, and includes an insulating layer and a semiconductor layer on the insulating layer, wherein the The semiconductor layer has a first heavily doped region; and At least one second heavily doped region is formed in the semiconductor layer, wherein the second heavily doped region and the first heavily doped region together form an electrostatic protection layer, and the electrostatic protection layer is located in the above the second base region, and the electrostatic protection layer completely overlaps within the range of the second base region. 2. The manufacturing method according to claim 1, wherein the step of forming at least one second heavily doped region in the semiconductor layer comprises: performing a doping step and a thermal infiltration step in sequence , so as to simultaneously form at least one first source region in the first body region of the device region, and to form the second heavily doped region in the semiconductor layer, the first heavily doped region The interface with the second heavily doped region is a PN junction. 3. The manufacturing method according to claim 2, further comprising: forming at least one gate structure in the component region, wherein the second base region has an extension portion, At least one of the gate structures is connected, and in the step of forming the first source region, a second source region located on the extension portion is simultaneously formed. 4. The manufacturing method according to claim 3, wherein the gate structure is a trench gate structure or a planar gate structure. 5. The manufacturing method of claim 1, wherein the step of forming the first base region and the second base region comprises: performing a base doping step on the epitaxial layer to form a first preliminary base doping region in the device region and a second preliminary base doping region in the electrostatic protection region; and A substrate heat-trapping step is performed to form the first substrate region and the second substrate region. 6. The manufacturing method according to claim 5, wherein the step of forming the laminated structure comprises: forming an initial insulating layer and an undoped semiconductor layer on the surface of the epitaxial layer in sequence; forming the first heavily doped region within the undoped semiconductor layer to form an initial semiconductor layer; and A part of the initial insulating layer and a part of the initial semiconductor layer in the component region are removed to form the stacked structure in the electrostatic protection region. 7. The manufacturing method of claim 1, wherein the first heavily doped region, the first base region and the second base region have the same conductivity type, and the first source The pole region and the second heavily doped region have the same conductivity type. 8. The manufacturing method according to claim 1, wherein the semiconductor layer is isolated from the epitaxial layer by the insulating layer, and the width of the semiconductor layer is separated from the width of the insulating layer. The difference is less than 0.5um. 9. The manufacturing method of claim 1, wherein in the step of forming the second heavily doped region in the semiconductor layer, the first heavily doped region is sandwiched between two between the second heavily doped regions. 10. A semiconductor component, which is divided into a component area and an electrostatic protection area, wherein the semiconductor component comprises: an epitaxial layer including a first base region located in the device region and a second base region located in the electrostatic protection region; a gate structure disposed in the device region and connected to at least the first base region; and an electrostatic protection layer disposed on a surface of the epitaxial layer and isolated from the epitaxial layer, wherein the electrostatic protection layer is located above the second base region, and the electrostatic protection layer completely overlaps within the second base region. 11. The semiconductor device of claim 10, wherein the electrostatic protection layer comprises a first heavily doped region and a second heavily doped region, and the first heavily doped region and the The interface of the second heavily doped region is a PN junction. 12. The semiconductor component of claim 10, wherein the semiconductor component further comprises an insulating layer, the insulating layer is located between the electrostatic protection layer and the epitaxial layer, and the insulating layer is connected to the second base region, and the difference between the width of the electrostatic protection layer and the width of the insulating layer is less than 0.5um. 13. The semiconductor device of claim 10, wherein the gate structure is a trench gate structure or a planar gate structure. 14. The semiconductor device of claim 10, wherein the epitaxial layer further comprises a first source region within the device region, the first source region being connected to the gate one side of the structure, and the first base region surrounds the first source region. 15. The semiconductor device of claim 14, wherein the second base region has an extension portion connected to the other side of the gate structure, and a second source region is located in the extension part above.

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