CN111369946A

CN111369946A - Display screen, mobile terminal and control method thereof

Info

Publication number: CN111369946A
Application number: CN201811593997.0A
Authority: CN
Inventors: 刘俊彦; 韦育伦
Original assignee: Huawei Device Co Ltd
Current assignee: Huawei Device Co Ltd
Priority date: 2018-12-25
Filing date: 2018-12-25
Publication date: 2020-07-03
Also published as: EP3889951A1; EP3889951A4; WO2020134914A1

Abstract

The embodiment of the application provides a display screen, a mobile terminal and a control method thereof, relates to the technical field of display, and solves the problem that the mobile terminal cannot realize regional brightness control according to user requirements or product design requirements. The display screen comprises a display driver, a first pixel array and a second pixel array. A first voltage input end of the pixel circuit of the first sub-pixel is electrically connected with a first signal end of the display driver and receives a first power supply voltage output by the first signal end. The second voltage input end is electrically connected with a second signal end of the display driver and receives a second power supply voltage output by the second signal end. And a third voltage input end of the pixel circuit of the second sub-pixel is electrically connected with a third signal end of the display driver and receives a third power supply voltage output by the third signal end. The fourth voltage input end is electrically connected with the second signal end of the display driver and receives a second power supply voltage output by the second signal end. The third supply voltage has a different voltage value than the first supply voltage.

Description

Display screen, mobile terminal and control method thereof

Technical Field

The application relates to the technical field of display, in particular to a display screen, a mobile terminal and a control method of the display screen and the mobile terminal.

Background

With the continuous development of display technology, mobile terminals with display functions, such as mobile phones, tablet computers, smart watches, and the like, have an increasing share in the market. However, at present, the mobile terminal cannot realize the brightness control in different areas according to the requirements of users or product design requirements, which is not favorable for improving the competitive power of products in the market.

Disclosure of Invention

The application provides a display screen, a mobile terminal and a control method thereof, and solves the problem that the mobile terminal cannot realize regional brightness control according to the requirements of users or product design requirements.

In order to achieve the purpose, the technical scheme is as follows:

in one aspect of the present application, a display panel is provided, the display panel including a display driver, a first pixel array, and a second pixel array, the display driver including a first signal terminal, a second signal terminal, and a third signal terminal, the first pixel array including a plurality of first sub-pixels, the pixel circuits in the first sub-pixels including a first voltage input terminal and a second voltage input terminal, the second pixel array including a plurality of second sub-pixels, the pixel circuits in the second sub-pixels including a third voltage input terminal and a fourth voltage input terminal, the pixel circuits of the first sub-pixels having first voltage input terminals electrically connected to the first signal terminals of the display driver, the first voltage input terminals receiving a first power supply voltage output from the first signal terminals, the second voltage input terminals electrically connected to the second signal terminals of the display driver, the second voltage input terminals receiving a second power supply voltage output from the second signal terminals, the third voltage input terminals of the pixel circuits of the second sub-pixels having second voltage input terminals electrically connected to the third signal terminals of the display driver, the third voltage input terminals receiving a third power supply voltage, the fourth voltage output from the pixel circuits, the pixel circuits of the second sub-pixels, the pixel array, the pixel circuits receiving a second power supply voltage, the elv-vss, and the second voltage input terminals of the pixel array, the pixels, the elv-elv circuit, wherein the pixel circuits are respectively connected to control the pixel circuits, the pixel array, the elv-elv circuit, and the elv circuit, and the elv circuit.

Optionally, the first power supply voltage output by the first signal terminal of the display driver is greater than the second power supply voltage output by the second signal terminal of the display driver. The third supply voltage output by the third signal terminal of the display driver is greater than the second supply voltage output by the second signal terminal of the display driver. In this case, the first subpixel and the second subpixel may share the second power supply voltage, i.e., the second power supply voltage is the voltage ELVSS.

Optionally, the pixel circuit of the first sub-pixel in the first pixel array includes a first driving transistor and a first light emitting device. The first electrode of the first driving transistor is electrically connected with the first signal end of the display driver, and the second electrode of the first driving transistor is electrically connected with the anode of the first light-emitting device; the cathode of the first light emitting device is electrically connected with the second signal terminal of the display driver. The second pixel array includes a plurality of second sub-pixels, and the pixel circuits in the second sub-pixels include second driving transistors and second light emitting devices. The first electrode of the second driving transistor is electrically connected with the third signal end of the display driver, and the second electrode of the second driving transistor is electrically connected with the anode of the second light-emitting device; the cathode of the second light emitting device is electrically connected to a second signal terminal of the display driver. In this case, the first electrode of the first driving transistor is the first voltage input terminal of the pixel circuit of the first sub-pixel. The cathode of the first light emitting device is a second voltage input end of the pixel circuit of the first sub-pixel. The first electrode of the second driving transistor is a third voltage input end of the pixel circuit of the second sub-pixel. The cathode of the second light emitting device is a fourth voltage input terminal of the pixel circuit of the second sub-pixel.

Optionally, the first power supply voltage output by the first signal terminal of the display driver is less than the second power supply voltage output by the second signal terminal of the display driver. The third supply voltage output by the third signal terminal of the display driver is less than the second supply voltage output by the second signal terminal of the display driver. In this case, the first subpixel and the second subpixel may share the second power supply voltage, which is the voltage ELVSS.

Optionally, the pixel circuit of the first sub-pixel in the first pixel array includes a first driving transistor and a first light emitting device. The first electrode of the first driving transistor is electrically connected with the second signal end of the display driver, and the second electrode of the first driving transistor is electrically connected with the anode of the first light-emitting device; the cathode of the first light emitting device is electrically connected to a first signal terminal of the display driver. The second pixel array includes a plurality of second sub-pixels, and the pixel circuits in the second sub-pixels include second driving transistors and second light emitting devices. The first electrode of the second driving transistor is electrically connected with the second signal end of the display driver, and the second electrode of the second driving transistor is electrically connected with the anode of the second light-emitting device; the cathode of the second light emitting device is electrically connected to a third signal terminal of the display driver. In this case, the first electrode of the first driving transistor is the second voltage input terminal of the pixel circuit of the first sub-pixel. The cathode of the first light emitting device is a first voltage input terminal of the pixel circuit of the first sub-pixel. The first electrode of the second driving transistor is a fourth voltage input end of the pixel circuit of the second sub-pixel. The cathode of the second light emitting device is a third voltage input terminal of the pixel circuit of the second sub-pixel.

Optionally, the display driver comprises a power management integrated circuit. The power management integrated circuit comprises a first voltage end, a second voltage end and a third voltage end. The first voltage terminal of the power management integrated circuit is electrically connected to the first voltage input terminal of the pixel circuit of the first subpixel. The second output terminal of the power management integrated circuit is electrically connected to the second voltage input terminal of the pixel circuit of the first subpixel and the fourth voltage input terminal of the pixel circuit of the second subpixel. A third output terminal of the power management integrated circuit is electrically connected to a third voltage input terminal of the pixel circuit of the second subpixel. Therefore, the brightness of the area where the first pixel array is located and the brightness of the area where the second pixel array is located can be controlled through one power management integrated circuit.

Optionally, the display driver comprises a first power management integrated circuit and a second power management integrated circuit. The first power management integrated circuit includes a first voltage terminal and a second voltage terminal. The second power management integrated circuit includes a third voltage terminal and a fourth voltage terminal. The first voltage terminal of the first power management integrated circuit is electrically connected to the first voltage input terminal of the pixel circuit of the first subpixel. The third voltage terminal of the second power management integrated circuit is electrically connected to the third voltage input terminal of the pixel circuit of the second subpixel. The second voltage terminal of the first power management integrated circuit is electrically connected to the second voltage input terminal of the pixel circuit of the first subpixel and the fourth voltage input terminal of the pixel circuit of the second subpixel. Alternatively, the fourth voltage terminal of the second power management integrated circuit is electrically connected to the second voltage input terminal of the pixel circuit of the first sub-pixel and the fourth voltage input terminal of the pixel circuit of the second sub-pixel. Therefore, the brightness of the area where the first pixel array is located and the brightness of the area where the second pixel array is located can be controlled through the first power management integrated circuit and the second power management integrated circuit respectively.

Optionally, the active display area includes an auxiliary display area and a main display area. Wherein the non-display side of the auxiliary display area is used for integrating a camera or a sensor. The first pixel array is located in the auxiliary display area. The second pixel array is located in the main display area. The pixel density of the auxiliary display area is less than that of the main display area. In this way, the sub-pixels in the auxiliary display area have more light transmitting area, so that more light is received or emitted by the camera or the sensor on the non-display side of the auxiliary display area through the display screen.

Optionally, the light-shielding area occupied by the pixel circuit of the first sub-pixel is the same as the light-shielding area occupied by the pixel circuit of the second sub-pixel. The light transmission area of the first sub-pixel except the pixel circuit is larger than that of the second sub-pixel except the pixel circuit.

Optionally, the display screen further includes a substrate base plate; the first pixel array and the second pixel array are arranged on the substrate base plate. Wherein the material constituting the base substrate includes a flexible resin material. The display driving circuit further comprises a processor, the processor is electrically connected with the at least one power management integrated circuit, and the processor is used for outputting a brightness control signal to the at least one power management integrated circuit when detecting that the first pixel array or the second pixel array is bent to the non-display side of the display screen. The display screen can be bent. When the first pixel array or the second pixel array is bent to the non-display side of the display screen, the brightness of the area where the pixel array bent to the non-display side of the display screen is located can be reduced through the processor.

In another aspect, a mobile terminal is provided, which includes any one of the above display screens. The mobile terminal also comprises a camera and a sensor. The camera, and/or the sensor, is located on a non-display side of the display screen. The mobile terminal has the same technical effect as the display screen provided by the foregoing embodiment, and details are not repeated here.

Optionally, the display screen includes an auxiliary display area and a main display area; the pixel density of the auxiliary display area is less than that of the main display area. The camera and the sensor are arranged on the non-display side of the auxiliary display area. When the camera and the sensor are located on the non-display side of the display screen, a full screen can be realized.

Optionally, an opening is provided on the display screen. The display screen includes auxiliary display areas located at both sides of the opening, and a main display area located below the opening. Wherein, the pixel density of the auxiliary display area is less than that of the main display area. The camera is located within the opening. The sensor is arranged on the non-display side of the auxiliary display area. The display screen is a special-shaped screen.

In another aspect, a method of controlling a mobile terminal is provided, the mobile terminal including a display screen. The display screen comprises a display driver, a first pixel array and a second pixel array. The display driver includes a first signal terminal, a second signal terminal, and a third signal terminal. The first pixel array comprises a plurality of first sub-pixels, and the pixel circuits in the first sub-pixels comprise first voltage input ends and second voltage input ends. The second pixel array comprises a plurality of second sub-pixels, and the pixel circuits in the second sub-pixels comprise third voltage input ends and fourth voltage input ends. A first voltage input end of the pixel circuit of the first sub-pixel is electrically connected with a first signal end of the display driver, and a second voltage input end of the pixel circuit of the first sub-pixel is electrically connected with a second signal end of the display driver. The third voltage input end of the pixel circuit of the second sub-pixel is electrically connected with the third signal end of the display driver, and the fourth voltage input end is electrically connected with the second signal end of the display driver. In addition, the display screen also comprises a substrate base plate; the first pixel array and the second pixel array are arranged on the substrate base plate; the substrate base plate is made of a flexible resin material, so that the display screen is a flexible display screen capable of being bent. Based on this, the control method of the mobile terminal includes that the display driver detects that the first sub-pixel array is bent to the non-display side of the display screen. Next, the first signal terminal of the display driver reduces the first supply voltage input to the first voltage input terminal of the pixel circuit of the first subpixel in the first subpixel array. Alternatively, the second signal terminal of the display driver increases the second supply voltage output to the second voltage input terminal of the pixel circuit of the first subpixel. At this time, the light emission luminance of the first subpixel decreases. Wherein the first supply voltage is greater than the second supply voltage. The control method of the mobile terminal has the same technical effects as the mobile terminal provided by the foregoing embodiment. And will not be described in detail herein.

Drawings

Fig. 1 is a schematic structural diagram of a display screen according to some embodiments of the present application;

FIG. 2 is a schematic diagram of a pixel circuit of each sub-pixel in FIG. 1;

FIG. 3 is a timing diagram of a portion of the control signals of the pixel circuit shown in FIG. 2;

fig. 4 is an equivalent circuit diagram of the pixel circuit shown in fig. 2 corresponding to the third stage in fig. 3;

FIG. 5a is a graph of the current through the OLED of FIG. 2, as well as the voltage applied between the cathode and anode of the OLED;

FIG. 5b is a graph of the output characteristics of the driving transistor of FIG. 2;

FIG. 5c is a schematic diagram of another display screen provided in accordance with some embodiments of the present application;

fig. 6a is a schematic structural diagram of a mobile terminal according to some embodiments of the present application;

fig. 6b is a schematic structural diagram of a mobile terminal according to some embodiments of the present application;

fig. 6c is a schematic structural diagram of a mobile terminal according to some embodiments of the present application;

FIG. 7 is a schematic diagram of the division of the display area around the opening in FIG. 6a or FIG. 6 b;

FIG. 8 is a schematic view of an arrangement of sub-pixels around the opening in FIG. 6a or FIG. 6 b;

FIG. 9 is a schematic view of another arrangement of sub-pixels around the opening in FIG. 6a or FIG. 6 b;

FIG. 10 is a schematic view of the arrangement of the sensor of FIG. 6 b;

FIG. 11a is a schematic view of an arrangement of sub-pixels around the opening in FIG. 6 b;

FIG. 11b is a schematic diagram of a pixel circuit of a portion of the sub-pixels shown in FIG. 11 a;

FIG. 11c is a schematic view of another arrangement of sub-pixels around the opening in FIG. 6 b;

FIG. 12a is a schematic view of another arrangement of sub-pixels around the opening in FIG. 6 b;

FIG. 12b is a schematic view of another arrangement of sub-pixels around the opening in FIG. 6 b;

FIG. 12c is a schematic diagram of the pixel circuit of a portion of the sub-pixels shown in FIG. 12b

FIG. 13a is a schematic diagram of a display screen according to some embodiments of the present application;

FIG. 13b is a schematic view of another embodiment of a display screen provided in accordance with the present application;

FIG. 13c is a schematic diagram of an output characteristic of a driving transistor in a pixel circuit of a display panel according to some embodiments of the present application;

FIG. 14a is a schematic view of another embodiment of a display screen provided in accordance with the present application;

FIG. 14b is a schematic view of another embodiment of a display screen provided in accordance with the present application;

FIG. 15 is a schematic structural diagram of a cathode layer in a display panel according to some embodiments of the present application;

FIG. 16 is a schematic cross-sectional view of a display screen provided in accordance with some embodiments of the present application;

FIG. 17 is a schematic view of a display screen provided in accordance with some embodiments of the present application;

FIG. 18a is a schematic view of a display screen according to some embodiments of the present application in a folded configuration;

FIG. 18b is a schematic view of the display screen shown in FIG. 18a after being folded in the folding manner;

FIG. 19 is a schematic view of another folding of a display screen provided in accordance with some embodiments of the present application;

FIG. 20 is a schematic view of another folding of a display screen provided in accordance with some embodiments of the present application;

FIG. 21a is a schematic diagram of a division of display sub-regions of a display screen according to some embodiments of the present application;

FIG. 21b is a schematic diagram of the connection structure between the PMIC of FIG. 21a and the pixel circuit of each sub-pixel;

FIG. 22a is a schematic illustration of another division of display sub-regions of a display screen according to some embodiments of the present application;

FIG. 22b is a schematic diagram of the connection structure between the PMIC of FIG. 22a and the pixel circuit of each sub-pixel;

FIG. 23 is a schematic view of another display screen provided in accordance with some embodiments of the present application;

fig. 24 is a schematic diagram of another division manner of display sub-areas of a display screen according to some embodiments of the present application.

Reference numerals:

01-mobile terminal; 02-pixel; 03-a display driver; 113-a first signal terminal of a display driver; 123-a second signal terminal of the display driver; 133-third signal terminal of display driver; 10-a display screen; 11-a camera; 12-an infrared sensor; 13-a three-dimensional sensor; 20-sub-pixel; 20 a-a first subpixel; 112-a first voltage input of a first subpixel; 122-a second voltage input of the first subpixel; 20 b-a second subpixel; 20 c-a third subpixel; 132-a third voltage input of the second subpixel; 142-a fourth voltage input of the second subpixel; region 100-AA; 101-non-display area; 110-an auxiliary display area; 120-a main display area; 201-pixel circuits; 200-opening; 30-PMIC; 31-a processor; 300-a cathode layer; 301-a first electrode block; 302-a second electrode block; 21-pixel definition layer; 22-the anode of the OLED; 23-an organic functional layer; 24-the cathode of the OLED; 400-TFT backplane; 41-a first pixel array; 42-second pixel array.

Detailed Description

The technical solutions in the embodiments of the present invention will be described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments.

The terms "first", "second" and "first" are used herein for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified.

Further, the directional terms "upper", "lower", "left" and "right" are defined herein with respect to the schematically-placed orientation of the display panel in the drawings, and it is to be understood that these directional terms are relative concepts that are used for descriptive and clarifying purposes relative thereto, and may vary accordingly depending on the change in the orientation in which the display panel is placed.

The present disclosure provides a mobile terminal, which may be a mobile phone, a tablet computer, a notebook, a Personal Digital Assistant (PDA), a vehicle-mounted computer, or the like. The embodiment of the present application does not specifically limit the specific form of the mobile terminal.

The mobile terminal includes a display screen 10 as shown in fig. 1. The display screen 10 is an Organic Light Emitting Diode (OLED) display screen. The OLED display screen has the characteristics of self luminescence, response speed block, wide viewing angle, capability of being manufactured on a flexible substrate and the like.

In addition, the display screen 10 includes an Active Area (AA) 100 and a non-display area 101 located at the periphery of the AA area 100.

The active display area 100 includes a plurality of sub-pixels 20. For convenience of description, the plurality of sub-pixels 20 are described as an example of a matrix arrangement in the present application.

At this time, the sub-pixels 20 arranged in a line in the horizontal direction X are referred to as sub-pixels in the same row, and the sub-pixels 20 arranged in a line in the vertical direction Y are referred to as sub-pixels in the same column.

In addition, a pixel circuit 201 for controlling the sub-pixel 20 to perform display is provided in the sub-pixel 20. As shown in fig. 2, the pixel circuit 201 includes a capacitor C and a plurality of switching transistors (M1, M2, M3, M5, M6, M7) and a driving transistor M4.

It should be noted that the operation process of the pixel circuit 201 shown in fig. 2 includes three stages shown in fig. 3, namely, a first stage ①, a second stage ②, and a third stage ③.

In the first stage ①, under the control of the first gate signal N-1, in fig. 2, the transistor M1 and the transistor M7 are turned on, and the initial voltage Vint is transmitted to the gate (gate, abbreviated as g) of the driving transistor M4 and the anode (anode, abbreviated as a) of the OLED through the transistor M1 and the transistor M7, respectively, so as to reset the anode a of the OLED and the gate g of the driving transistor M4.

In the second stage ②, under the control of the second gate signal N, the transistor M2 and the transistor M3 are turned on, when the transistor M3 is turned on, the gate g and the drain (drain, d) of the driving transistor M4 are electrically connected, and the driving transistor M4 is in a diode conducting state, at this time, the data signal Vdata is written to the source(s) of the driving transistor M4 through the turned-on transistor M2, and the threshold voltage Vth of the driving transistor M4 is compensated.

A third stage ③ in which the transistor M5 and the transistor M6 are turned on and the current path between the voltage ELVDD and ELVSS is turned on under the control of the emission control signal EM, and the equivalent circuit diagram of the third stage is shown in FIG. 4. the driving transistor M4 is turned on, the first electrode (source s) of the driving transistor M4 receives the voltage ELVDD, the second electrode of the driving transistor M4 and the anode of the OLED are connectedThe poles (a) are electrically connected. The cathode (c) of the OLED receives the voltage ELVSS. In this case, the driving transistor M4 generates the driving current I_sdThe current is transmitted to the OLED through the current path to drive the OLED to emit light.

As can be seen from fig. 4, the voltage difference △ V between the voltage ELVDD and the voltage ELVSS satisfies the following formula (1):

△V＝ELVDD-ELVSS＝V_sd+V_OLED(1)

wherein, V_sdIs the source voltage of the drive transistor M4; v_OLEDIs the voltage difference between the anode (a) and the cathode (c) of the OLED.

The luminance of the light emitted in the third phase ③ and the current I flowing through the OLED_OLED(with the above-mentioned drive current I)_dsThe same) is proportional.

Furthermore, as shown in FIG. 5a, I_OLEDAnd V_OLEDIs in direct proportion. In this case, when the light emitting luminance of a subpixel 20 is larger, V of the OLED in the subpixel 20_OLEDThe larger the value, the larger the value of △ V-ELVSS in equation (1), and the smaller the value.

In this case, the OLED display screen 10 provided in the embodiment of the present application may adjust the size of the △ V-ELVDD-ELVSS for different areas as needed to implement the divisional area brightness control.

In order to realize the regional brightness control, the embodiment of the application provides a display screen 01. As shown in fig. 5c, the display panel 01 includes a display driver 03, a first pixel array 41, and a second pixel array 42.

The display driver 03 includes a first signal terminal 113, a second signal terminal 123, and a third signal terminal 133.

In addition, the first pixel array 41 includes a plurality of first sub-pixels 12 a. The pixel circuit 201 of the first sub-pixel 12a comprises a first voltage input 112 and a second voltage input 122.

The second pixel array 42 includes a plurality of second sub-pixels 12 b. The pixel circuit 201 of the second subpixel 12b comprises a third voltage input 132 and a fourth voltage input 142.

The first voltage input terminal 112 of the pixel circuit 201 of the first sub-pixel 12a is electrically connected to the first signal terminal 113 of the display driver 03, and receives the first supply voltage V1 output from the first signal terminal 113.

The second voltage input terminal 122 of the pixel circuit 21 of the first sub-pixel 12a is electrically connected to the second signal terminal 123 of the display driver 03, and receives the second power supply voltage V2 output from the second signal terminal 123.

The third voltage input terminal 132 of the pixel circuit 201 of the second sub-pixel 12b is electrically connected to the third signal terminal 133 of the display driver 03, and receives the third power supply voltage V3 outputted from the third signal terminal 133.

The fourth voltage input terminal 142 of the pixel circuit 201 of the second sub-pixel 12b is electrically connected to the second signal terminal 123 of the display driver 03, and receives the second power supply voltage V2 outputted from the second signal terminal 123.

Wherein the third supply voltage V3 has a different voltage value than the first supply voltage V1.

In some embodiments of the present application, the first supply voltage V1 is greater than the second supply voltage V2, and the third supply voltage V3 is also greater than the second supply voltage V2. At this time, the second power supply voltage V2 may be the voltage ELVSS. In this case, the pixel circuits 102 of the first and

second pixel arrays

41 and 42 share the voltage ELVSS.

Alternatively, in other embodiments of the present application, the first power supply voltage V1 is less than the second power supply voltage V2, and the third power supply voltage V3 is also less than the second power supply voltage V2. At this time, the second power supply voltage V2 may be the voltage ELVDD. In this case, the pixel circuits 102 of the first and

second pixel arrays

41 and 42 share the voltage ELVDD.

In this way, by supplying power to the pixel circuits 102 of the first pixel array 41 and the second pixel array 42, △ V of each pixel circuit in the area where the first pixel array 41 is located is adjusted to the ELVDD-ELVSS value, and △ V of each pixel circuit in the area where the second pixel array 42 is located is adjusted to the ELVDD-ELVSS value, thereby realizing luminance division control of the display panel 01.

The following illustrates a process of performing brightness partition control on the display screen 01 in different scenes.

Example one

In this embodiment, a mobile terminal 01 having a display screen 10 is integrated with various electronic devices for implementing different functions, such as a camera 11, an infrared sensor (IR sensor)12, a three-dimensional sensor (3D sensor)13, and the like as shown in fig. 6 a.

In order to increase the screen ratio (the ratio of the effective display area of the display screen to the whole display screen) of the display screen 10 of the mobile phone, in some embodiments of the present application, an opening 200 is formed on the display screen 10 of the mobile terminal 01.

Thus, the electronic device can be disposed in the opening 200. On the basis, the parts of the display screen 10 on both sides of the opening 200 can still display, thereby achieving the purpose of improving the display screen ratio.

On this basis, in order to further improve the screen occupation ratio of the display screen 10, as shown in fig. 6b, a part of the electronic devices, such as the IR sensor12 and the 3D sensor13, may be disposed below the display screen 10 (under display), i.e., the non-display side of the display screen, i.e., the receiver and transmitter of the IR sensor12, and the receiver and transmitter of the 3D sensor13 are disposed below the display screen 10. The camera 11 is disposed in the opening 200.

Alternatively, as shown in fig. 6c, all of the IR sensor12, the 3D sensor13, and the camera 11 may be disposed below the display screen 10, that is, on the non-display side of the display screen. Thereby further improving the screen occupation ratio of the display screen 10 and achieving the effect of a full screen.

In the embodiment of the present application, the structure shown in fig. 6b may be adopted, or the structure shown in fig. 6c may be adopted, which is not limited in the present application. For convenience of explanation, the following description will be made by taking the shaped screen shown in fig. 6b as an example.

In this case, the light emitted from the transmitter of the sensor may pass through the display screen, and the light transmitted by the sub-pixel 20 is emitted from the display screen 10, and when the light emitted from the sensor encounters an obstacle, the light may be reflected, and the reflected light may pass through the light transmitted by the sub-pixel 20 in the display screen and enter the receiver of the sensor, so that the sensor may perform a sensing operation according to the received reflected light. Thus, the area of the opening 200 can be reduced, and the purpose of improving the screen occupation ratio can be achieved.

However, the AA area 100 of the display screen 10 needs to bypass the opening 200 under the influence of the opening 200. Thus, the AA area 100 of the display screen 10 is no longer a complete rectangle. At this time, as shown in fig. 7, the AA area 100 of the display screen 10 may be divided into an auxiliary display area 110 located at both sides of the opening 200 and a main display area 120 located below the opening 200 and the auxiliary display area 110.

In this case, the first pixel array 41 is disposed in the auxiliary display region 110, and the first pixel array 41 includes a plurality of the first sub-pixels 20a as shown in fig. 8.

The second pixel array 42 is disposed in the main display area 120, and the second pixel array 42 includes a plurality of second sub-pixels 20b as shown in fig. 8.

As shown in fig. 8, the second sub-pixels 20b are arranged in the entire row in the horizontal direction X in the main display area 120. For example, in the main display area 120, the number of the second sub-pixels 20b in one row is N in the horizontal direction X. N is more than or equal to 2 and is a positive integer.

In addition, due to the opening 200, the number of the first sub-pixels 20a in one row is M in the horizontal direction X in the auxiliary display area 110. M is more than or equal to 2 and less than or equal to N, and M is a positive integer.

However, as is apparent from the above description, the pixel circuit 201 of the display panel 10 includes a plurality of transistors. The transistor is mainly made of a non-light-transmissive metal material, so that the metal density (metal density) of the first sub-pixel 20a or the second sub-pixel 20b is relatively high, and the light-transmissive area of the first sub-pixel 20a or the second sub-pixel 20b is correspondingly reduced.

In this case, when the under display technology is adopted, the light emitted by the emitters of the

IR sensors

12 and 3D sensor13 cannot effectively pass through the light-transmitting portion of the first sub-pixel 20a to exit, and the reflected light cannot effectively pass through the light-transmitting portion of the first sub-pixel 20a and is incident on the receivers of the

IR sensors

12 and 3D sensor13, thereby reducing the detection accuracy of the sensors.

In some embodiments of the present application, in order to improve the detection accuracy of the sensor. As shown in fig. 9, a pixel density (PPI) of the auxiliary display region 110 may be made smaller than that of the main display region 120.

Thus, the area of the first sub-pixel 20a of the auxiliary display region 110 is larger than the area of the second sub-pixel 20b of the main display region 120, so that the light transmission area of the first sub-pixel 20a of the auxiliary display region 110 is larger than the light transmission area of the second sub-pixel 20b of the main display region 120.

Based on this, as shown in fig. 10, the first sub-pixel 20a in the auxiliary display area 110 has enough light-transmitting portion to enable the light transmitted by the transmitters of the

IR sensors

12 and 3D sensor13 to exit from the display screen 10, and the above reflected light can also be transmitted through the light-transmitting portion of the first sub-pixel 20a in the auxiliary display area 110 to be incident into the receivers of the sensors, such as the

IR sensors

12 and 3D sensor13, located below the auxiliary display area 110. Therefore, the sensor can send and receive more light rays, and the sensing precision of the sensor is improved.

In order to make the PPI of the auxiliary display region 110 smaller than that of the main display region 120, the present application provides the following scheme.

Example 1

In this example, the number of the first sub-pixels 20a in one pixel 02 of the auxiliary display area 110 is different from the number of the second sub-pixels 20b in one pixel 02 of the main display area 120.

For example, as shown in fig. 11a, in the display panel 10, the length L1 in the X direction and the length L2 in the Y direction of any two pixels (pixels) 02 are the same.

In addition, in one pixel 02 of the auxiliary display region 110, the number of the first sub-pixels 20a is smaller than the number of the second sub-pixels 20b in one pixel 02 of the main display region 120. So that the area of the first subpixel 20a of the auxiliary display region 110 may be made larger than the area of the second subpixel 20b of the main display region 120.

For example, the auxiliary display area 110 includes three first sub-pixels 20a, namely, a red (R) first sub-pixel, a green (G) first sub-pixel, and a blue (B) first sub-pixel, in one pixel 02.

One pixel 02 of the main display area 120 includes four second sub-pixels 20B, i.e., R second sub-pixel, G second sub-pixel, B second sub-pixel, and W (white, W) second sub-pixel.

In this case, the pixel circuits of any one of the first subpixel 20a and the second subpixel 20b in the display panel 10 are configured as shown in fig. 2 as an example.

As shown in fig. 11b, in the Y direction, in the pixel circuit of the first sub-pixel 20a in the same column in the auxiliary display region 110, the source(s) of the transistor M2 is electrically connected to the same Data Line (DL). The DL is used to supply a data voltage Vdata.

In addition, in the Y direction, in the pixel circuit of the second sub-pixel 20b in the same column in the main display area 120, the source(s) of the transistor M2 is electrically connected to the same bar DL.

Based on this, as can be seen from fig. 11b, the pixel circuits of the third column of the first sub-pixels 20a of the auxiliary display area 110 and the pixel circuits of the fourth column of the second sub-pixels 20b of the main display area 120 are electrically connected to the same DL along the Y direction.

In addition, in the Y direction, the DL electrically connected to the pixel circuit of the first column of the second sub-pixel 20b, the pixel circuit of the second column of the second sub-pixel 20b, and the pixel circuit of the third column of the second sub-pixel 20b of the main display area 120 need not be shared with the pixel circuit of the auxiliary display area 110.

Alternatively, for example, as shown in fig. 11c, one pixel 02 of the auxiliary display region 110 includes three first sub-pixels 20a, which are an R first sub-pixel, a G first sub-pixel, and a B first sub-pixel.

The pixel arrangement of the main display area 120 adopts a pentile manner. That is, one pixel 02 of the main display area 120 includes two second sub-pixels 20b, which are R second sub-pixels and G second sub-pixels; or B second sub-pixel and G second sub-pixel.

Wherein the area of the R second sub-pixel and the B second sub-pixel in the main display region 120 is twice that of the G second sub-pixel. Two adjacent pixels 02 share either the R second sub-pixel or the B second sub-pixel.

Further, in the display screen 10, the length L1b of one pixel 02 of the auxiliary display area 110 in the X direction is larger than the length L1a of one pixel 02 of the main display area 120 in the X direction. So that the area of the first subpixel 20a of the auxiliary display region 110 may be made larger than the area of the first subpixel 20b of the main display region 120.

In the display panel 10 shown in fig. 11c, the connection between the pixel circuits of the sub-pixels and the DL can be set with reference to fig. 11b, and details thereof are not repeated.

Example two

In this example, as shown in fig. 12a or12 b, the number of first sub-pixels 20a in one pixel 02 of the auxiliary display area 110 is the same as the number of second sub-pixels 20b in one pixel 02 of the main display area 120.

One pixel 02 of the main display region 120 includes three second sub-pixels 20B, which are the R second sub-pixel, the G second sub-pixel, and the B second sub-pixel.

Further, as shown in fig. 12a or12 b, in the display screen 10, the length L1b of the pixels 02 of the auxiliary display area 110 in the X direction is greater than the length L1a of the pixels 02 of the main display area 120 in the X direction. In FIG. 12b, L1b is about twice L1 a. The length L2b of the pixel 02 of the auxiliary display area 110 in the Y direction may be the same as the length L2a of the pixel 02 of the main display area 120 in the Y direction. So that the area of the first subpixel 20a of the auxiliary display region 110 is greater than the area of the second subpixel 20b of the main display region 120.

In this case, the structure shown in fig. 12b is taken as an example, and the pixel circuit of any one of the sub-pixels in the display panel 10 is taken as an example as shown in fig. 2.

As shown in fig. 12c, in the Y direction, in the pixel circuit of the first sub-pixel 20a in the same column in the auxiliary display area 110, the source(s) of the transistor M2 is electrically connected to the same bar DL. The DL is used to supply a data voltage Vdata.

Based on this, as can be seen from fig. 12c, the pixel circuits of the first column of the first sub-pixels 20a of the auxiliary display area 110 and the pixel circuits of the second column of the second sub-pixels 20b of the main display area 120 are electrically connected along the Y direction with the same DL.

The pixel circuit of the second column of the first sub-pixel 20a of the auxiliary display region 110 and the pixel circuit of the fourth column of the second sub-pixel 20b of the main display region 120 are electrically connected to the same DL.

The pixel circuit of the third column of the first sub-pixel 20a of the auxiliary display region 110 and the pixel circuit of the sixth column of the second sub-pixel 20b of the main display region 120 are electrically connected to the same DL.

In addition, in the Y direction, the DL electrically connected to the pixel circuit of the first column of the second sub-pixel 20b, the pixel circuit of the third column of the second sub-pixel 20b, and the pixel circuit of the fifth column of the second sub-pixel 20b of the main display area 120 need not be shared with the pixel circuit of the auxiliary display area 110. Therefore, the DL, which may be electrically connected to the pixel circuit of the first column of the second subpixel 20b, the pixel circuit of the third column of the second subpixel 20b, and the fifth column of the second subpixel 20b of the main display area 120, may be disposed only within the main display area 120.

In this case, the PPI of the auxiliary display region 110 may be made smaller than the PPI of the main display region 120 by the above-described various arrangements. For convenience of explanation, the following description will be given by taking the structure shown in fig. 12b as an example.

When the display screen 10 displays a picture, the brightness S1_ a of each pixel 02 in the auxiliary display area 110 is proportional to the ratio of the brightness S1 of the auxiliary display area 110 to the aperture ratio a _ a of the auxiliary display area 110, i.e., S1_ a ∈ (S1/a _ a).

The luminance S2_ b of each pixel 02 in the main display area 120 is proportional to the ratio of the luminance S2 of the main display area 120 to the aperture ratio A _ b of the main display area 120, i.e., S2_ b ℃, (S2/A _ b).

Wherein the aperture ratio is a ratio of an area of a light emitting region of a sub-pixel to the area of the sub-pixel.

Based on this, in the manufacturing process, the areas of the light emitting regions of the first sub-pixel 20a of the auxiliary display region 110 and the second sub-pixel 20b of the main display region 120 are set to be the same. As can be seen from the above description, the area of the first sub-pixel 20a of the auxiliary display region 110 is larger than the area of the second sub-pixel 20b of the main display region 120. Therefore, the aperture ratio a _ a of the auxiliary display area 110 is smaller than a _ b of the main display area 120.

In this case, in the case where the auxiliary display region 110 and the main display region 120 are displaying the same gray scale screen, for example, the gray scale screen of G255, the brightness S1 of the auxiliary display region 110 needs to be the same as the brightness S2 of the main display region 120. Therefore, as can be seen from the above-mentioned relations S1_ a ∈ (S1/a _ a) and S2_ b ∈ (S2/a _ b), the luminance S1_ a of the single pixel 02 in the auxiliary display region 110 is larger than the luminance S2_ b of the single pixel 02 in the main display region 120. That is, the light emitting luminance of the OLED in any one of the first sub-pixels 20a of the auxiliary display area 110 is greater than the light emitting luminance of the OLED in any one of the second sub-pixels 20b of the main display area 120.

As can be seen from the above, the luminance of the OLED and the current I flowing through the OLED_OLED(i.e., the above-mentioned drive current I)_ds) Is in direct proportion. Current I_OLEDA voltage difference V between the anode (a) and the cathode (c) of the OLED_OLEDIs in direct proportion.

Furthermore, as can be seen from the above formula (1), the voltage difference △ V between the voltage ELVDD and the voltage ELVSS in the pixel circuit of any one of the first sub-pixels 20a in the auxiliary display area 110₁＝ELVDD-ELVSS＝V_sd1+V_OLED＝V_sd1+V₁。

A voltage difference △ V between the voltage ELVDD and the voltage ELVSS in the pixel circuit of any one of the second sub-pixels 20b in the main display area 120₀＝ELVDD-ELVSS＝V_sd0+V_OLED＝V_sd0+V₀。

Therein, theIn this case, as shown in fig. 5a, a voltage difference V between an anode (a) and a cathode (c) of the OLED in the pixel circuit of the auxiliary display area 110_OLED(V as shown in FIG. 5a₁) Greater than a voltage difference V between an anode (a) and a cathode (c) of the OLED in the pixel circuit of the main display area 120_OLED(V as shown in FIG. 5a₀)。

In addition, the source voltage V of the driving transistor M4 in the pixel circuit 201 of the auxiliary display area 110_sd1Is larger than the source voltage V of the driving transistor M4 in the pixel circuit 201 of the main display area 120_sd0。

Therefore △ V₁＞△V₀。

In this case, when the pixel circuits 201 of the auxiliary display area 110 and the pixel circuits 201 of the main display area 120 share the voltage ELVDD and the voltage ELVSS, in order to satisfy the requirement that the auxiliary display area 110 needs to emit higher luminance, the actual source voltage Vsd of the driving transistor M4 is applied to the pixel circuits of the main display area 120 in the vicinity of the point a2 of the characteristic curve S _120 as shown in fig. 5 b.

However, in the pixel circuit 201 of the main display area 120, the source voltage V of the driving transistor M4_sdWhen the voltage is near the saturation point a1 of the characteristic curve S _120 (the intersection point where the characteristic curve of the transistor changes from curved to straight), the driving transistor M4 can be turned on completely, so that the main display region 120 displays a gray-scale image of G255. Since the voltage at point a2 is greater than the voltage at saturation point a1, power is wasted.

In order to solve the above problems, embodiments of the present application provide the following solutions.

Example three

In this example, the first power supply voltage V1 is greater than the second power supply voltage V2, and the third power supply voltage V3 is also greater than the second power supply voltage V2. At this time, the second power supply voltage V2 may be the voltage ELVSS. In this case, the pixel circuits 102 of the auxiliary display area 110 and the main display area 120 share the voltage ELVSS.

Wherein, the first power supply voltage V1 > the third power supply voltage V3.

For example, the auxiliary display area 110 and the main display area 120 are displayedFor example, the first power supply voltage V1 may be about 5.6V in gray scale image G255. At this time, in the pixel circuit 201 of the auxiliary display area 110, the source voltage V of the first driving transistor M4a_sdAt the saturation point C1 (shown in fig. 13C) of the characteristic curve of the driving transistor M4 a.

The third supply voltage V3 may be around 4.6V. At this time, in the pixel circuit 201 of the main display area 120, the source voltage V of the second driving transistor M4b_sdAt the saturation point C2 (shown in fig. 13C) of the characteristic curve of the driving transistor M4 b.

In this case, the display driving circuit 03 includes a Power Management Integrated Circuit (PMIC) 30 as shown in fig. 13 a. The PMIC30 includes a first voltage terminal B1, a second voltage terminal B2, and a third voltage terminal B3.

The first voltage terminal B1 of the PMIC30 is used as the first signal terminal 113 of the display driver 03.

The second voltage terminal B2 of the PMIC30 serves as the second signal terminal 123 of the display driver 03.

The third voltage terminal B3 of the PMIC30 serves as the third signal terminal 133 of the display driver 03.

Based on this, as shown in fig. 13a, according to the equivalent circuit diagram of the pixel circuit 201 shown in fig. 4, in the pixel circuit 201 of the auxiliary display area 110, the first pole (source s) of the first driving transistor M4a is used as the first sub-pixel 20a, and the first voltage input terminal 112 of the pixel circuit 201 is electrically connected to the first voltage terminal B1 of the PMIC 30. The first voltage terminal B1 of the PMIC30 provides a first supply voltage V1 to the first pole (source s) of the first drive transistor M4 a.

In addition, the second electrode (drain D) of the first driving transistor M4a is electrically connected to the anode (a) of the first light emitting device D1 in the first subpixel 20 a.

The cathode (c) of the first light emitting device D1 is electrically connected to the second voltage terminal B2 of the PMIC30 as the second voltage input terminal 122 of the pixel circuit 201 in the first sub-pixel 20 a. The second voltage terminal B2 of the PMIC30 provides the second power supply voltage V2, i.e., the voltage ELVSS, to the cathode (c) of the first light emitting device D1.

Similarly, as shown in the equivalent circuit diagram of the pixel circuit 201 shown in fig. 4, as shown in fig. 13a, the first electrode (source s) of the second driving transistor M4B in the main display area 120 is electrically connected to the third voltage terminal B3 of the PMIC30 as the third voltage input terminal 132 of the pixel circuit 201 in the second sub-pixel 20B. The third voltage terminal B3 of the PMIC30 provides a third supply voltage V3 to the first pole (source s) of the second drive transistor M4B.

In addition, the second electrode (drain D) of the second driving transistor M4b is electrically connected to the anode (a) of the second light emitting device D2 in the second subpixel 20 b.

The cathode (c) of the second light emitting device D2 is electrically connected to the second voltage terminal B2 of the PMIC30 as the fourth voltage input terminal 142 of the pixel circuit 201 of the second sub-pixel 20B. The second voltage terminal B2 of the PMIC30 provides the second power supply voltage V2, i.e., the voltage ELVSS, to the cathode (c) of the second light emitting device D2. Thereby achieving the purpose of sharing ELVSS for the first subpixel 20a and the second subpixel 20 b.

As can be seen from the above, the pixel circuits 201 of the auxiliary display area 110 and the pixel circuits 201 of the main display area 120 share the second power supply voltage V2, i.e., the voltage ELVSS, output from the second voltage terminal B2 of the PMIC 30. In this case, the current sink capability of the second voltage terminal B2 of the PMIC30 is the current I provided by the first voltage terminal B1 of the PMIC30_B1And a third voltage terminal B3 provides the current I_B2And (4) summing.

For example, the first voltage terminal B1 of PMIC30 provides a first supply voltage V1 of 5.6V to the pixel circuit 201 of the auxiliary display area 110 and provides a current I_B1＝400mA。

The third voltage terminal B3 of the PMIC30 provides a third supply voltage V3 of 4.6V to the pixel circuit 201 of the main display area 120 and provides a current I_B2＝50mA。

In this case, the current sinking capability of the second voltage terminal B2 of the PMIC30 is greater than or equal to I_B1+I_B2＝400mA+50mA＝450mA。

Example four

Wherein, the first power supply voltage V1 > the third power supply voltage V3.

The difference from the third example is that the display driving circuit 03 includes two PMICs 30 as shown in fig. 13b, including a first PMIC30_ a and a second PMIC30_ b.

The first PMIC30_ a includes a first voltage terminal B1 and a second voltage terminal B2.

The second PMIC30_ a includes a third voltage terminal B3 and a fourth voltage terminal B4.

The first voltage terminal B1 of the first PMIC30_ a serves as the first signal terminal 113 of the display driver 03.

The third voltage terminal B3 of the second PMIC30_ B serves as the third signal terminal 133 of the display driver 03.

The second voltage terminal B2 of the first PMIC30_ a serves as the second signal terminal 123 of the display driver 03.

Alternatively, the fourth voltage terminal B4 of the second PMIC30_ B is used as the second signal terminal 123 of the display driver 03.

Based on the above, as can be seen from the equivalent circuit diagram of the pixel circuit 201 shown in fig. 4, as shown in fig. 13B, in each pixel circuit 201 of the auxiliary display area 110, the first pole (source s) of the first driving transistor M4a is used as the first voltage input terminal 112 of the pixel circuit 201 in the first sub-pixel 20a and is electrically connected to the first voltage terminal B1 of the first PMIC30_ a. The first voltage terminal B1 of the first PMIC30_ a provides the first supply voltage V1 to the first pole (source s) of the first drive transistor M4 a.

The cathode (c) of the first light emitting device D1 is used as the second voltage input terminal 122 of the pixel circuit 201 in the first sub-pixel 20a and is electrically connected to the second voltage terminal B2 of the first PMIC30_ a. The second voltage terminal B2 of the first PMIC30_ a provides the second power supply voltage V2, i.e., the voltage ELVSS, to the cathode (c) of the first light emitting device D1.

Similarly, as shown in fig. 13B, according to the equivalent circuit diagram of the pixel circuit 201 shown in fig. 4, in the main display area 120, the first pole (source s) of the second driving transistor M4B is used as the third voltage input terminal 132 of the pixel circuit 201 in the second sub-pixel 20B and is electrically connected to the third voltage terminal B3 of the second PMIC30_ B. The third voltage terminal B3 of the second PMIC30_ B provides a third supply voltage V3 to the first pole (source s) of the second driving transistor M4B.

The cathode (c) of the second light emitting device D2 is used as the fourth voltage input terminal 142 of the pixel circuit 201 in the second sub-pixel 20B and is electrically connected to the second voltage terminal B2 of the first PMIC30_ a. The second voltage terminal B2 of the first PMIC30_ a provides the second power supply voltage V2, i.e., the voltage ELVSS, to the cathode (c) of the second light emitting device D2, thereby achieving the purpose of sharing ELVSS between the first sub-pixel 20a and the second sub-pixel 20B. At this time, the fourth voltage terminal B4 of the second PMIC30_ B is empty.

Alternatively, the cathode (c) of the first light emitting device D1 and the cathode (c) of the second light emitting device D2 are electrically connected to the fourth voltage terminal B4 of the second PMIC30_ B, respectively. The fourth voltage terminal B4 of the second PMIC30_ B provides the second power supply voltage V2, i.e., the voltage ELVSS, to the cathode (c) of the first light emitting device D1 and the cathode (c) of the second light emitting device D2. At this time, the second voltage terminal B2 of the first PMIC30_ a is empty.

It should be noted that, as can be seen from the above description, the pixel circuits 201 of the auxiliary display area 110 and the main display area 120 share the second voltage terminal B2 of the first PMIC30_ a or the fourth voltage terminal B4 of the second PMIC30_ a. In this case, the current sinking capability of the second voltage terminal B2 of the first PMIC30_ a or the fourth voltage terminal B4 of the second PMIC30_ a is the current I provided by the first voltage terminal B1 of the first PMIC30_ a_B1And a third voltage terminal B3 of the second PMIC30_ a provides the current I_B3And (4) summing.

For example, the first voltage terminal B1 of the first PMIC30_ a provides the first power supply voltage V1 of 5.6V to the pixel circuit 201 of the auxiliary display area 110, and provides the current I_B1＝400mA。

The third voltage terminal B3 of the second PMIC30_ a provides a third supply voltage V3 of 4.6V to the pixel circuit 201 of the main display area 120 and provides a current I_B3＝50mA。

In this case, the current sinking capability of the second voltage terminal B2 of the first PMIC30_ a or the fourth voltage terminal B4 of the second PMIC30_ a is greater than or equal to I_B1+I_B3＝400mA+50mA＝450mA。

In summary, in example three and example four, the first power supply voltage V1 is supplied to the pixel circuits 201 of the auxiliary display area 110. The third supply voltage V3 is supplied to the pixel circuits 201 of the main display area 120. Wherein, the first power supply voltage V1 > the third power supply voltage V3.

Thus, when the auxiliary display area 110 and the main display area 120 both display gray-scale images of G255, the pixel circuit 201 of the auxiliary display area 110 can have the actual source voltage V of the first driving transistor M4a under the action of the first power supply voltage V1_sdAs shown in fig. 13C, is located near the saturation point C1 of the characteristic curve S _ 110.

In addition, in the pixel circuit 201 of the main display area 120, at the time of the third power supply voltage V3, the actual source voltage V of the second driving transistor M4b_sdAs shown in fig. 13C, is located near the saturation point C2 of the characteristic curve S _ 120.

In this case, when the display panel 10 displays a screen, the source voltage V of the first driving transistor M4a in the pixel circuit 201 of the auxiliary display area 110 and the second driving transistor M4b in the pixel circuit 201 of the main display area 120_sdAre all near the saturation point. At this time, the first driving transistor M4a and the second driving transistor M4b are just in a fully turned-on state, so that the first driving transistor M4a and the second driving transistor M4b are fully turned on without providing a higher voltage, thereby achieving the purpose of saving power consumption.

Example five

In this example, the first power supply voltage V1 is smaller than the second power supply voltage V2, and the third power supply voltage V3 is also smaller than the second power supply voltage V2. At this time, the second power supply voltage V2 may be the voltage ELVDD. In this case, the pixel circuits 102 of the auxiliary display area 110 and the main display area 120 share the voltage ELVDD.

Wherein the first supply voltage V1 < the third supply voltage V3.

In this case, the display driver circuit 03 includes one PMIC30 as shown in fig. 14 a. The PMIC30 includes a first voltage terminal B1, a second voltage terminal B2, and a third voltage terminal B3.

The first voltage terminal B1 of the PMIC30 serves as the first signal terminal 113 of the display driver 03.

Based on this, as shown in fig. 14a, in the auxiliary display area 110, the first pole (source s) of the first driving transistor M4a is used as the second voltage input terminal 122 of the pixel circuit 201 in the first sub-pixel 20a and electrically connected to the second voltage terminal B2 of the PMIC30, and the second voltage terminal B2 of the PMIC30 is used for providing the second power supply voltage V2, i.e., ELVDD, to the first pole (source s) of the first driving transistor M4a according to the equivalent circuit diagram of the pixel circuit 201 shown in fig. 4.

Further, the second pole (drain s) of the first driving transistor M4a is electrically connected to the anode (a) of the first light emitting device D1.

The cathode (c) of the first light emitting device D1 is used as the first voltage input terminal 112 of the pixel circuit 201 in the first sub-pixel 20a and is electrically connected to the first voltage terminal B1 of the PMIC 30. The first voltage terminal B1 of the PMIC30 is used to provide a first supply voltage V1 to the cathode (c) of the first light emitting device D1.

In addition, as shown in the equivalent circuit diagram of the pixel circuit 201 shown in fig. 4, as shown in fig. 14a, in the main display area 120, the first pole (source s) of the second driving transistor M4B is electrically connected to the second voltage terminal B2 of the PMIC30 as the fourth voltage input terminal 142 of the pixel circuit 201 in the second sub-pixel 20B. The second terminal B of the PMIC30 is used to provide the second supply voltage V2, i.e., ELVDD, to the first pole (source s) of the second driving transistor M4B.

In addition, the second pole of the second driving transistor M4b is electrically connected to the anode (a) of the second light emitting device D2.

The cathode (c) of the second light emitting device D2 is electrically connected to the third voltage terminal B3 of the PMIC30 as the third voltage input terminal 132 of the pixel circuit 201 in the second sub-pixel 20B. The third terminal B of the PMIC30 the cathode (c) of the second light emitting device D2 provides a third supply voltage V3.

Similarly, the current sinking capability of the first voltage terminal B1 of PMIC30 and the third voltage terminal B3 of PMIC30 is greater than the current provided by the second voltage terminal B2 of PMIC 30.

Example six

Wherein the first supply voltage V1 < the third supply voltage V3.

The difference from the fifth example is that the display driving circuit 03 includes two PMICs 30 as shown in fig. 14b, including a first PMIC30_ a and a second PMIC30_ b.

Based on the above, as can be seen from the equivalent circuit diagram of the pixel circuit 201 shown in fig. 4, as shown in fig. 14B, in each pixel circuit 201 of the auxiliary display area 110, the first pole (source s) of the first driving transistor M4a is used as the second voltage input terminal 122 of the pixel circuit 201 in the first sub-pixel 20a and is electrically connected to the second voltage terminal B2 of the first PMIC30_ a.

The second voltage terminal B2 of the first PMIC30_ a provides the second supply voltage V2, i.e., ELVDD described above, to the first pole (source s) of the first drive transistor M4 a.

The cathode (c) of the first light emitting device D1 is used as the first voltage input terminal 112 of the pixel circuit 201 in the first sub-pixel 20a and is electrically connected to the first voltage terminal B1 of the first PMIC30_ a. The first voltage terminal B1 of the first PMIC30_ a provides the first power supply voltage V1 to the cathode (c) of the first light emitting device D1.

Similarly, as shown in fig. 14B, according to the equivalent circuit diagram of the pixel circuit 201 shown in fig. 4, in the main display area 120, the first pole (source s) of the second driving transistor M4B is used as the fourth voltage input terminal 142 of the pixel circuit 201 in the second sub-pixel 20B and is electrically connected to the second voltage terminal B2 of the first PMIC30_ a.

The second voltage terminal B2 of the first PMIC30_ a provides the second supply voltage V2, i.e., ELVDD described above, to the first pole (source s) of the second drive transistor M4B. Thereby achieving the purpose of sharing ELVDD for the first subpixel 20a and the second subpixel 20 b. At this time, the fourth voltage terminal B4 of the second PMIC30_ B is empty.

The cathode (c) of the second light emitting device D2 is electrically connected to the third voltage terminal B3 of the second PMIC30_ B as the third voltage input terminal 132 of the pixel circuit 201 of the second sub-pixel 20B. The third voltage terminal B3 of the second PMIC30_ B provides the above-mentioned third supply voltage V3, i.e., the voltage ELVSS, to the cathode (c) of the second light emitting device D2.

Alternatively, the first pole (source s) of the first driving transistor M4a and the first pole (source s) of the second driving transistor M4B may be electrically connected to the fourth voltage terminal B4 of the second PMIC30_ B. The fourth voltage terminal B4 of the second PMIC30_ B provides the third power supply voltage V3, i.e., the voltage ELVSS, to the first pole (source s) of the first driving transistor M4a and the first pole (source s) of the second driving transistor M4B. At this time, the second voltage terminal B2 of the first PMIC30_ a is empty.

Similarly, the current sinking capability of the first voltage terminal B1 of the first PMIC30_ a and the third voltage terminal B3 of the second PMIC30_ a is greater than the current provided by the second voltage terminal B2 of the first PMIC30_ a or the second voltage terminal B2 of the second PMIC30_ a.

As can be seen from example five and example six, the voltages applied to the cathodes of the respective light emitting devices, e.g., OLEDs, in the auxiliary display area 110 are the same. In the main display area 120, the cathodes of the respective OLEDs need to be applied with the same voltage. In addition, the cathode of any one of the OLEDs in the auxiliary display area 110 is applied with a different voltage from the cathode of any one of the OLEDs in the main display area 120.

In this case, the display screen 10 has a structure as shown in fig. 15, and the display screen 10 includes a cathode layer 300. The cathode layer 300 is disposed in the AA region 100. The cathode layer 300 includes a first electrode block 301 positioned in the auxiliary display area 110, and a second electrode block 302 positioned in the main display area 120.

Here, as shown in fig. 16, the first electrode block 301 serves as the cathode 24 of each OLED in the auxiliary display area 110. The second electrode block 302 serves as a cathode 24 of each OLED in the main display area 120.

In this case, when the PMIC power supply method shown in example five is adopted, as shown in fig. 15, the first electrode block 301 is electrically connected to the first voltage terminal B1 of the PMIC30, so that the first voltage terminal B1 receiving the PMIC30 provides the first power supply voltage V1.

The second electrode block 302 is electrically coupled to the third voltage terminal B3 of the PMIC30 such that the third voltage terminal B3 receiving the PMIC30 provides a third power supply voltage V3.

In order to realize independent power supply of the first electrode block 301 and the second electrode block 302, as shown in fig. 16, a gap H is provided between the first electrode block 301 and the second electrode block 302. When the display screen 10 is manufactured, the size of the gap H can be reduced as much as possible when the manufacturing accuracy allows, so as to avoid that the OLED at the position of the gap H cannot be provided with the cathode 24, and thus the sub-pixel 20 having the OLED cannot perform display.

As shown in fig. 1, the display screen 10 includes a Thin Film Transistor (TFT) backplane 400. The plurality of transistors, i.e., TFTs, in the pixel circuit 201 described above are formed on the TFT backplane 400.

In addition, the display screen 10 further includes a Pixel Definition Layer (PDL) 21 located above the TFT backplane 400, and a plurality of OLEDs.

The pixel definition layer 21 has a plurality of through holes, and each sub-pixel 20 has one through hole therein. The through hole is filled with an anode (anode)22 of the OLED and an organic functional layer 23. The organic functional layer 23 may include a hole injection layer, a hole transport layer, an organic light emitting layer, an electron transport layer, and an electron injection layer in this order in a direction away from the anode 22.

In addition, in the auxiliary display region 110, the cathodes 24 of the OLEDs are connected to each other to form an integrated structure, and the first electrode block 301 is formed. In the main display area 120, the cathodes 24 of the OLEDs are connected to each other to form the second electrode block 302.

Example two

In this embodiment, the mobile terminal 01 having the display screen 10, for example, a mobile phone, may be divided into at least two display sub-areas.

As shown in fig. 17, the AA area 100 of the display screen 10 may be divided into a display sub-area a, a display sub-area B, and a display sub-area C.

In some embodiments of the present application, the display sub-area C may be bent to the back (i.e. non-display side) of the display screen 10 as shown in fig. 18 a. At this time, as shown in fig. 18B, the user only needs to view the images displayed in the display sub-area a and the display sub-area B.

In this case, since the user does not need to look at the display sub-area C, the display luminance of the display sub-area C, that is, the light emission luminance of the OLED in each pixel circuit 20 in the display sub-area C, can be reduced.

Alternatively, as shown in fig. 19, when the display sub-area a is bent to the back of the display screen 10, the light emission luminance of the OLED in each pixel circuit 20 in the display sub-area a can be reduced.

Still alternatively, as shown in fig. 20, when the display sub-area a and the display sub-area C are both bent to the back of the display screen 10, the light emitting luminance of the OLED in each pixel circuit 20 in the display sub-area a and the display sub-area C can be reduced.

Therefore, the brightness of the display subarea which is not needed to be watched by a user is reduced by controlling the subarea brightness of each display subarea, and the purpose of saving power consumption is achieved.

Based on this, in order to control the brightness of each display sub-area in the display screen 10, as shown in fig. 21a, the display screen 10 includes at least one PMIC30 and a processor 31 electrically connected to the PMIC 30. Fig. 21a illustrates an example in which the display panel 10 includes one PMIC 30.

As shown in fig. 21a, the effective display area 100 has 1080 rows of sub-pixels 20 along the horizontal direction X and 1920 columns of sub-pixels along the vertical direction Y.

In this case, the display sub-area a includes the 1 st to 640 th columns of sub-pixels 20 in the vertical direction Y. The display sub-area B includes 641 th to 1280 th columns of sub-pixels 20 in the vertical direction Y. The display sub-area C includes the 1281 st to 1920 th columns of sub-pixels 20 in the vertical direction Y.

Each of the display sub-area a, the display sub-area B, and the display sub-area C has 1080 rows of sub-pixels in the horizontal direction X. For convenience of description, the sub-pixels in the display sub-area a are referred to as first sub-pixels 20a, and a plurality of first sub-pixels 20a constitute a first pixel array, as shown in fig. 21 b; the sub-pixels in the display sub-area B are referred to as second sub-pixels 20B, and a plurality of the second sub-pixels 20B constitute a second sub-pixel array; the sub-pixels in the display sub-area C are referred to as a third sub-pixel 20C, and a plurality of the third sub-pixels 20C constitute a third sub-pixel array.

The PMIC30 has a first voltage terminal B1, a second voltage terminal B2, a third voltage terminal B3, and a fourth voltage terminal B4.

As shown in fig. 21B, in the display sub-area a, in each pixel circuit 201, the first driving transistor M4a is electrically connected to the first voltage terminal B1 of the PMIC 30.

The first voltage terminal B1 of the PMIC30 is used for individually providing the first power supply voltage V1 to each pixel circuit 201 in the display subarea a.

In the sub-area B, the second driving transistor M4B is electrically connected to the third voltage terminal B3 of the PMIC30 in each pixel circuit 201.

The third voltage terminal B2 of the PMIC30 is used for individually providing the third supply voltage V3 to each pixel circuit 201 in the display sub-area B.

In the sub-area C, in each pixel circuit 201, the third driving transistor M4C is electrically connected to the fourth voltage terminal B4 of the PMIC 30.

The fourth voltage terminal B4 of the PMIC30 is used for individually providing the fourth power supply voltage V4 to each pixel circuit 201 in the display sub-area C.

In addition, the cathode (C) of the first light emitting device D1 in the display sub-area a, the second light emitting device D2 in the display sub-area B, and the third light emitting device D3 in the display sub-area C are electrically connected to the fourth voltage terminal B4 of the PMIC 30.

The second voltage terminal B2 of the PMIC30 is used for simultaneously providing the second power supply voltage V2, i.e., ELVSS, to the first light emitting device D1 in the display sub-area a, the second light emitting device D2 in the display sub-area B, and the cathode (C) of the first light emitting device D1 in the display sub-area C. Therefore, the pixel circuit common voltage ELVSS of the display sub-area a, the display sub-area B, and the display sub-area C can be realized.

The first supply voltage V1, the third supply voltage V3, and the fourth supply voltage V4 have different voltage values. And, V1 > V2; v3 > V2; v4 > V2.

As described above, the current sinking capability of the second voltage terminal B2 of the PMIC30 is greater than or equal to the sum of the output currents of the first voltage terminal B1 of the PMIC30, the third voltage terminal B3 of the PMIC30 and the fourth voltage terminal B4 of the PMIC 30.

In addition, the display panel 01 further includes a substrate board based on the structure of fig. 21 b. The first pixel array in the display sub-area a, the second pixel array in the display sub-area B, and the third pixel array in the display sub-area C are disposed on the substrate. Further, the material constituting the above-described base substrate includes a flexible resin material.

Based on this, the present application provides a control method of a mobile terminal having a display screen shown in fig. 21b, including:

first, the display driver 03 detects that the display sub-area a having the first sub-pixel array is bent to the non-display side of the display panel 01.

Specifically, the display driver 03 includes a processor 31 connected to the PMIC30 as shown in fig. 21 a. The processor 31 is configured to detect whether each display sub-area is bent to the back of the display screen 10, and send a brightness control signal to the PMIC30 according to the detection result.

Next, the method further includes: the first signal terminal 113 of the display driver 03, i.e. the first voltage terminal B1 of the PMIC30, reduces the first supply voltage V1 input to the first voltage input terminal 112 (i.e. the first pole of the first driving transistor M4 a) of the pixel circuit of the first sub-pixel 20a in the display sub-area a having the first sub-pixel array.

Alternatively, the second signal terminal 123 of the display driver 03, i.e., the second voltage terminal B2 of the PMIC30, increases the second power supply voltage V2 input to the second voltage input terminal 122 of the pixel circuit of the first sub-pixel 20a (i.e., the cathode of the first light emitting device D1), so that the light emitting luminance of the first sub-pixel 20a decreases.

Specifically, when the processor 31 detects that the display sub-area a having the first sub-pixel array is bent to the back of the display screen 10, the processor sends a brightness control signal to the PMIC 30. The PMIC30 may decrease the first supply voltage V1 input to the first voltage terminal B1 of the PMIC30 or increase the first supply voltage V1 input to the second voltage terminal B2 of the PMIC30 according to the brightness control signal. Thereby causing the light emission luminance of the display sub-area a to decrease.

The above description is given by taking the example that the display sub-region a is bent to the back of the display screen 10, and when the processor 31 detects that other display sub-regions are bent to the back of the display screen 10, the same manner can be obtained for the brightness of other display sub-regions being reduced, and details are not repeated here.

On this basis, in order to enable the processor 31 to detect whether the respective display subarea is bent to the back of the display screen 10. In some embodiments of the present application, a voltage variable resistor (not shown) may be disposed on the flexible substrate of the display screen 10 at the interface between two adjacent display sub-regions, for example, the display sub-region B and the display sub-region C.

The voltage-variable resistor is connected with the processor 31, and when the display subarea a is bent to the back of the display screen 10, the voltage-variable resistor changes its resistance under pressure, and the processor 31 can send a brightness control signal to the PMIC30 according to the detected change of the resistance of the voltage-variable resistor.

Alternatively, in other embodiments of the present application, in order to control the brightness of each display sub-area in the display screen 10, the display screen 10 includes three PMICs, such as a first PMIC30_ a, a second PMIC30_ b and a third PMIC30_ c, as shown in fig. 22 a. In addition, the display panel 10 further includes a processor 31 electrically connected to the three PMICs.

The first PMIC30_ a has a first voltage terminal B1 and a second voltage terminal B2.

The second PMIC30_ B has a third voltage terminal B3 and a fourth voltage terminal B4.

The third PMIC30_ c has a fifth voltage terminal B5 and a sixth voltage terminal B6.

As shown in fig. 22B, in the display sub-area a, in each pixel circuit 201, the first pole (source s) of the first driving transistor M4a is electrically connected to the first voltage terminal B1 of the first PMIC30_ a.

The first voltage terminal B1 of the first PMIC30_ a is used for individually providing the first power supply voltage V1 to each pixel circuit 201 in the display sub-area a.

In the sub-area B, in each pixel circuit 201, the first electrode (source s) of the second driving transistor M4B is electrically connected to the third voltage terminal B3 of the second PMIC30_ B.

The third voltage terminal B3 of the second PMIC30_ B is used for individually providing the third power supply voltage V3 to each pixel circuit 201 in the display sub-area B.

In the sub-area C, in each pixel circuit 201, the first electrode (source s) of the third driving transistor M4C is electrically connected to the fifth voltage terminal B5 of the third PMIC30_ C.

The fifth voltage terminal B5 of the third PMIC30_ C is used for individually providing the fifth power supply voltage V5 to each pixel circuit 201 in the display sub-area C.

In addition, the cathode (C) of the first light emitting device D1 in the display sub area a, the cathode (C) of the second light emitting device D2 in the display sub area B, and the cathode (C) of the third light emitting device D3 in the display sub area C are electrically connected to the second voltage terminal B2 of the first PMIC30_ a, respectively. At this time, the fourth voltage terminal B4 of the second PMIC30_ B and the sixth voltage terminal B6 of the third PMIC30_ c are empty.

The second voltage terminal B2 of the first PMIC30_ a is used for simultaneously providing the second power supply voltage V2, i.e., the voltage ELVSS, to the cathodes of the light emitting devices in the pixel circuits 201 in the display sub-area a, the display sub-area B, and the display sub-area C. Thereby making the voltage ELVSS common to the respective pixel circuits 201 in the display sub-area a, the display sub-area B, and the display sub-area C described above.

The first supply voltage V1, the third supply voltage V3, and the fifth supply voltage V5 have different voltage values. And, V1 > V2; v3 > V2; v5 > V2.

As described above, the current sinking capability of the second voltage terminal B2 of the first PMIC30_ a is equal to or greater than the sum of the output currents of the first voltage terminal B1 of the first PMIC30_ a, the third voltage terminal B3 of the second PMIC30_ B and the fifth voltage terminal B5 of the third PMIC30_ c.

Alternatively, in other embodiments of the present application, the cathode (C) of the first light emitting device D1 in the pixel circuit of the display sub-area a, the cathode (C) of the second light emitting device D2 in the pixel circuit of the display sub-area B, and the cathode (C) of the third light emitting device D3 in the pixel circuit of the display sub-area C are electrically connected to the fourth voltage terminal B4 of the second PMIC30_ B or the sixth voltage terminal B6 of the third PMIC30_ C, respectively.

At this time, the fourth voltage terminal B4, or the sixth voltage terminal B6 of the third PMIC30_ C, is used to simultaneously supply the above voltage ELVSS to the cathodes of the light emitting devices in the respective pixel circuits 201 in the display sub-area a, the display sub-area B, and the display sub-area C.

In this case, the processor 31 detects whether each display sub-area is bent to the back of the display screen 10. When detecting that a display sub-area, for example, the display sub-area C is folded to the back of the display screen 10, the processor 31 sends the brightness control signal to the third PMIC30_ C.

The third PMIC30_ c reduces a fifth supply voltage V5 output by a fifth voltage terminal B5 of the third PMIC30_ c according to the brightness control signal. Thereby causing the light emission luminance of the display sub-region C to decrease.

The above description is given by taking the example that the display sub-region C is bent to the back of the display screen 10, and when the processor 31 detects that other display sub-regions C are bent to the back of the display screen 10, the same manner can be obtained for the brightness of other display sub-regions being reduced, and the description thereof is omitted here.

It should be noted that the above description is made by taking as an example that the pixel circuits 201 in the display sub-area a, the display sub-area B, and the display sub-area C receive the same voltage ELVSS, and the luminance of each display sub-area is controlled independently. Of course, in order to realize independent brightness control of each display sub-region, the pixel circuits 201 of each display sub-region may also have the same voltage ELVDD. In this case, the PMIC and the arrangement of the cathode layer 300 in the display panel 10 are the same as those in the first embodiment, and are not described herein again.

EXAMPLE III

As shown in fig. 23, the AA area 100 of the display screen 10 may be divided into a display sub-area a and a display sub-area B. The display sub-area a and the display sub-area B display different contents.

For example, in some embodiments of the present disclosure, display sub-region B plays a movie.

When the mobile terminal 01 receives the dialogue information, for example, the WeChat content, the dialogue information displayed in the sub-area A is displayed. When the mobile terminal 01 does not receive the dialogue information, the display sub-area a and the display sub-area B display the same screen together.

In this case, the display sub-area B of the movie is usually played, and its light emission luminance is dark. The display sub-area a displaying the dialog information emits light brightly. The dialog information displayed in the display sub-area a is too dazzling, thereby reducing the viewing effect of the user. In this case, the brightness of the display sub-area a and the brightness of the display sub-area B need to be controlled separately to reduce the brightness of the display sub-area a.

Based on this, in order to control the brightness of each display sub-area in the display panel 10, as shown in fig. 24, the display panel 10 includes at least one PMIC30 and a processor 31 electrically connected to the PMIC 30. Fig. 24 illustrates an example in which the display panel 10 includes one PMIC 30.

As shown in fig. 24, the effective display area 100 has 1920 rows of sub-pixels 20 in the horizontal direction X and 1080 columns of sub-pixels in the vertical direction Y.

In this case, the display sub-area a includes the 1 st to 640 th rows of sub-pixels 20 in the horizontal direction X. The display sub-area B includes 641 th to 1920 th rows of sub-pixels 20 in the horizontal direction.

The display sub-area A and the display sub-area B both have 1080 columns of sub-pixels in the vertical direction and the horizontal direction Y.

The PMIC30 has a first voltage terminal B1, a second voltage terminal B2, and a third voltage terminal B3.

In the same manner as the second embodiment, in the display sub-area a, in each pixel circuit 201, the first electrode (source s) of the first driving transistor M4a is electrically connected to the first voltage terminal B1 of the PMIC 30.

In the sub-area B, in each pixel circuit 201, the first electrode (source s) of the second driving transistor M4a is electrically connected to the second voltage terminal B2 of the PMIC 30.

The third voltage terminal B3 of the PMIC30 is used for individually providing the third supply voltage V3 to each pixel circuit 201 in the display sub-area B.

In addition, the cathode (c) of the first light emitting device D1 in the pixel circuit 201 of the display sub-area a and the cathode (c) of the second light emitting device D2 in the pixel circuit 201 of the display sub-area B are electrically connected to the second voltage terminal B2 of the PMIC30, respectively.

The second voltage terminal B2 of the PMIC30 is used for providing the second power supply voltage V2, i.e., the voltage ELVSS, to each pixel circuit 201 in the display sub-area a and the display sub-area B simultaneously.

The first supply voltage V1 and the third supply voltage V3 have different voltage values, and V1 is greater than V2; v3 > V2.

In addition, when the display screen has two PMICs, the two PMICs are respectively used for providing different first power supply voltage V1 and third power supply voltage V3 to the display subarea a and the display subarea B. The arrangement of the two PMICs is the same as the principle of the second embodiment, and is not described herein again.

On this basis, as shown in fig. 24, the processor 31 is electrically connected to the PMIC. When the processor 31 detects that the display sub-area a displays dialogue information and the display sub-area B plays a movie, a brightness control signal is sent to the PMIC 30.

The PMIC30 may reduce the first supply voltage V1 output by the first voltage terminal B1 of the PMIC30 according to the brightness control signal. Thereby causing the light emission luminance of the display sub-area a to decrease. The problem that the display effect is influenced by too dazzling of the dialog information displayed in the display sub-area A is avoided.

Alternatively, in other embodiments of the present application, display sub-area B displays a background image.

When the mobile terminal 01 receives the dialogue information, the dialogue information displayed in the sub-area a is displayed. When the mobile terminal 01 does not receive the dialogue information, the display sub-area a and the display sub-area B display the same screen together.

In this case, if the display sub-area B of the background image is displayed, the light emission luminance is equivalent to that of the display sub-area a displaying the dialogue information. It may result in the user easily ignoring important information. In this case, the brightness of the display sub-area a and the brightness of the display sub-area B need to be controlled separately to increase the brightness of the display sub-area a.

Based on this, when the processor 31 detects that the display subarea a displays dialogue information and the display subarea B displays a background image, a brightness control signal is sent to the PMIC 30.

The PMIC30 may increase the first supply voltage V1 output from the first voltage terminal B1 of the PMIC30 according to the brightness control signal. Thereby causing the light emission luminance of the display sub-area a to be improved. The dialog information to be displayed avoiding the display sub-area a is ignored.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A display screen is characterized by comprising a display driver, a first pixel array and a second pixel array; wherein:

the display driver comprises a first signal end, a second signal end and a third signal end;

the first pixel array comprises a plurality of first sub-pixels, and pixel circuits in the first sub-pixels comprise a first voltage input end and a second voltage input end;

the second pixel array comprises a plurality of second sub-pixels, and pixel circuits in the second sub-pixels comprise third voltage input ends and fourth voltage input ends;

a first voltage input end of a pixel circuit of the first sub-pixel is electrically connected with a first signal end of the display driver and receives a first power supply voltage output by the first signal end, and a second voltage input end of the pixel circuit of the first sub-pixel is electrically connected with a second signal end of the display driver and receives a second power supply voltage output by the second signal end;

a third voltage input end of the pixel circuit of the second sub-pixel is electrically connected with a third signal end of the display driver and receives a third power supply voltage output by the third signal end, and a fourth voltage input end of the pixel circuit of the second sub-pixel is electrically connected with a second signal end of the display driver and receives a second power supply voltage output by the second signal end;

wherein the third supply voltage is different in voltage value from the first supply voltage.

2. The display screen of claim 1, wherein the first supply voltage output by the first signal terminal of the display driver is greater than the second supply voltage output by the second signal terminal of the display driver;

and the third power supply voltage output by the third signal end of the display driver is greater than the second power supply voltage output by the second signal end of the display driver.

3. The display screen of claim 2, wherein the pixel circuit of the first sub-pixel in the first pixel array comprises a first drive transistor and a first light emitting device; a first electrode of the first driving transistor is electrically connected with a first signal end of the display driver, and a second electrode of the first driving transistor is electrically connected with an anode of the first light-emitting device; the cathode of the first light-emitting device is electrically connected with a second signal end of the display driver;

the second pixel array comprises a plurality of second sub-pixels, and pixel circuits in the second sub-pixels comprise second driving transistors and second light-emitting devices;

a first electrode of the second driving transistor is electrically connected with a third signal end of the display driver, and a second electrode of the second driving transistor is electrically connected with an anode of the second light-emitting device; and the cathode of the second light-emitting device is electrically connected with a second signal end of the display driver.

4. The display screen of claim 1, wherein the first supply voltage output by the first signal terminal of the display driver is less than the second supply voltage output by the second signal terminal of the display driver;

and the third power supply voltage output by the third signal end of the display driver is less than the second power supply voltage output by the second signal end of the display driver.

5. The display screen of claim 4, wherein the pixel circuit of the first sub-pixel in the first pixel array comprises a first drive transistor and a first light emitting device;

a first electrode of the first driving transistor is electrically connected with a second signal end of the display driver, and a second electrode of the first driving transistor is electrically connected with an anode of the first light-emitting device; the cathode of the first light-emitting device is electrically connected with a first signal end of the display driver;

a first electrode of the second driving transistor is electrically connected with a second signal end of the display driver, and a second electrode of the second driving transistor is electrically connected with an anode of the second light-emitting device; and the cathode of the second light-emitting device is electrically connected with a third signal end of the display driver.

6. A display screen in accordance with claim 1, wherein the display driver comprises a power management integrated circuit; the power management integrated circuit comprises a first voltage end, a second voltage end and a third voltage end;

a first voltage terminal of the power management integrated circuit is electrically connected with a first voltage input terminal of the pixel circuit of the first sub-pixel;

a second output terminal of the power management integrated circuit is electrically connected to a second voltage input terminal of the pixel circuit of the first subpixel and a fourth voltage input terminal of the pixel circuit of the second subpixel;

a third output terminal of the power management integrated circuit is electrically connected to a third voltage input terminal of the pixel circuit of the second subpixel.

7. The display screen of claim 1, wherein the display driver comprises a first power management integrated circuit and a second power management integrated circuit;

the first power management integrated circuit comprises a first voltage terminal and a second voltage terminal;

the second power management integrated circuit comprises a third voltage terminal and a fourth voltage terminal;

a first voltage terminal of the first power management integrated circuit is electrically connected with a first voltage input terminal of the pixel circuit of the first sub-pixel;

a third voltage terminal of the second power management integrated circuit is electrically connected with a third voltage input terminal of the pixel circuit of the second sub-pixel;

the second voltage terminal of the first power management integrated circuit is electrically connected with the second voltage input terminal of the pixel circuit of the first sub-pixel and the fourth voltage input terminal of the pixel circuit of the second sub-pixel;

alternatively, the fourth voltage terminal of the second power management integrated circuit is electrically connected to the second voltage input terminal of the pixel circuit of the first sub-pixel and the fourth voltage input terminal of the pixel circuit of the second sub-pixel.

8. A display screen according to any one of claims 1 to 7,

the effective display area comprises an auxiliary display area and a main display area; the non-display side of the auxiliary display area is used for integrating a camera or a sensor;

wherein the first pixel array is located in the auxiliary display area; the second pixel array is positioned in the main display area;

the pixel density of the auxiliary display area is less than that of the main display area.

9. The display screen of claim 7, wherein the pixel circuit of the first sub-pixel occupies the same light-shielding area as the pixel circuit of the second sub-pixel;

the light transmission area of the first sub-pixel except the pixel circuit is larger than that of the second sub-pixel except the pixel circuit.

10. Display screen according to claim 6 or 7,

the display screen also comprises a substrate base plate; the first pixel array and the second pixel array are arranged on the substrate base plate;

wherein a material constituting the substrate base plate includes a flexible resin material;

the display driving circuit further comprises a processor, the processor is electrically connected with at least one power management integrated circuit, and the processor is used for outputting a brightness control signal to at least one power management integrated circuit when detecting that the first pixel array or the second pixel array is bent to the non-display side of the display screen.

11. A mobile terminal, characterized in that it comprises a display screen according to any one of claims 1-10;

the mobile terminal also comprises a camera and a sensor; the camera, and/or the sensor, is located on a non-display side of the display screen.

12. The mobile terminal of claim 11, wherein the display comprises a secondary display area and a primary display area; the pixel density of the auxiliary display area is less than that of the main display area;

the camera and the sensor are arranged on the non-display side of the auxiliary display area.

13. The mobile terminal of claim 11, wherein the display screen has an opening disposed thereon; the display screen comprises auxiliary display areas positioned at two sides of the opening and a main display area positioned below the opening;

wherein the pixel density of the auxiliary display area is less than the pixel density of the main display area;

the camera is positioned in the opening; the sensor is arranged on the non-display side of the auxiliary display area.

14. A control method of a mobile terminal is characterized in that the mobile terminal comprises a display screen; the display screen comprises a display driver, a first pixel array and a second pixel array; wherein: the display driver comprises a first signal end, a second signal end and a third signal end; the first pixel array comprises a plurality of first sub-pixels, and pixel circuits in the first sub-pixels comprise a first voltage input end and a second voltage input end; the second pixel array comprises a plurality of second sub-pixels, and pixel circuits in the second sub-pixels comprise third voltage input ends and fourth voltage input ends; a first voltage input end of the pixel circuit of the first sub-pixel is electrically connected with a first signal end of the display driver, and a second voltage input end of the pixel circuit of the first sub-pixel is electrically connected with a second signal end of the display driver; a third voltage input end of the pixel circuit of the second sub-pixel is electrically connected with a third signal end of the display driver, and a fourth voltage input end of the pixel circuit of the second sub-pixel is electrically connected with a second signal end of the display driver;

the display screen also comprises a substrate base plate; the first pixel array and the second pixel array are arranged on the substrate base plate; the material constituting the substrate base plate includes a flexible resin material;

the control method of the mobile terminal comprises the following steps:

the display driver detects that the first sub-pixel array is bent to the non-display side of the display screen;

a first signal end of the display driver reduces a first power supply voltage input to a first voltage input end of a pixel circuit of a first sub-pixel in a first sub-pixel array; or the second signal terminal of the display driver increases a second supply voltage output to the second voltage input terminal of the pixel circuit of the first sub-pixel, and the light-emitting brightness of the first sub-pixel is reduced;

wherein the first supply voltage is greater than the second supply voltage.