CN111366898B - Coherent radar wide pulse waveform generation method and device - Google Patents

Abstract

The invention relates to a coherent radar wide pulse waveform generation method and a coherent radar wide pulse waveform generation device, wherein the method comprises the following steps: receiving the transmitted waveform data by a front stage FIFO; storing the waveform data into a DDR through a DDR MIG core by utilizing the read-write control of the pre-stage FIFO; controlling a DDR MIG core to pre-read waveform data from the DDR by utilizing a rear-stage FIFO programmable full signal; when an internal trigger signal generated according to a radar starting instruction is detected, the rear-stage FIFO outputs waveform data to the digital-to-analog conversion interface to generate an analog signal, and waveform output is realized. The method is used for generating the coherent radar wide pulse waveform, can greatly release the resources in the chip, is flexible to apply, and can ensure the coherence and the continuity of the radar transmitting waveform.

Description

Coherent radar wide pulse waveform generation method and device

Technical Field

The invention relates to the technical field of radar signal processing, in particular to a coherent radar wide pulse waveform generation method and device.

Background

The existing dynamic target scattering measurement system has the capabilities of target searching, tracking and measuring, and can realize the tracking of a moving target and the acquisition of characteristic measurement data. The measuring system needs to have coherent pulse waveform transmitting capacity, has various waveform types and larger pulse width, and can adaptively replace the waveform in real time according to target position information in the working process. According to the requirements, various waveforms need to be generated and then stored in a cache, and the transmitted waveform address is changed in real time according to the mode and parameter information in the working process, so that the purpose of switching the waveforms is achieved. The conventional method is to store the waveform file into an internal RAM (random access memory) of an FPGA (field programmable gate array), the real-time performance is high, and the time delay is fixed, but the storage capacity of various wide pulse waveforms is large, so that the problems of large resource occupation, insufficient logic resources, short time sequence and the like can be caused when the on-chip resources are used, the signal processing and the time sequence control can be influenced, and the conditions of unstable time sequence and the like can be caused.

Therefore, in view of the above disadvantages, it is desirable to provide a method and apparatus for producing coherent radar wide pulse waveform with less on-chip resource consumption.

Disclosure of Invention

The invention aims to solve the technical problems that in the prior art, the storage capacity of a wide pulse waveform is large, so that the on-chip resources are occupied greatly, the logic resources are insufficient, the time sequence is short, the signal processing and the time sequence control are influenced, and the time sequence is unstable.

In order to solve the above technical problem, the present invention provides a coherent radar wide pulse waveform generation method, including:

receiving the transmitted waveform data by a front stage FIFO;

storing the waveform data into a DDR through a DDR MIG core by utilizing the read-write control of the pre-stage FIFO;

controlling a DDR MIG core to pre-read waveform data from the DDR by utilizing a rear-stage FIFO programmable full signal;

when an internal trigger signal generated according to a radar starting instruction is detected, the rear-stage FIFO outputs waveform data to the digital-to-analog conversion interface to generate an analog signal, and waveform output is realized.

Preferably, whether the front stage FIFO generates a non-empty signal is detected, if so, the front stage FIFO data is written into the DDR when the DDR MIG core write ready signal is pulled high; and in the writing process, accumulating the waveform data volume written into the DDR, and jumping to a waiting state when the waveform data volume is accumulated to the issued waveform data volume.

Preferably, the step of controlling the DDR MIG core to pre-read waveform data from the DDR by using the post-stage FIFO programmable full signal specifically includes:

in a waiting state, when detecting that a programmable full signal of the rear-stage FIFO is low, writing DDR data into the rear-stage FIFO;

and when the data volume of the rear-stage FIFO is detected to be larger than a set threshold value, pulling up a programmable full signal of the rear-stage FIFO, interrupting the DDR data reading operation, and pulling up a waiting ready signal.

Preferably, the step of outputting the waveform data to the digital-to-analog conversion interface by the back stage FIFO specifically includes:

when waiting for the ready signal to be pulled up, detecting whether an internal trigger signal generated according to a radar starting instruction is received, if so, skipping to a reading state, and controlling the continuous output of the rear-stage FIFO data to a digital-to-analog conversion interface; when the data volume of the rear-stage FIFO is detected to be smaller than a set threshold value, a programmable full signal of the rear-stage FIFO is pulled down, and DDR data is continuously written into the rear-stage FIFO; and when detecting that the accumulated amount of the read data is equal to the number of points corresponding to the waveform pulse width, skipping to a waiting state after the reading is finished, and resetting the rear-stage FIFO and the DDR read address.

Preferably, the method further comprises:

waveform data are generated through simulation and stored in a waveform file, and then the waveform file is issued to the front stage FIFO through an upper computer software via a PCI interface.

The invention also provides a coherent radar wide pulse waveform generation device, which comprises: the system comprises an integration module, an interface module, a read-write state machine and a radar time sequence state machine;

the interface module comprises a PCI interface and a digital-to-analog conversion interface;

the integrated module includes: a front-stage FIFO, a rear-stage FIFO, a DDR and a DDR MIG core; the input end of the front stage FIFO is connected with the PCI interface and is used for receiving the issued waveform data; the output end of the rear-stage FIFO is connected with the digital-to-analog conversion interface and used for outputting waveform data; the DDR MIG core is connected to the DDR to read and write data;

the radar time sequence state machine is used for generating an internal trigger signal according to a received radar starting instruction and a set period; the read-write state machine is connected with the radar time sequence state machine and a front-stage FIFO, a rear-stage FIFO and a DDR MIG core of the integrated module, and is used for storing waveform data written into the front-stage FIFO into a DDR through the DDR MIG core and controlling the DDR MIG core to pre-read the waveform data from the DDR through a rear-stage FIFO programmable full signal; and the read-write state machine is also used for controlling the back-stage FIFO to output waveform data to the digital-to-analog conversion interface after detecting the internal trigger signal, generating an analog signal and realizing waveform output. Preferably, the read-write state machine is further configured to detect whether the pre-stage FIFO generates a non-empty signal, and if so, write data of the pre-stage FIFO into the DDR when a write ready signal of the DDR MIG core is pulled high; and the read-write state machine is also used for accumulating the waveform data volume written into the DDR, and jumping to a waiting state when the waveform data volume is accumulated to the issued waveform data volume.

Preferably, the read-write state machine is further configured to, in the wait state, write DDR data into the back-stage FIFO by detecting that a programmable full signal of the back-stage FIFO is low; and the read-write state machine is also used for interrupting the DDR data read operation and pulling up a waiting ready signal when detecting that the data volume of the rear-stage FIFO is greater than a set threshold value and the programmable full signal of the rear-stage FIFO is pulled up.

Preferably, the read-write state machine is further configured to detect whether an internal trigger signal generated according to a radar start instruction is received when the ready signal is pulled high, and if so, skip to a read state to control the subsequent FIFO data to be continuously output to the digital-to-analog conversion interface; the read-write state machine is also used for controlling the programmable full signal of the rear-stage FIFO to be pulled down and continuously writing the DDR data into the rear-stage FIFO when the data volume of the rear-stage FIFO is detected to be smaller than a set threshold value; and the read-write state machine is also used for jumping to a waiting state after the reading is finished and resetting the rear-stage FIFO and the DDR read address when the accumulated quantity of the read data is detected to be equal to the number of points corresponding to the waveform pulse width.

Preferably, the apparatus further comprises:

and the simulation calculator is used for generating waveform data through simulation and then sending the waveform data to the front stage FIFO through the PCI interface through upper computer software.

The coherent radar wide pulse waveform generation method and the coherent radar wide pulse waveform generation device have the following beneficial effects:

1. the method is used for generating the coherent radar wide pulse waveform, can greatly release the resources in the chip, can improve the flexibility of generating the radar waveform, and can ensure that the radar can adaptively switch the waveform according to different modes in the working process;

2. the method can be applied to a multi-waveform and wide-pulse measurement radar system, realizes the phase consistency of radar emission waveforms through a DDR and later stage FIFO matching mechanism, and ensures the waveform coherence;

3. according to the invention, when the waveform file is input into the DDR, the DDR is read at the same time, part of waveform data is stored in the rear-stage FIFO and read from the rear-stage FIFO when being read, and when the data amount in the rear-stage FIFO is smaller than the threshold value, the waveform data is read from the DDR and then written into the rear-stage FIFO.

Drawings

Fig. 1 is a schematic structural diagram of a coherent radar wide pulse waveform generation apparatus according to a first embodiment of the present invention;

fig. 2 is a flowchart of a coherent radar wide pulse waveform generation method according to a second embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.

Example one

As shown in fig. 1, a schematic structural diagram of a coherent radar wide pulse waveform generating device according to an embodiment of the present invention includes: an interface module, an integration module 200, a read-write state machine 300, and a radar timing state machine 400.

The interface module includes a digital-to-analog conversion interface 110 and a PCI interface 120.

The integrated module 200 includes: a front stage FIFO (first in first out queue) 210, a back stage FIFO220, a DDR (double data Rate synchronous dynamic random Access memory) 230, and a DDR MIG core 240. In the integrated module 200, an input end of the front stage FIFO210 is connected to the PCI interface 120 for receiving the transmitted waveform data, and an output end of the front stage FIFO210 is connected to the read/write state machine 300 for outputting the waveform data to the read/write state machine 300 in a write state. The input end of the back stage FIFO220 is connected to the read/write state machine 300, and receives the waveform data from the read/write state machine 300 in the read state, and the output end of the back stage FIFO220 is connected to the digital-to-analog conversion interface 110, and is used for generating an analog signal and outputting a waveform. The DDR MIG core 240 receives waveform data to be written from the read-write state machine 300 in a write state and transmits the waveform data to the DDR particles; in the read state, the waveform data from the DDR grains is received and transmitted to the read/write state machine 300, completing the data interaction with the read/write state machine 300.

The dac interface 110 in the interface module 100 receives the waveform data from the back-stage FIFO220, assigns the waveform data to a dac chip, and generates an analog signal to output the waveform.

The apparatus may further include a simulation calculator for generating waveform data through simulation, and then issuing the waveform data to the front stage FIFO210 through the PCI interface 120 by the upper computer software.

The radar timing state machine 400 generates an internal trigger signal according to a set period according to a radar start command, and is connected to the read/write state machine 300. When the radar timing state machine 400 receives the radar stop instruction and the read/write state machine 300 is in the wait state, the internal trigger signal is stopped, and the read/write state machine 300 jumps to the idle state.

The read/write state machine 300 is used to implement timing control and data interaction functions. The read/write state machine 300 is in an idle state after power-on reset, and when the upper computer software sends a waveform data downloading instruction, the waveform data is transmitted to the PCI interface 120 through the PCI bus, and is input into the front stage FIFO210 after being analyzed. When the front stage FIFO210 writes waveform data, the non-empty signal of the front stage FIFO210 will be pulled high, and the read/write state machine 300 enters a write state according to the non-empty signal. In the write state, when the write ready signal of the DDR MIG core 240 is pulled high and the front stage FIFO210 is not pulled high, the front stage FIFO210 read enable is pulled high and the waveform data in the front stage FIFO210 is assigned to the input terminal of the DDR MIG core 240 by the read/write state machine 300 and then transmitted to the DDR 230.

In the writing process, the data amount written into the DDR230 is recorded by the write counter, the write counter accumulates every time one data is written, and when the data amount is accumulated to the lower waveform data amount, the write completion indication signal is generated, and the read/write state machine 300 jumps to the waiting state. The wait state indicates that the writing of the waveform data is completed and the reading can be performed.

In order to ensure that the waveform data can be read out quickly and continuously, a part of the waveform data needs to be buffered in the subsequent stage FIFO220 before the read state starts. The DDR MIG core 240 is controlled by a programmable full signal of the rear-stage FIFO220 for buffering part of waveform data, the rear-stage FIFO220 is pulled low by an empty programmable full signal in a waiting state, the DDR230 is controlled by the read-write state machine 300 to perform pre-reading, and the waveform data from the DDR MIG core 240 is written into the rear-stage FIFO 220. With the continuous writing of the waveform data, when the data amount in the back stage FIFO220 is greater than the set threshold, the back stage FIFO220 may be programmed to be full signal pulled high, the read/write state machine 300 jumps to a waiting state, interrupts the waveform data reading operation, and waits for the ready signal to be pulled high, and may enter a reading state under the control of the radar timing state machine 400.

When the wait ready signal is pulled high and the internal trigger signal is pulled high, the read/write state machine jumps to the read state. After the read state starts, the read/write state machine controls the read enable of the back stage FIFO220 to be pulled high, and the waveform data in the back stage FIFO220 is output to the digital-to-analog conversion interface 110 to generate an analog signal, so that the waveform output is realized. With the reduction of the waveform data in the rear-stage FIFO220, when the data volume of the rear-stage FIFO220 is smaller than the set threshold, the programmable full signal is pulled down, the read-write state machine controls the DDR230 to read the waveform data, the DDR230 addresses are accumulated continuously, the data volume of the rear-stage FIFO220 is supplemented, and the feedback mechanism can maintain the data volume of the rear-stage FIFO220 to be constant, so that the waveform continuity is ensured.

During the reading process, the data reading counter is accumulated every time one data reading counter is read, when the number of points corresponding to the waveform pulse width is accumulated, the reading is completed, the reading and writing state machine 300 jumps to a waiting state to wait for a next internal trigger signal, the read addresses of the rear stage FIFO220 and the DDR230 need to be reset at the moment, and the waveform data can be read from the read address 0 of the DDR230 and the waveform data in the rear stage FIFO220 keeps consistent each time the internal trigger signal is effective.

According to the method, through a DDR and rear-stage FIFO matching mechanism, the phase consistency of radar transmitting waveforms can be realized, and the waveform consistency is ensured. In addition, when the waveform data is read from the DDR, the DDR data supports data stream output, but the DDR read data is a charging and discharging process, and the delay of effective output of the first data is not fixed under the condition of fixed reading time, so that the waveforms are not coherent.

Example two

As shown in fig. 1, a coherent radar wide pulse waveform generating method according to a first embodiment of the present invention is specifically executed according to the following steps:

first, in step S1, the preceding stage FIFO210 receives the delivered waveform data.

The waveform data received by the front stage FIFO210 in the invention is generated by simulation according to the requirement of radar transmission waveform. Therefore, the method of the present invention may further comprise: waveform data is generated through simulation and stored in a waveform file, and then the waveform data is issued to the front stage FIFO210 through the PCI interface 120 by the upper computer software. The specific process can be as follows: after the upper computer software sends a waveform data downloading instruction, the waveform data is transmitted to the PCI interface 120 through the PCI bus, and is written into the front stage FIFO210 after being analyzed. In one embodiment, a set of waveform data can be generated by using Matlab software simulation according to the requirements of radar transmission waveforms and stored in a waveform file.

Subsequently, in step S2, the waveform data is stored in the DDR230 through the DDR MIG core 240 by read/write control to the front stage FIFO 210.

Since the DDR read-write bandwidth is larger than the waveform data download bandwidth, the non-empty signal of the front stage FIFO210 can be used as the read enable control signal of the front stage FIFO 210. When the front stage FIFO210 writes waveform data, the non-empty signal of the front stage FIFO210 is pulled high, and the read/write state machine 300 is controlled to enter a write state according to the non-empty signal. It should be understood that, in the present invention, step S2 is not executed after step S1 is completed, and when step S1 is started, i.e. the waveform data is written into the front stage FIFO210, the non-empty signal of the front stage FIFO210 is pulled high, the read/write state machine 300 can enter the write state, and then step S1 and step S2 can be executed synchronously.

In the write state, when the write ready signal of the DDR MIG core 240 is pulled high and the front stage FIFO210 is not empty, the front stage FIFO210 read enable is pulled high and the waveform data in the front stage FIFO210 is assigned to the input terminal of the DDR MIG core 240 through the read/write state machine 300 and then transmitted to the DDR 230. The front stage FIFO210 may function as a data buffer and clock domain crossing.

In the writing process, the data amount written into the DDR230 can be recorded by a write counter, the write counter accumulates every time one data is written, when the waveform data amount is accumulated to the lower-sending state, a write completion indication signal is generated, and the read/write state machine 300 jumps to the waiting state. The wait state indicates that the writing of the waveform data is completed and the reading can be performed.

Subsequently in step S3, the DDR MIG core 240 is controlled by the post FIFO220 programmable full signal to pre-read waveform data from the DDR 230.

If the waveform data is directly read from the DDR230, since the DDR230 reads the data in the charging and discharging process, the delay from the reading time to the first data output effective time is not fixed and discontinuous, and coherent and continuous radar emission waveforms cannot be realized. In order to ensure that the waveform data can be read out quickly and continuously, a part of the waveform data needs to be buffered in the subsequent stage FIFO220 before the read state starts. The buffer storage of partial waveform data is controlled by a programmable full signal of the rear-stage FIFO220, in a waiting state, the rear-stage FIFO220 is empty, the programmable full signal is pulled down, the read-write state machine controls the DDR230 to pre-read, the waveform data from the DDR MIG core 240 is written into the rear-stage FIFO220, along with the continuous writing of the waveform data, when the data volume in the rear-stage FIFO220 is larger than a set threshold value, the programmable full signal of the rear-stage FIFO220 is pulled up, the read-write state machine 300 jumps to the waiting state, the waveform data reading operation is interrupted, the ready signal is pulled up to wait, and the read state can be entered under the control of the radar timing state machine 400. The set threshold in the present invention may be set according to the waveform data amount, for example, the set threshold may be one fourth of the waveform data amount and smaller than the capacity of the rear stage FIFO, and if the set threshold is larger than the capacity of the rear stage FIFO, the value obtained by subtracting 100 from the capacity of the rear stage FIFO may be taken.

According to the invention, the DDR MIG core 240 is controlled by the full programmable signal of the rear-stage FIFO220 to realize pre-reading of waveform data in the DDR230, part of the waveform data is written into the rear-stage FIFO220 before the reading state starts, part of the waveform data can be cached by the rear-stage FIFO220, and the consistency of the reading time is ensured when the waveform is generated, so that the phase consistency is realized, and the coherent and continuous radar emission waveform can be realized.

Finally, in step S4, when the internal trigger signal generated according to the radar start command is detected, the back-stage FIFO220 outputs waveform data to the digital-to-analog conversion interface 110, and generates an analog signal to implement waveform output.

The internal trigger signal in the present invention is generated by the radar timing state machine 400 according to the radar start command. When the wait for ready signal is pulled high and the internal trigger signal is pulled high, the read/write state machine 300 jumps to the read state. After the read state starts, the read/write state machine 300 controls the read enable of the back stage FIFO220 to be pulled high, and the waveform data in the back stage FIFO220 is output to the digital-to-analog conversion interface 110 to generate an analog signal, thereby realizing waveform output.

With the decrease of the waveform data in the rear stage FIFO220, when the data amount of the rear stage FIFO220 is smaller than the set threshold, the programmable full signal is pulled down, at this time, the read/write state machine 300 controls the DDR230 to read the waveform data, the waveform data from the DDR MIG core 240 is written into the rear stage FIFO220 again, the DDR230 addresses are accumulated continuously, the data amount of the rear stage FIFO220 is supplemented, with the continuous writing of the waveform data, when the data amount of the rear stage FIFO220 is larger than the set threshold, the programmable full signal of the rear stage FIFO220 is pulled up again, and the feedback mechanism can maintain the data amount of the rear stage FIFO220 constant, and ensure the waveform continuity.

In the reading process, the data reading counter is accumulated every time one data reading counter is read, when the number of points corresponding to the waveform pulse width is accumulated, the reading is completed, the reading and writing state machine 300 jumps to a waiting state to wait for a next internal trigger signal, the read address of the rear stage FIFO220 and the read address of the DDR230 need to be reset at the moment, when the next internal trigger signal is effective, the waveform data can be read from the read address 0 of the DDR230, and the waveform data in the rear stage FIFO220 is triggered and kept consistent every time, so that the radar emission waveform coherence is ensured. When the radar timing state machine 400 receives the radar stop instruction and the read/write state machine 300 is in the wait state, the internal trigger signal is stopped, and the read/write state machine 300 jumps to the idle mode.

It should be understood that the coherent radar wide pulse waveform generation apparatus of the present invention has the same principle as the coherent radar wide pulse waveform generation method, and thus the detailed description of the embodiment of the coherent radar wide pulse waveform generation method is also applicable to the apparatus.

In conclusion, the method is used for generating the coherent radar wide pulse waveform, so that the on-chip resources can be greatly released, the flexibility of waveform generation is improved, and the adaptive waveform switching of the radar according to different modes in the working process can be ensured; the method can be applied to a multi-waveform and wide-pulse measurement radar system, realizes the phase consistency of radar emission waveforms through a DDR and later stage FIFO matching mechanism, and ensures the waveform coherence; in addition, when the waveform file is read from the DDR, the DDR data supports data stream output, but the DDR has a charge and discharge process, and the delay of the first data output of the waveform is not fixed under the condition of fixed reading time, so that the waveforms are not coherent.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (4)

1. A coherent radar wide pulse waveform generation method, comprising:

receiving the transmitted waveform data by a front stage FIFO;

storing the waveform data into a DDR through a DDR MIG core by utilizing the read-write control of the pre-stage FIFO;

controlling a DDR MIG core to pre-read waveform data from the DDR by utilizing a rear-stage FIFO programmable full signal;

when an internal trigger signal generated according to a radar starting instruction is detected, the rear-stage FIFO outputs waveform data to the digital-to-analog conversion interface to generate an analog signal, and waveform output is realized;

the step of storing the waveform data into the DDR through the DDR MIG core by utilizing the read-write control of the front stage FIFO specifically comprises the following steps:

detecting whether the front stage FIFO generates a non-empty signal, if so, writing the front stage FIFO data into the DDR when the DDR MIG core write ready signal is pulled up; in the writing process, waveform data volume written into DDR is accumulated, and when the waveform data volume is accumulated to the issued waveform data volume, the DDR jumps to a waiting state;

the step of utilizing the post-stage FIFO programmable full signal to control the DDR MIG core to pre-read waveform data from the DDR specifically comprises the following steps:

in a waiting state, when detecting that a programmable full signal of the rear-stage FIFO is low, writing DDR data into the rear-stage FIFO;

when the data volume of the rear-stage FIFO is detected to be larger than a set threshold value, a programmable full signal of the rear-stage FIFO is pulled up, the DDR data reading operation is interrupted, and a waiting ready signal is pulled up;

the step of outputting the waveform data to the digital-to-analog conversion interface by the back-stage FIFO specifically comprises the following steps:

when waiting for the ready signal to be pulled up, detecting whether an internal trigger signal generated according to a radar starting instruction is received, if so, skipping to a reading state, and controlling the continuous output of the rear-stage FIFO data to a digital-to-analog conversion interface; when the data volume of the rear-stage FIFO is detected to be smaller than a set threshold value, a programmable full signal of the rear-stage FIFO is pulled down, and DDR data is continuously written into the rear-stage FIFO; and when detecting that the accumulated amount of the read data is equal to the number of points corresponding to the waveform pulse width, skipping to a waiting state after the reading is finished, and resetting the rear-stage FIFO and the DDR read address.

2. The coherent radar wide pulse waveform generation method of claim 1, further comprising:

waveform data are generated through simulation and stored in a waveform file, and then the waveform file is issued to the front stage FIFO through an upper computer software via a PCI interface.

3. A coherent radar wide pulse waveform generation apparatus, comprising: the system comprises an integration module, an interface module, a read-write state machine and a radar time sequence state machine;

the interface module comprises a PCI interface and a digital-to-analog conversion interface;

the integrated module includes: a front-stage FIFO, a rear-stage FIFO, a DDR and a DDR MIG core; the input end of the front stage FIFO is connected with the PCI interface and is used for receiving the issued waveform data; the output end of the rear-stage FIFO is connected with the digital-to-analog conversion interface and used for outputting waveform data; the DDR MIG core is connected to the DDR to read and write data;

the radar time sequence state machine is used for generating an internal trigger signal according to a received radar starting instruction and a set period; the read-write state machine is connected with the radar time sequence state machine and a front-stage FIFO, a rear-stage FIFO and a DDR MIG core of the integrated module, and is used for storing waveform data written into the front-stage FIFO into a DDR through the DDR MIG core and controlling the DDR MIG core to pre-read the waveform data from the DDR through a rear-stage FIFO programmable full signal; the read-write state machine is also used for controlling the back-stage FIFO to output waveform data to the digital-to-analog conversion interface after detecting the internal trigger signal, generating an analog signal and realizing waveform output;

the read-write state machine is also used for detecting whether the front-stage FIFO generates a non-empty signal or not, and if so, writing the front-stage FIFO data into the DDR when the DDR MIG core write ready signal is pulled high; the read-write state machine is also used for accumulating the waveform data volume written into the DDR, and jumping to a waiting state when the waveform data volume is accumulated to the issued waveform data volume;

the read-write state machine is also used for writing DDR data into the rear-stage FIFO when the programmable full signal of the rear-stage FIFO is detected to be low in a waiting state; the read-write state machine is also used for interrupting DDR data read operation and pulling up a waiting ready signal when detecting that the data volume of the rear-stage FIFO is larger than a set threshold value and the programmable full signal of the rear-stage FIFO is pulled up;

the read-write state machine is also used for detecting whether an internal trigger signal generated according to a radar starting instruction is received or not when the ready signal is waited to be pulled up, and jumping to a read state if the internal trigger signal is received, and controlling the subsequent FIFO data to be continuously output to the digital-to-analog conversion interface; the read-write state machine is also used for controlling the programmable full signal of the rear-stage FIFO to be pulled down and continuously writing the DDR data into the rear-stage FIFO when the data volume of the rear-stage FIFO is detected to be smaller than a set threshold value; and the read-write state machine is also used for jumping to a waiting state after the reading is finished and resetting the rear-stage FIFO and the DDR read address when the accumulated quantity of the read data is detected to be equal to the number of points corresponding to the waveform pulse width.

4. The coherent radar wide pulse waveform generation device according to claim 3, further comprising:

and the simulation calculator is used for generating waveform data through simulation and then sending the waveform data to the front stage FIFO through the PCI interface through upper computer software.

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