CN111342785A - Signal conditioning circuit - Google Patents
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Abstract
The invention discloses a signal conditioning circuit and a signal conditioning method, wherein the signal conditioning circuit comprises a sensor, and the input end of the sensor is connected with a direct current power supply VCC; the reverse input end of the first amplifying circuit is connected with the output end of the sensor; the analog-to-digital conversion unit is connected with the output end of the first amplifying circuit; the control unit is connected with the output end of the analog-to-digital conversion unit and generates an output signal according to the change of the output signal of the first amplifying circuit; the input end of the digital-to-analog conversion unit is connected with the output end of the control unit; and the reverse input end of the second amplifying circuit is connected with the output end of the analog-to-digital conversion unit, the output end of the second amplifying circuit is connected with one end of a feedback resistor (R0), and the other end of the feedback resistor (R0) is connected with the reverse input end of the first amplifying circuit. The signal conditioning circuit realizes the simultaneous consideration of the detection range and the detection precision, and can improve the anti-interference capability of the detection circuit.
Description
Technical Field
The invention relates to the technical field of signal measurement, in particular to a signal conditioning circuit.
Background
In the technical fields of aerospace, unmanned aerial vehicles and the like, the acceleration signal can represent the running condition of the device, so that the requirement on acceleration control is high. Since the quartz accelerometer can detect external acceleration signals through the detection mass, and finally output current signals are in direct proportion to the acceleration signals through circuit demodulation and amplification, the output current of the meter head of the quartz accelerometer is usually adopted to reflect the magnitude of the acceleration. In the prior art, a signal conditioning circuit for detecting output current usually adopts a sampling resistor to convert current into voltage, then the load capacity of the signal is enhanced through a voltage follower, and then the signal is amplified and voltage-biased and then transmitted to an analog-to-digital converter (ADC). However, in the detection method in the prior art, although the signal acquisition capability and the load capability are improved, no current exists on a signal line of the voltage follower, and the anti-interference capability is weakened; if the range of the output ADC is increased, the sampling resistance needs to be reduced, but when the acceleration signal is weak, the signal input to the ADC only occupies a small part of the input range of the ADC; if the sampling resistance is increased, although the input range of the ADC can be fully utilized by weak acceleration signals, the precision is improved, the input range of the ADC can be exceeded when the acceleration is large, and the range and the precision cannot be considered at the same time.
Disclosure of Invention
Therefore, the technical problem to be solved by the invention is to overcome the defects that the detection circuit in the prior art has low anti-interference capability and cannot take the measurement range and the precision into consideration, thereby providing a signal conditioning circuit.
According to a first aspect, an embodiment of the present invention provides a signal conditioning circuit, including: the input end of the sensor is connected with a direct current power supply VCC; the reverse input end of the first amplifying circuit is connected with the output end of the sensor; the analog-to-digital conversion unit is connected with the output end of the first amplifying circuit; the control unit is connected with the output end of the analog-to-digital conversion unit and generates an output signal according to the change of the output signal of the first amplifying circuit; the input end of the digital-to-analog conversion unit is connected with the output end of the control unit; and the reverse input end of the second amplifying circuit is connected with the output end of the analog-to-digital conversion unit, the output end of the second amplifying circuit is connected with one end of a feedback resistor R0, and the other end of the feedback resistor R0 is connected with the reverse input end of the first amplifying circuit.
With reference to the first aspect, in a first implementation manner of the first aspect, the first amplifying circuit includes a first operational amplifier U1, a first resistor R1, and a bias resistor R2, the first resistor R1 is connected between an inverting input terminal and an output terminal of the first operational amplifier U1, one end of the bias resistor R2 is connected to a forward input terminal of the first operational amplifier U1, and the other end of the bias resistor R2 is grounded.
With reference to the first aspect, in a second implementation manner of the first aspect, the second amplifying circuit includes a second operational amplifier U2, a second resistor R3, and a bias resistor R4, the second resistor R3 is connected between an inverting input terminal and an output terminal of the second operational amplifier U2, one end of the bias resistor R4 is connected to a forward input terminal of the second operational amplifier U2, and the other end of the bias resistor R4 is grounded.
With reference to the first aspect, in a third implementation manner of the first aspect, the control unit includes an FPGA, an ARM, a DSP, or an MCU.
With reference to the first aspect, in a fourth implementation manner of the first aspect, the circuit further includes: and the voltage stabilizing circuit is connected with the output end of the first amplifying circuit and the input end of the analog-to-digital conversion unit.
With reference to the fourth implementation manner of the first aspect, in a fifth implementation manner of the first aspect, the voltage stabilizing circuit includes: the circuit comprises a third resistor R5, a fourth resistor R6 and a capacitor C3, wherein one end of the fourth resistor R6 is connected with one end of the capacitor C1 in series, and two ends of the third resistor R5 are respectively connected with the other end of the fourth resistor R6 and the other end of the capacitor C1.
With reference to the fifth implementation manner of the first aspect, in a sixth implementation manner of the first aspect, the circuit further includes: and one end of the fifth resistor R7 is connected with the output end of the digital-to-analog conversion unit, and the other end of the fifth resistor R7 is connected with the inverted input end of the second operational amplifier U2.
According to a second aspect, an embodiment of the present invention provides a signal conditioning method, which is used in the signal conditioning circuit described in the first aspect or any implementation manner of the first aspect, and includes: the control unit adjusts the output current of the digital-to-analog conversion unit to offset the current change of the input end of the first amplifying circuit, and the adjustment formula is as follows:
Ifb＝(Vo2-Vi)/R0
wherein Ifb is an output current, Vo2 is an output voltage of the second amplifying circuit, Vi is an input voltage of the inverting input terminal of the first amplifying circuit, and R0 is a feedback resistor.
The technical scheme of the invention has the following advantages:
the invention provides a signal conditioning circuit and a signal conditioning method, wherein the signal conditioning circuit comprises a sensor, the input end of which is connected with a direct current power supply VCC; the reverse input end of the first amplifying circuit is connected with the output end of the sensor; the analog-to-digital conversion unit is connected with the output end of the first amplifying circuit; the control unit is connected with the output end of the analog-to-digital conversion unit and generates an output signal according to the change of the output signal of the first amplifying circuit; the input end of the digital-to-analog conversion unit is connected with the output end of the control unit; and the reverse input end of the second amplifying circuit is connected with the output end of the analog-to-digital conversion unit, the output end of the second amplifying circuit is connected with one end of the feedback resistor R0, and the other end of the feedback resistor R0 is connected with the reverse input end of the first amplifying circuit. The signal conditioning circuit improves the anti-interference capability of the detection circuit, and realizes the simultaneous consideration of the detection range and the detection precision.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a circuit diagram of a signal conditioning circuit according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of signal conditioning according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of signal conditioning according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of signal conditioning according to an embodiment of the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
The embodiment provides a signal conditioning circuit, can be applied to current high accuracy measurement field such as aerospace, unmanned aerial vehicle, the quartz of this application use the aerospace field adds the table as the example, adds the table with this signal conditioning circuit application quartz, comes the size of characterization acceleration through output current. As shown in fig. 1, includes: the device comprises a sensor, a first amplifying circuit, an analog-to-digital conversion unit, a control unit, a digital-to-analog conversion unit, a second amplifying circuit and a feedback resistor. The input end of the sensor is connected with a direct current power supply VCC, and the output end of the sensor is connected with the reverse input end of the first amplifying circuit; the analog-to-digital conversion unit is connected with the output end of the first amplifying circuit; the control unit is connected with the output end of the analog-to-digital conversion unit and generates an output signal according to the change of the output signal of the first amplifying circuit; the input end of the digital-to-analog conversion unit is connected with the output end of the control unit; the reverse input end of the second amplifying circuit is connected with the output end of the analog-to-digital conversion unit, the output end of the second amplifying circuit is connected with one end of the feedback resistor R0, and the other end of the feedback resistor R0 is connected with the reverse input end of the first amplifying circuit.
The sensor is a sensor that reflects a parameter of the physical characteristic, that is, a sensor that can reflect a change of the physical characteristic through the output current, such as an acceleration sensor and a temperature sensor, and the sensor is not limited in this application and can be determined by a person skilled in the art according to actual needs. The input end of the sensor may include two input terminals, namely, a positive terminal and a ground terminal, the positive terminal is connected to the positive terminal of the dc power VCC, and the ground terminal is connected to the ground terminal of the dc power VCC, such as an acceleration sensor; a power access terminal may also be included and connected to the dc power source VCC via the power access terminal, such as a temperature sensor. The quartz accelerometer is taken as an example, namely an acceleration sensor is taken as an example, the analog-digital conversion unit, the digital-analog conversion unit and the control unit are connected with each other to form a closed loop, the analog-digital conversion unit can send the detected output voltage of the first amplifying circuit to the control unit, and the control unit can adjust the output current of the digital-analog conversion unit based on a target algorithm, so that the output voltage of the second amplifying circuit is adjusted, the current passing through the feedback resistor R0 is changed, the current change of the output end of the sensor caused by the acceleration change is counteracted, namely, the voltage change of the input end of the first amplifying circuit is counteracted, and the detection value of the analog-digital conversion unit returns to the initial value. The initial value of the analog-to-digital conversion unit may be set to the middle value of the operating voltage of the analog-to-digital conversion unit because the sensitivity of the digital-to-analog conversion unit is optimal at the middle value of the operating voltage. The signal conditioning circuit can ensure that the detection value of the analog-to-digital conversion unit is in an initial value no matter how large the voltage change input to the sensor by the direct-current power supply VCC is, namely, no matter how large the current change input to the input end of the first amplifying circuit by the output end of the sensor is, thereby ensuring that the detection precision is irrelevant to the measurement range, and ensuring that a signal path has certain current through reasonable parameter configuration, thereby improving the anti-jamming capability of the circuit. .
As an alternative embodiment of the present application, as shown in fig. 2, the first amplifying circuit includes a first operational amplifier U1, a first resistor R1 and a bias resistor R2, the first resistor R1 is connected between the inverting input terminal and the output terminal of the first operational amplifier U1, one end of the bias resistor R2 is connected to the forward input terminal of the first operational amplifier U1, and the other end is grounded. The second amplifying circuit comprises a second operational amplifier U2, a second resistor R3 and a bias resistor R4, wherein the second resistor R3 is connected between the inverting input end and the output end of the second operational amplifier U2, one end of the bias resistor R4 is connected with the inverting input end of the second operational amplifier U2, and the other end of the bias resistor R4 is grounded. The control unit comprises an FPGA or a singlechip or a DSP.
Illustratively, taking the control unit as FPGA, the analog-to-digital conversion unit as ADC, and the digital-to-analog conversion unit as DAC, the working voltage of the ADC is adjusted to V/2, and the output current of the DAC can be set by the FPGA, so that the working voltage of the ADC is V/2 when the ADC works at the middle value of its measurement range, that is, when the input current is zero. The forward input end of the first operational amplifier U1 and the forward input end of the second operational amplifier U2 are respectively connected with reference voltages Vbias1 and Vbias2, and the reference voltages of the forward input ends of the first operational amplifier U1 and the second operational amplifier U2 are respectively V/2 and V. The specific adjusting steps are as follows:
(1) when the input current Iacc1 of the quartz gauge head is 0, the FPGA sets the output current of the DAC to I0So that the output voltage Vo2 of the second operational amplifier is V-R3I0V/2; the input voltage Vi at the inverting input terminal of the first operational amplifier is constantly equal to V/2, so the total current Isum ═ iac 1+ Ifb ═ 0 is input to the inverting input terminal of the first operational amplifier, and after passing through the first resistor R1, the output voltage Vo1 ═ V/2-Isum × (R1) ═ V/2, that is, the ADC operates at the middle of its range.
(2) When the input current Iacc1 of the quartz gauge head is not equal to 0, the input voltage Vi of the inverting input end of the first operational amplifier is constantly equal to V/2, and the total current Isum input to the inverting input end of the first operational amplifier is equal to Iacc1+ Ifb; after passing through the first resistor R1, the output voltage Vo1 of the first operational amplifier is V/2-Isum R1;
(3) the ADC transmits the detection value of V1 to the FPGA;
(4) the FPGA controls the DAC to enable the output current to change △ I, and then Vo2 is V-R3 (I)0+△I)；
(5) And calculating a feedback current Ifb passing through the feedback resistor R0 according to the Vo2, the Vi and the feedback resistor, wherein the Ifb is (Vo2-Vi)/R0 is C △ I, so that the C △ I just offsets the Iacc1, and the Isum is Iacc1+ Ifb is 0 to enable the Vo1 to return to the middle point V/2 of the working range of the ADC.
In the process of regulating the working voltage of the ADC, the current digital quantity output by the DAC can reflect the acceleration, and when the quartz adding meter outputs large current, the DAC can regulate the current output so as to offset the large current output by the quartz adding meter, so that the output of the ADC cannot have the over-range problem. And by combining the resistors arranged between the output ends and the reverse input ends of the first operational amplifier and the second operational amplifier, the current passing on the signal line at any time is ensured, so that the anti-interference capability is enhanced.
As an alternative embodiment of the present application, as shown in fig. 3, the signal conditioning circuit further includes: the voltage stabilizing circuit is connected with the output end of the first amplifying circuit and the input end of the analog-to-digital conversion unit; the voltage stabilizing circuit comprises: the circuit comprises a third resistor R5, a fourth resistor R6 and a capacitor C1, wherein the fourth resistor R6 and the capacitor C1 are connected in series and are connected in parallel with the third resistor R5. The voltage on the signal wire can be more stable by arranging the voltage stabilizing circuit, the output voltage of the first amplifying circuit can be more easily detected by arranging the third resistor R5, the fourth resistor R6 and the capacitor C1, and the detection effect is better.
As an alternative embodiment of the present application, as shown in fig. 3, the signal conditioning circuit further includes: and one end of the fifth resistor R7 is connected with the output end of the digital-to-analog conversion unit, and the other end of the fifth resistor R7 is connected with the reverse input end of the second amplifying circuit. The output voltage on the signal line between the digital-to-analog conversion unit and the second amplification circuit can be more stabilized by providing the fifth resistor R7.
The present embodiment provides a signal conditioning method, which can be used in the signal conditioning circuit described in the foregoing embodiment, and the method includes:
the control unit adjusts the output current of the digital-to-analog conversion unit to offset the current change of the input end of the first amplifying circuit, and the adjustment formula is as follows:
Ifb＝(Vo2-Vi)/R0
wherein Ifb is an output current, Vo2 is an output voltage of the second amplifying circuit, Vi is an input voltage of the inverting input terminal of the first amplifying circuit, and R0 is a feedback resistor.
For an exemplary case, the adjusting step is described in the corresponding portion of the above embodiment, and is not described again here. As shown in fig. 4, when the first amplifying circuit includes the first operational amplifier U1, the first resistor R1 and the bias resistor R2; the second amplifying circuit comprises a second operational amplifier U2, a second resistor R3 and a bias resistor R4; the control unit comprises an FPGA; the voltage stabilizing circuit comprises a third resistor R5, a fourth resistor R6 and a capacitor C3, and is connected with the output end of the first operational amplifier U1 and the input end of the analog-to-digital conversion unit; one end of the fifth resistor R7 is connected to the output end of the digital-to-analog conversion unit, and the other end is connected to the inverting input end of the second operational amplifier U2. Wherein, the first operational amplifier U1 and the second operational amplifier U2 select a chip OPA21871DR, the feedback resistor R0 is 100 Ω/1206, the first resistor R1 is 1K Ω/1206, the second resistor R3 is 200 Ω/1206, the bias resistor R2 and the bias resistor R4 are 1K Ω/0603, the third resistor R5, the fourth resistor R6 and the capacitor C3 are 1K Ω/0603, 1K Ω/0603 and 0.1 μ 50V/0603 respectively, the fifth resistor R7 is 15 Ω/1206, the analog-to-digital conversion unit ADC is 700-MAX1168BEEG, the working range is 0-4.096V, the digital-to-analog conversion unit DAC is DAC8750IPWP, the working voltage of the ADC is set to be 2.048V all the time,
first, the reference voltages at the forward inputs of the first and second operational amplifiers U1 and U2 are 2.048V and 4.096V, respectively. When the input current Iacc1 of the quartz gauge head is 0, the FPGA sets the output current Iout of the DAC to be 10.24mA, so that the output voltage Vo2 of the second operational amplifier is 4.096-200 10.24 mA-2.048V; the input voltage Vi at the inverting input terminal of the first operational amplifier is equal to 2.048V, Ifb (Vo2-Vi)/R1 is equal to 0, so the total current Isum input to the inverting input terminal of the first operational amplifier is Iacc1+ Ifb is equal to 0, and after passing through the first resistor R1, the output voltage Vo1 of the first operational amplifier is equal to 2.048V-Isum 1K Ω is equal to 2.048V, that is, the ADC operates at the middle value of its range.
Secondly, when the input current Iacc1 of the quartz gauge head is not equal to 0, the input voltage Vi of the inverting input end of the first operational amplifier is constantly equal to 2.048V, and the total current Isum input to the inverting input end of the first operational amplifier is Iacc1+ Ifb; after passing through the first resistor R1, the output voltage Vo1 of the first operational amplifier is 2.048V-Isum × 1K Ω;
thirdly, the ADC transmits the detected value of Vo3 to the FPGA, and the FPGA controls the DAC to enable the output current to change △ I, so that Vo2 is 4.096V-200 omega (10.24mA + △ I);
again, the feedback current Ifb through the feedback resistor R0 is calculated from Vo2, Vi and the feedback resistor R0, Ifb ═ (Vo2-Vi)/R0 ═ -200 ═ △ I/100 ═ 2 ═ △ I, so that-2 ═ △ I just cancels Iacc1, when Isum ═ Iacc1+ Ifb ═ 0, Vo1 reverts to the midpoint of the ADC operating range at 2.048V.
When the quartz adding meter outputs large current, namely the current at the input end of the first amplifying circuit changes, the current output by the quartz adding meter can represent acceleration, and if the current is too large, the output of the analog-to-digital conversion unit generates an over-range problem, so that the acceleration measurement precision is reduced. The current output of the digital-to-analog conversion unit is adjusted through the FPGA, so that the large current output by the quartz adder is offset, the problem of over-range of the output of the analog-to-digital conversion unit is solved, the range and the measurement precision are considered, and the accuracy of acceleration measurement is ensured.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (8)
1. A signal conditioning circuit, comprising:
a sensor having an input terminal connected to a direct current power supply (VCC);
the reverse input end of the first amplifying circuit is connected with the output end of the sensor;
the analog-to-digital conversion unit is connected with the output end of the first amplifying circuit;
the control unit is connected with the output end of the analog-to-digital conversion unit and generates an output signal according to the change of the output signal of the first amplifying circuit;
the input end of the digital-to-analog conversion unit is connected with the output end of the control unit;
and the reverse input end of the second amplifying circuit is connected with the output end of the analog-to-digital conversion unit, the output end of the second amplifying circuit is connected with one end of a feedback resistor (R0), and the other end of the feedback resistor (R0) is connected with the reverse input end of the first amplifying circuit.
2. The circuit of claim 1, wherein the first amplifying circuit comprises a first operational amplifier (U1), a first resistor (R1) and a bias resistor (R2), the first resistor (R1) is connected between the inverting input terminal and the output terminal of the first operational amplifier (U1), one end of the bias resistor (R2) is connected to the forward input terminal of the first operational amplifier (U1), and the other end of the bias resistor is grounded.
3. The circuit of claim 1, wherein the second amplifying circuit comprises a second operational amplifier (U2), a second resistor (R3) and a bias resistor (R4), the second resistor (R3) is connected between the inverting input terminal and the output terminal of the second operational amplifier (U2), one end of the bias resistor (R4) is connected with the forward input terminal of the second operational amplifier (U2), and the other end of the bias resistor is grounded.
4. The circuit of claim 1, wherein the control unit comprises an FPGA or an ARM or a DSP or an MCU.
5. The circuit of claim 1, further comprising: and the voltage stabilizing circuit is connected with the output end of the first amplifying circuit and the input end of the analog-to-digital conversion unit.
6. The circuit of claim 5, wherein the voltage regulator circuit comprises: the circuit comprises a third resistor (R5), a fourth resistor (R6) and a capacitor (C1), wherein one end of the fourth resistor (R6) is connected with one end of the capacitor (C1) in series, and two ends of the third resistor (R5) are respectively connected with the other end of the fourth resistor (R6) and the other end of the capacitor (C1).
7. The circuit of claim 6, further comprising: and one end of the fifth resistor (R7) is connected with the output end of the digital-to-analog conversion unit, and the other end of the fifth resistor (R7) is connected with the reverse input end of the second amplifying circuit.
8. A signal conditioning method for use in a signal conditioning circuit as claimed in any one of claims 1 to 7, comprising:
the control unit adjusts the output current of the digital-to-analog conversion unit to offset the current change of the input end of the first amplifying circuit, and the adjustment formula is as follows:
Ifb＝(Vo2-Vi)/R0
wherein Ifb is an output current, Vo2 is an output voltage of the second amplifying circuit, Vi is an input voltage of the inverting input terminal of the first amplifying circuit, and R0 is a feedback resistor.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113551693A (en) * | 2021-07-26 | 2021-10-26 | 联合微电子中心有限责任公司 | Step-by-step self-zero-adjusting detection circuit and method |
| CN118432619A (en) * | 2024-07-02 | 2024-08-02 | 深圳斯诺凡科技有限公司 | Acquisition circuit and acquisition method of piezoresistive sensor |
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| CN113551693A (en) * | 2021-07-26 | 2021-10-26 | 联合微电子中心有限责任公司 | Step-by-step self-zero-adjusting detection circuit and method |
| CN118432619A (en) * | 2024-07-02 | 2024-08-02 | 深圳斯诺凡科技有限公司 | Acquisition circuit and acquisition method of piezoresistive sensor |
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