CN111293118B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN111293118B CN111293118B CN201811506592.9A CN201811506592A CN111293118B CN 111293118 B CN111293118 B CN 111293118B CN 201811506592 A CN201811506592 A CN 201811506592A CN 111293118 B CN111293118 B CN 111293118B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate; forming a gate dielectric layer on the substrate of the N-type transistor area and the P-type transistor area; forming a first work function layer on the gate dielectric layer for adjusting the threshold voltage of the P-type transistor; converting the first work function layer in the P-type transistor region into a second work function layer which is more difficult to etch than the first work function layer and is used for adjusting the threshold voltage of the P-type transistor; removing the first work function layer in the N-type transistor region; and after the first work function layer in the N-type transistor area is removed, forming a third work function layer covering the N-type transistor area and used for adjusting the threshold voltage of the N-type transistor. Because the second work function layer is more difficult to etch than the first work function layer, when the first work function layer in the N-type transistor area is etched and removed, the probability of the second work function layer in the P-type transistor area being mistakenly etched is reduced, and the electrical performance of the semiconductor structure is improved.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In the current semiconductor industry, integrated circuit products can be largely divided into three major types: logic, memory, and analog circuits, wherein memory devices represent a significant proportion of integrated circuit products. The development of semiconductor technology has led to a wider application of memory devices, which require that the memory device be formed on a chip together with other device regions to form an embedded semiconductor memory device. For example, the storage device is embedded in the cpu, so that the storage device is compatible with the embedded cpu platform, and the original specifications and corresponding electrical properties of the storage device are maintained.
In general, it is desirable to have the memory device compatible with embedded standard logic devices. For embedded semiconductor devices, they are generally divided into a logic region, which generally includes logic devices, and a memory region, which includes memory devices. With the development of Memory technology, various types of semiconductor memories such as static random access Memory (SRAM, static Random Access Memory), dynamic random access Memory (DRAM, dynamic Random Access Memory), erasable programmable read Only Memory (EPROM, erasable Programmable Read-Only Memory), electrically erasable programmable read Only Memory (EEPROM, electrically Erasable Programmable Read-Only) and Flash Memory (Flash) have emerged. Static random access memories have the advantages of low power consumption, high working speed and the like, so that the static random access memories and the forming method thereof are attracting more and more attention.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and optimizes the electrical performance of the semiconductor structure.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises an adjacent N-type transistor area and a P-type transistor area; forming a gate dielectric layer on the substrate of the N-type transistor area and the P-type transistor area; forming a first work function layer on the gate dielectric layer, wherein the first work function layer is used for adjusting the threshold voltage of the P-type transistor; converting a first work function layer in the P-type transistor region into a second work function layer that is more difficult to etch than the first work function layer and is used to adjust a threshold voltage of the P-type transistor; removing the first work function layer in the N-type transistor region; and after the first work function layer in the N-type transistor area is removed, forming a third work function layer covering the N-type transistor area, wherein the third work function layer is used for adjusting the threshold voltage of the N-type transistor.
Optionally, the step of forming the second work function layer includes: forming a mask layer covering the N-type transistor region and exposing the first work function layer of the P-type transistor region; the first work function layer in the P-type transistor region reacts with the modifying gas to form a second work function layer.
Optionally, the modifying gas is SiH 4 Or SiH 2 Cl 2 。
Optionally, the step of forming the second work function layer includes: forming a mask layer covering the N-type transistor region and exposing the first work function layer in the P-type transistor region; and doping ions in the first work function layer of the P-type transistor area to form a second work function layer.
Optionally, si, N or C is doped in the first work function layer by means of ion implantation.
Optionally, the second work function layer has a higher mass percentage of Si than the first work function layer; or the mass percentage of N in the second work function layer is higher than that of N in the first work function layer; or, the mass percentage of C in the second work function layer is higher than that in the first work function layer.
Optionally, the material of the first work function layer is TiN or TaN.
Optionally, the material of the first work function layer is TiN, and the material of the second work function layer is one or more of TiSiN, tiCN and nitrogen-rich titanium nitride; or the material of the first work function layer is TaN, and the material of the second work function layer is one or more of TaSiN, taCN and nitrogen-rich tantalum nitride.
Optionally, the material of the third work function layer is one or more of TiAl, taAlN, tiAlN, tiC, taCN, alN and TiAlC.
Optionally, the method for forming the semiconductor structure includes: after forming a gate dielectric layer and before forming a first work function layer, forming an anti-etching layer covering the gate dielectric layer; and in the step of removing the first work function layer in the N-type transistor region, taking the etching resistant layer as a stop layer.
Optionally, the material of the anti-etching layer is TaN.
Optionally, the thickness of the etching-resistant layer is 0.7 nm to 1 nm.
Optionally, a wet etching process is used to remove the first work function layer in the N-type transistor region.
Optionally, the wet etching process parameters include: a first cleaning step and a second cleaning step which are sequentially carried outThe method comprises the steps of carrying out a first treatment on the surface of the The cleaning solution used in the first cleaning step comprises NH 4 Solution and H 2 O 2 A solution; the cleaning temperature is 30-50 ℃; the cleaning solution used in the second cleaning step comprises HCl solution and H 2 O 2 A solution; the cleaning temperature is 40 ℃ to 60 ℃.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: the substrate comprises an N-type transistor area and a P-type transistor area; the gate dielectric layer is positioned on the substrates of the N-type transistor area and the P-type transistor area; the second work function layer is positioned on the substrate of the P-type transistor area and is used for adjusting the threshold voltage of the P-type transistor, and the material of the second work function layer is one or more of Si-rich, C-rich or N-rich; and the third work function layer is positioned on the substrate of the N-type transistor area and is used for adjusting the threshold voltage of the N-type transistor.
Optionally, the substrate includes: a substrate and discrete fins on the substrate.
Optionally, the material of the third work function layer is one or more of TiAl, taAlN, tiAlN, tiC, taCN, alN and TiAlC.
Optionally, the third work function layer is further located on the second work function layer.
Optionally, an etch-resistant layer is located on the substrate, and the second work function layer and the third work function are located on the etch-resistant layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the embodiment of the invention, a first work function layer in a P-type transistor area is converted into a second work function layer which is more difficult to etch than the first work function layer and is used for adjusting the threshold voltage of the P-type transistor; and forming a third work function layer covering the N-type transistor area. An N/P interface (N/P Boundary Interface) is formed between the first work function layer and the second work function layer at the junction of the NMOS transistor area and the PMOS transistor area, because the second work function layer is more difficult to etch than the first work function layer, when the first work function layer in the N-type transistor area is removed by etching, the probability of the second work function layer in the P-type transistor area being mistakenly etched is reduced, a groove is not easy to form in the P-type transistor area near the N/P interface, and correspondingly, a third work function layer formed later cannot be mistakenly introduced into the P-type transistor area, so that the threshold voltages of the P-type transistor area and the N-type transistor area are not easy to influence, the electrical parameters between the P-type transistor area and the N-type transistor area are well matched, and the electrical performance of the semiconductor structure is improved.
Drawings
Fig. 1 to 5 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;
fig. 6 to 14 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As can be seen from the background art, the devices formed at present still have the problem of poor performance. The reason for the poor performance of the device is analyzed by combining a forming method of a semiconductor structure.
Referring to fig. 1 to 5, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
Taking the semiconductor structure as an SRAM device as an example, as shown in fig. 1 and 2, fig. 1 is a schematic top view of the semiconductor structure, and fig. 2 is a cross-sectional view in a direction a-a in fig. 1. The SRAM device includes a Pull-Up (PU) transistor, a Pull-Down (PD) transistor, and a Pass Gate (PG) transistor, wherein the Pull-Up transistor is a PMOS transistor, and the Pull-Down transistor and the Pass Gate transistor are NMOS transistors.
Taking an SRAM device as a FinFET device, a region with a dashed box in the figure includes a pull-up transistor and a pull-down transistor, where the region where the pull-up transistor is located is a P-type transistor region I, the region where the pull-down transistor is located is an N-type transistor region II, the pull-up transistor includes a fin portion 1b and the pull-down transistor includes a fin portion 1a, and the fin portions 1a and 1b share a gate structure 8.
Specifically, as shown in fig. 2, the steps of forming the SRAM device include: providing a base comprising a substrate 2 and a fin 1 separated on the substrate 2; forming an isolation structure 5 on the substrate 2 exposed by the fin part 1; forming an interface layer 3 on the side wall and the top wall of the fin part 1 exposed by the isolation structure 5; and forming a gate dielectric layer 4 on the interfacial layer 3 and the isolation structure 5 exposed by the fin portion 1.
As shown in fig. 3, an etching-resistant layer 6 covering the gate dielectric layer 4 and a P-type work function layer 7 positioned on the etching-resistant layer 6 are formed;
as shown in fig. 4, a shielding layer 8 is formed to cover the P-type transistor region I and expose the N-type transistor region II.
As shown in fig. 5, a wet etching process is used to remove the P-type work function layer 7 in the N-type transistor region II exposed by the shielding layer 8.
In the subsequent process, an N-type work function layer is formed in the P-type transistor region I.
When the NMOS device and the PMOS device share the same gate structure, an N/P interface (N/P Boundary Interface) is formed between the N-type work function layer and the P-type work function layer at the interface of the NMOS device and the PMOS device, and when the P-type work function layer 7 exposed by the shielding layer 8 is removed by adopting a wet etching process, the P-type work function layer 7 near the N/P interface is easily etched by a lateral error in the N-type transistor region II to form a recess 9 (as shown in fig. 5), and then the N-type work function layer is easily filled into the recess 9 when the N-type work function layer is covered in the P-type transistor region I in a conformal manner, so that the work function materials at the N/P interface mutually diffuse and affect each other, which affects the threshold voltage of the PMOS device and the NMOS device, resulting in a deterioration of electrical parameter Mismatch (Mismatch) between the PMOS device and the NMOS device of the SRAM device, and further affecting the electrical performance of the SRAM device.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises an adjacent N-type transistor area and a P-type transistor area; forming a gate dielectric layer on the substrate of the N-type transistor area and the P-type transistor area; forming a first work function layer on the gate dielectric layer, wherein the first work function layer is used for adjusting the threshold voltage of the P-type transistor; converting a first work function layer in the P-type transistor region into a second work function layer that is more difficult to etch than the first work function layer and is used to adjust a threshold voltage of the P-type transistor; removing the first work function layer in the N-type transistor region; and after the first work function layer in the N-type transistor area is removed, forming a third work function layer covering the N-type transistor area, wherein the third work function layer is used for adjusting the threshold voltage of the N-type transistor.
In the embodiment of the invention, a first work function layer in a P-type transistor area is converted into a second work function layer, and the second work function layer is more difficult to etch than the first work function layer and is used for adjusting the threshold voltage of the P-type transistor; and forming a third work function layer covering the N-type transistor area. An N/P interface (N/P Boundary Interface) is formed between the first work function layer and the second work function layer at the junction of the NMOS transistor region and the PMOS transistor region, because the second work function layer has a higher etching selectivity ratio to the first work function layer, when the first work function layer in the N-type transistor region is removed by etching, the probability of the second work function layer in the P-type transistor region being erroneously etched is reduced, a groove is not easily formed in the P-type transistor region near the junction of the P-type transistor region and the N-type transistor region, and accordingly, the formed third work function layer is not erroneously introduced into the P-type transistor region, so that the threshold voltages of the P-type transistor region and the N-type transistor region are not easily affected, the electrical parameters between the P-type transistor region and the N-type transistor region are well matched, and the electrical performance of the semiconductor structure is improved.
In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, a detailed description of specific embodiments of the present invention is provided below with reference to the accompanying drawings.
Fig. 6 to 14 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 6, a substrate is provided, which includes adjacent N-type transistor region II and P-type transistor region I.
In this embodiment, the N-type transistor region II provides a process platform for forming a pull-down transistor, which is an NMOS device, subsequently; the P-type transistor region I provides a process platform for the subsequent formation of a pull-up transistor, which is a PMOS device.
In this embodiment, the base includes a substrate 100 and a discrete fin 101 located on the substrate 100, and the base includes: a substrate 100 and discrete fins 101 on said substrate 100.
The material of the substrate 100 is silicon, germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate 100 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate; the fin 101 material may include silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide. In this embodiment, the substrate 100 is a silicon substrate, and the material of the fin portion 101 is silicon.
The substrate further comprises: and the isolation structure 102 is positioned on the substrate 100 exposed by the fin 101, the isolation structure 102 covers part of the side wall of the fin 101, and the top of the isolation structure 102 is lower than the top of the fin 101. The isolation structures 102 serve to electrically isolate adjacent fins 101 from adjacent devices.
The isolation structure 102 is made of silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the isolation structure 102 is silicon oxide.
Referring to fig. 7, a gate dielectric layer 103 is formed on the substrate of the N-type transistor region II and the P-type transistor region I.
The step of forming the gate dielectric layer 103 includes: and forming a gate dielectric layer 103 on the fin portion 101 and the substrate 100 exposed by the fin portion 101.
The gate dielectric layer 103 is made of a gate dielectric material with a relative dielectric constant greater than that of silicon oxide. In this embodiment, the gate dielectric layer 103 is made of HfO2. In other embodiments, the gate dielectric layer may also be HfSiO, hfSiON, hfTaO, hfTiO, hfZrO, zrO 2 Or Al 2 O 3 。
In this embodiment, an atomic layer deposition process (Atomic Layer Deposition, ALD) is used to form the gate dielectric layer 103. In other embodiments, a physical vapor deposition process (Physical Vapor Diposition, PVD) may also be used to form the gate dielectric layer.
The method for forming the semiconductor structure further comprises the following steps: before forming the gate dielectric layer 103, an interface layer (Interfacial Layer, IL) 104 conformally covering the side walls and the top wall of the fin portion 101 is formed, and the gate dielectric layer 103 is located on the interface layer 104.
The interface layer 104 provides a good interface foundation for forming the gate dielectric layer 103, reduces the interface state density between the gate dielectric layer 103 and the fin portion 101, and avoids adverse effects caused by direct contact between the gate dielectric layer 103 and the fin portion 101.
In this embodiment, the material of the interface layer 104 is silicon oxide or silicon oxynitride.
In this embodiment, the interfacial layer 104 is formed by an oxidation process. In other embodiments, the interfacial layer may also be formed using a deposition process, such as: a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
The subsequent steps further comprise: a work function layer is formed on gate dielectric layer 103.
Referring to fig. 8, a first work function layer 105 is formed on the gate dielectric layer 103 for adjusting a threshold voltage of the P-type transistor.
In this embodiment, the material of the first work function layer 105 is TiN or TaN. The material of the first work function layer 105 is a P-type work function material, and the work function of the P-type work function material ranges from 5.1eV to 5.5eV.
In this embodiment, the first work function layer 105 may be formed using a chemical vapor deposition process (Chemical Vapor Deposition, CVD), a physical vapor deposition process, or an atomic layer deposition process.
The method for forming the semiconductor structure further comprises the following steps: after forming the gate dielectric layer 103, before forming the first work function layer 105, forming an anti-etching layer 106 covering the gate dielectric layer 103, wherein the anti-etching layer 106 is used as a stop layer in the step of removing the first work function layer 105 in the N-type transistor region II.
The material of the anti-etching layer 106 is different from that of the first work function layer 105, the etched rate of the anti-etching layer 106 is smaller than that of the first work function layer 105, and when the first work function layer 105 is etched subsequently, the anti-etching layer 106 can play a role of etching stop, so that etching damage to the gate dielectric layer 103 is not easy to occur.
In this embodiment, the material of the anti-etching layer 106 is TaN.
In this embodiment, the anti-etching layer 106 is formed by using an atomic layer deposition process, so that the anti-etching layer 106 has good step coverage.
In this embodiment, the etch-resistant layer 106 is preferably not too thick or too thin. The material of the anti-etching layer 106 is a P-type work function material, and the anti-etching layer 106 covers the P-type transistor region I and the N-type transistor region II; if the anti-etching layer 106 is too thick, the threshold voltage of the P-type transistor region I is affected; if the anti-etching layer 106 is too thin, the anti-etching layer 106 cannot well perform an etching stop function when the first work function layer 105 of the P-type transistor region I is removed by subsequent etching. In this embodiment, the thickness of the etching resist layer 106 is 0.7 nm to 1 nm.
Referring to fig. 9 to 12, the first work function layer 105 in the P-type transistor region I is converted into a second work function layer 107 (as shown in fig. 11), the second work function layer 107 being more difficult to etch than the first work function layer 105 and for adjusting the threshold voltage of the P-type transistor.
An N/P interface (N/P Boundary Interface) is formed between the first work function layer 105 and the second work function layer 107 at the junction of the NMOS transistor area II and the PMOS transistor area I, the second work function layer 107 is more difficult to etch than the first work function layer 105, when the first work function layer 105 in the N-type transistor area II is subsequently etched and removed, the probability of the second work function layer 107 in the P-type transistor area I being erroneously etched is reduced, a groove is not easily formed near the N/P interface in the P-type transistor area I, and accordingly, a third work function layer formed subsequently cannot be erroneously introduced into the P-type transistor area I, so that the threshold voltages of the P-type transistor area I and the N-type transistor area II are not easily affected, the electrical parameters between the P-type transistor area I and the NMOS transistor area II are well matched, and the electrical performance of the semiconductor structure is improved.
The second work function layer 107 is close to the work function of the first work function layer 105. In the embodiment of the present invention, the second work function layer 107 is used to replace the first work function layer 105, so that the performance of the semiconductor structure is not affected.
As shown in fig. 9 to 10, in the present embodiment, the step of forming the second work function layer 107 includes: a mask layer 108 is formed to cover the N-type transistor region II and expose the first work function layer 105 in the P-type transistor region I (as shown in fig. 10).
The step of forming the mask layer 108 includes: a mask material layer 109 (as shown in fig. 9) is formed to cover the first work function layer 105 conformally, and the mask material layer 109 in the N-type transistor region II is etched to form a mask layer 108.
In this embodiment, the material of the mask layer 108 is amorphous silicon. In other embodiments, the material of the mask layer may also be silicon nitride.
In this embodiment, the mask material layer 109 is formed by an atomic layer deposition process. In other embodiments, a physical vapor deposition process may be used to form the masking material layer.
As shown in fig. 11, the first work function layer 105 in the P-type transistor region I is reacted with a modifying gas to form a second work function layer 107. The gradient distribution of Si in the first work function layer 105 can be controlled by converting the first work function 105 into the second work function layer 107 through modification treatment, so that the Si content in the first work function layer 105 close to the surface of the first work function layer 105 is larger; the region of the first work function layer 105 close to the gate dielectric layer 103 has a smaller Si content, thereby reducing the influence on the gate dielectric layer 103.
In this embodiment, the modifying gas is SiH 4 . In other embodiments, the modifying gas may also be SiH 2 Cl 2 . In the present embodiment, the first work function layer 105 and SiH of the P-type transistor region I are formed 4 Or SiH 2 Cl 2 Reacting to form a second work function layer107 such that the mass percentage of Si in the second work function layer 107 is higher than the mass percentage of Si in the first work function layer 105. That is, the modifying gas is used to provide Si element to form the Si-rich second work function layer 107.
In this embodiment, the material of the first work function layer 105 is a P-type work function material, and the first work function layer 105 and SiH 4 The second work function layer 107 is formed by reaction. The second work function layer 107 is more difficult to etch than the first work function layer 105 in the subsequent step of removing the first work function layer 105. And the work function of the second work function layer 107 is close to the work function of the first work function layer 105.
The first work function layer 105 and SiH 4 Specific process parameters for forming the second work function layer 107 include: siH (SiH) 4 The flow rate of (C) is 5sccm to 200sccm, and the cavity pressure is 10Torr to 600Torr.
When the material of the first work function layer 105 is TiN, the material of the second work function layer 107 is TiSiN.
In other embodiments, the material of the first work function layer is TaN, and the material of the second work function layer is TaSiN.
In other embodiments, the first work function layer may also be modified with a C-containing gas to form a C-rich second work function layer. The mass percentage of C in the second work function layer is higher than that of C in the first work function layer. The gradient distribution of C in the first work function layer can be controlled by modifying the first work function layer to be converted into the second work function layer, so that the C content close to the surface of the first work function layer in the first work function layer is larger; the content of the region C, close to the gate dielectric layer, in the first work function layer is low, and therefore the influence on the gate dielectric layer is reduced.
In other embodiments, the first work function layer may also be modified with a gas containing N to form a second work function layer rich in N. The mass percentage of N in the second work function layer is higher than that of N in the first work function layer. The gradient distribution of N in the first work function layer can be controlled by modifying the first work function layer to be converted into the second work function layer, so that the N content in the first work function layer, which is close to the surface of the first work function layer, is larger; the N content of the area, close to the gate dielectric layer, of the first work function layer is low, and therefore the influence on the gate dielectric layer is reduced.
In other embodiments, the step of forming the second work function layer includes: ions are doped in the first work function layer of the P-type transistor region.
Specifically, si, N or C is doped in the first work function layer by means of ion implantation, so as to form a second work function layer.
The material of the first work function layer is TiN or TaN, and Si is doped in the first work function layer to form TiSiN or TaSiN respectively. The first work function layer is doped with Si such that the first work function layer of the polycrystalline structure is converted to a second work function layer of the amorphous structure, and thus the second work function layer is more difficult to etch than the first work function layer.
The parameters of the Si ion implantation process include: the implantation energy is 1KeV to 10KeV, the implantation dosage is 1.0E14atom/cm2 to 1.0E17atom/cm2, and the implantation angle is 7 degrees to 20 degrees.
When the material of the first work function layer is TiN, the doped ions can also be C ions or N ions to form TiCN or nitrogen-enriched titanium nitride. Nitrogen ions or carbon ions are doped in the first work function layer, so that the first work function layer of the polycrystalline structure is converted into a second work function layer of an amorphous structure. The second work function layer is more difficult to etch than the first work function layer.
Parameters of the C ion or N ion implantation process include: the implantation energy is 0.5KeV to 6KeV, the implantation dosage is 1.0E14atom/cm2 to 2.0E17atom/cm2, and the implantation angle is 7 degrees to 20 degrees.
When the material of the first work function layer is TaN, the doping ions can also be C ions or N ions, so as to form TaCN or nitrogen-rich tantalum nitride. Nitrogen ions or carbon ions are doped in the first work function layer, so that the first work function layer of the polycrystalline structure is converted into a second work function layer of an amorphous structure. The second work function layer is more difficult to etch than the first work function layer.
Parameters of the C ion or N ion implantation process include: the implantation energy is 0.5KeV to 7KeV, the implantation dosage is 1.0E14atom/cm2 to 1.5E17atom/cm2, and the implantation angle is 7 degrees to 20 degrees.
It should be noted that, when the step of converting the first work function layer into the second work function layer by using the ion implantation method further includes: and after the first work function layer is doped with ions, annealing the first work function layer doped with ions. The annealing process results in a more uniform distribution of the dopant ions in the first work function layer.
In other embodiments, the second work function layer is formed by doping Si, N or C in the first work function layer by ion implantation, that is, the ion implantation provides an element of Si, N or C such that the mass percentage of Si, N or C in the second work function layer is higher than the mass percentage of Si, N or C in the first work function layer.
As shown in fig. 12, the method for forming a semiconductor structure further includes: after the second work function layer 107 is formed, the mask layer 108 covering the N-type transistor region II is removed.
In this embodiment, the mask layer 108 is removed by ashing.
Referring to fig. 13, the first work function layer 105 in the N-type transistor region II is removed.
The step of removing the first work function layer 105 in the N-type transistor region II includes: a shielding layer 110 is formed to cover the second work function layer 107 and expose the first work function layer 105 in the N-type transistor region II.
In this embodiment, the material of the shielding layer 110 is a bottom anti-reflection layer. In other embodiments, the material of the shielding layer may also be photoresist.
In this embodiment, a wet etching process is used to remove the first work function layer 105 in the N-type transistor region II.
During the wet etching process, the etched rate of the first work function layer 105 is greater than the etched rate of the second work function layer 107.
Wet etchingThe technological parameters include: sequentially performing a first cleaning step and a second cleaning step; the cleaning solution used in the first cleaning step includes: NH (NH) 4 Solution and H 2 O 2 A solution; the cleaning temperature is 30-50 ℃; the cleaning solution used in the second cleaning step includes: HCl solution and H 2 O 2 A solution; the cleaning temperature is 40 ℃ to 60 ℃.
Specifically, NH in the first cleaning step 4 、H 2 O 2 And H 2 The volume percentage of O is 5:200:1000, HCL, H 2 O 2 And H 2 The volume percentage of O is 1:1.5:100.
after removing the mask layer 108, the shielding layer 110 is removed by an ashing process.
Referring to fig. 14, after the first work function layer 105 in the N-type transistor region II is removed, a third work function layer 111 covering the N-type transistor region II is formed for adjusting the threshold voltage of the N-type transistor.
In this embodiment, the material of the third work function layer 111 is one or more of TiAL, taAlN, tiAlN, tiC, taCN, alN and TiAlC.
In this embodiment, the third work function layer 111 is formed by a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 14, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.
The semiconductor structure includes: the substrate comprises an N-type transistor area II and a P-type transistor area I; the gate dielectric layer 103 is located on the substrate of the N-type transistor area II and the P-type transistor area I; the second work function layer 107 is located on the substrate of the P-type transistor area I and is used for adjusting the threshold voltage of the P-type transistor I, and the material of the second work function layer 107 is one or more of Si-rich, C-rich or N-rich; the third work function layer 111 is located on the substrate of the N-type transistor region II, and is used for adjusting the threshold voltage of the N-type transistor.
In this embodiment, the second work function layer 107 is formed by ion doping or chemical reaction of the first work function layer 105 (as shown in fig. 10) in the P-type transistor region I, and the second work function layer 107 is more difficult to etch than the first work function layer 105 due to the increased content of Si, C or N element before the ion doping or chemical reaction. It should be noted that, at the junction between the NMOS transistor region II and the PMOS transistor region I, there is an N/P interface (N/P Boundary Interface) between the first work function layer 105 and the second work function layer 107, and the first work function layer 105 is also formed in the N-type transistor region II, because the second work function layer 107 is more difficult to etch than the first work function layer 105, so that when the first work function layer 105 in the N-type transistor region II is removed, the probability of the second work function layer 107 being erroneously etched is reduced. In the P-type transistor area I, a groove is not easily formed near the N/P junction, and accordingly, the subsequently formed third work function layer 111 cannot be mistakenly inserted into the P-type transistor area I, so that the threshold voltages of the P-type transistor area I and the N-type transistor area II are not easily affected, and thus, the electrical parameters between the P-type transistor area I and the N-type transistor area II are well matched, and the electrical performance of the semiconductor structure is improved.
In this embodiment, the substrate includes: a substrate 100 and discrete fins 101 on said substrate 100.
The material of the substrate 100 is silicon, germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate 100 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate; the fin 101 material may include silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide. In this embodiment, the substrate 100 is a silicon substrate, and the material of the fin portion 101 is silicon.
The substrate further comprises: and the isolation structure 102 is positioned on the substrate 100 exposed by the fin portion 101. The isolation structure 102 covers part of the side wall of the fin 101, and the top of the isolation structure 102 is lower than the top of the fin 101. The isolation structures 102 serve to electrically isolate adjacent fins 101 from adjacent devices.
The isolation structure 102 is made of silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the isolation structure 102 is silicon oxide.
In this embodiment, the gate dielectric layer 103 is located on the substrate of the N-type transistor region II and the P-type transistor region I. Specifically, the gate dielectric layer 103 is located on the fin portion 101 and the substrate 100 exposed by the fin portion 101, and the second work function layer 107 and the third work function layer 111 are located on the gate dielectric layer 103.
The gate dielectric layer 103 is made of a gate dielectric material with a relative dielectric constant greater than that of silicon oxide. In this embodiment, the gate dielectric layer 103 is made of HfO 2 . In other embodiments, the gate dielectric layer may also be HfSiO, hfSiON, hfTaO, hfTiO, hfZrO, zrO 2 Or Al 2 O 3 。
The semiconductor structure further includes: and the interface layer 104 is positioned between the fin part 101 and the gate dielectric layer 103.
The interface layer 104 is configured to reduce the interface state density between the gate dielectric layer 103 and the fin portion 101, so as to avoid adverse effects caused by direct contact between the gate dielectric layer 103 and the fin portion 101.
In this embodiment, the material of the interface layer 104 is silicon oxide or silicon oxynitride.
The semiconductor structure further includes: an etch-resistant layer 106 is located on the substrate, and the second work function layer 107 and the third work function layer 111 are located on the etch-resistant layer 106.
Specifically, the anti-etching layer 106 is located on the gate dielectric layer 103. The anti-etching layer 106 is used for reducing the probability of being mistakenly etched in the process of forming the semiconductor.
In this embodiment, the material of the anti-etching layer 106 is TaN.
It should be noted that the etching resist layer 106 is not too thick or too thin. The material of the anti-etching layer 106 is a P-type work function material, the anti-etching layer 106 covers the gate dielectric layer 103, and if the anti-etching layer 106 is too thick, the threshold voltage of the P-type transistor area I is affected; if the anti-etching layer 106 is too thin, the anti-etching layer 106 cannot play a role of etching stop in the process of forming the semiconductor structure, and the probability of the gate dielectric layer 103 being erroneously etched cannot be reduced. In this embodiment, the thickness of the etching resist layer 106 is 0.7 nm to 1 nm.
In this embodiment, the material of the second work function layer 107 is one or more of TiSiN, taSiN, tiCN, taCN and titanium nitride-rich.
In this embodiment, the material of the third work function layer 111 is one or more of TiAl, taAlN, tiAlN, tiC, taCN, alN and TiAlC.
The third work function layer 111 is further located on the second work function layer 107.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (18)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises an adjacent N-type transistor area and a P-type transistor area;
forming a gate dielectric layer on the substrate of the N-type transistor area and the P-type transistor area;
forming a first work function layer on the gate dielectric layer, wherein the first work function layer is used for adjusting the threshold voltage of the P-type transistor; converting a first work function layer in the P-type transistor region into a second work function layer that is more difficult to etch than the first work function layer and is used to adjust a threshold voltage of the P-type transistor;
removing the first work function layer in the N-type transistor region;
and after the first work function layer in the N-type transistor area is removed, forming a third work function layer covering the N-type transistor area, wherein the third work function layer is used for adjusting the threshold voltage of the N-type transistor.
2. The method of forming a semiconductor structure of claim 1, wherein the step of forming a second work function layer comprises: forming a mask layer covering the N-type transistor region and exposing the first work function layer of the P-type transistor region;
the first work function layer in the P-type transistor region reacts with the modifying gas to form a second work function layer.
3. The method of forming a semiconductor structure of claim 2, wherein the modifying gas is SiH 4 Or SiH 2 Cl 2 。
4. The method of forming a semiconductor structure of claim 1, wherein the step of forming a second work function layer comprises: forming a mask layer covering the N-type transistor region and exposing the first work function layer in the P-type transistor region;
and doping ions in the first work function layer of the P-type transistor area to form a second work function layer.
5. The method of forming a semiconductor structure of claim 4, wherein Si, N, or C is doped in the first work function layer by ion implantation.
6. The method of forming a semiconductor structure of claim 1, wherein a mass percentage of Si in the second work function layer is higher than a mass percentage of Si in the first work function layer; or,
the mass percentage of N in the second work function layer is higher than that of N in the first work function layer; or,
the mass percentage of C in the second work function layer is higher than that of C in the first work function layer.
7. The method of claim 1, wherein the material of the first work function layer is TiN or TaN.
8. The method of claim 1, wherein the material of the first work function layer is TiN, and the material of the second work function layer is one or more of TiSiN, tiCN, and titanium nitride rich in nitrogen;
or the material of the first work function layer is TaN, and the material of the second work function layer is one or more of TaSiN, taCN and nitrogen-rich tantalum nitride.
9. The method of claim 1, wherein the third work function layer is formed of one or more of TiAl, taAlN, tiAlN, tiC, taCN, alN and TiAlC.
10. The method of forming a semiconductor structure of claim 1, wherein the method of forming a semiconductor structure comprises: after forming a gate dielectric layer and before forming a first work function layer, forming an anti-etching layer covering the gate dielectric layer; and in the step of removing the first work function layer in the N-type transistor region, taking the etching resistant layer as a stop layer.
11. The method of claim 10, wherein the etch-resistant layer is made of TaN.
12. The method of claim 10, wherein the etch-resistant layer has a thickness of 0.7 nm to 1 nm.
13. The method of claim 1, wherein the first work function layer in the N-type transistor region is removed by a wet etch process.
14. The method of forming a semiconductor structure of claim 13, wherein wet etching process parameters include: a first cleaning step and a second cleaning step which are sequentially performed; the cleaning solution used in the first cleaning step comprises NH 4 Solution and H 2 O 2 A solution; the cleaning temperature is 30-50 ℃; the second cleaning step uses a cleaning solution comprising HCl solution and H 2 O 2 A solution; the cleaning temperature is 40 ℃ to 60 ℃.
15. A semiconductor structure, comprising:
the substrate comprises an N-type transistor area and a P-type transistor area;
the gate dielectric layer is positioned on the substrates of the N-type transistor area and the P-type transistor area;
a second work function layer located on the substrate of the P-type transistor region and used for adjusting the threshold voltage of the P-type transistor, wherein the material of the second work function layer is one or more of Si-rich, C-rich or N-rich, the Si-rich, C-rich or N-rich is used for improving the etching difficulty of the second work function layer, the Si-rich, C-rich or N-rich is in gradient distribution in the second work function layer, the second work function layer is a silicon-rich, C-rich or N-rich material
The Si-rich, C-rich or N-rich content of the surface of the second work function layer is larger, and the Si-rich, C-rich or N-rich content of the area, close to the gate dielectric layer, in the second work function layer is smaller;
and the third work function layer is positioned on the substrate of the N-type transistor area and the second work function layer and is used for adjusting the threshold voltage of the N-type transistor.
16. The semiconductor structure of claim 15, wherein the substrate comprises: a substrate and discrete fins on the substrate.
17. The semiconductor structure of claim 15, wherein the material of the third work function layer is one or more of TiAl, taAlN, tiAlN, tiC, taCN, alN and TiAlC.
18. The semiconductor structure of claim 15, wherein the semiconductor structure further comprises: and the anti-etching layer is positioned on the substrate, and the second work function layer and the third work function layer are positioned on the anti-etching layer.
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