CN111212523A - Power integration module with low parasitic inductance and low thermal resistance - Google Patents
Power integration module with low parasitic inductance and low thermal resistance Download PDFInfo
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- CN111212523A CN111212523A CN202010178558.4A CN202010178558A CN111212523A CN 111212523 A CN111212523 A CN 111212523A CN 202010178558 A CN202010178558 A CN 202010178558A CN 111212523 A CN111212523 A CN 111212523A
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- 230000010354 integration Effects 0.000 title claims abstract description 25
- 230000003071 parasitic effect Effects 0.000 title claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 47
- 239000003990 capacitor Substances 0.000 claims abstract description 33
- 239000002184 metal Substances 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims description 17
- 230000000149 penetrating effect Effects 0.000 claims description 5
- 239000011347 resin Substances 0.000 claims description 4
- 229920005989 resin Polymers 0.000 claims description 4
- 238000001746 injection moulding Methods 0.000 claims description 3
- 229910002601 GaN Inorganic materials 0.000 description 21
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 21
- 238000010586 diagram Methods 0.000 description 6
- 230000017525 heat dissipation Effects 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 239000008186 active pharmaceutical agent Substances 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000165 glow discharge ionisation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
- H05K1/021—Components thermally connected to metal substrates or heat-sinks by insert mounting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
The embodiment of the invention relates to a power integration module with low parasitic inductance and low thermal resistance, which comprises a semiconductor switch device, a circuit board and a metal frame, wherein the semiconductor switch device is connected with the circuit board through a conductive wire; the metal frame comprises a radiating fin and a plurality of electrode terminals which are separated from each other, the semiconductor switch device is arranged between the circuit board and the radiating fin, and the surface of the circuit board, which is opposite to the semiconductor switch device, is provided with a capacitor which forms a current loop with the semiconductor switch device; the two opposite surfaces of the semiconductor switch device are respectively provided with a heat conducting disc and a plurality of electrodes, the electrodes are electrically connected with a plurality of electrode terminals through a circuit board, and the heat conducting disc is thermally connected with the radiating fin; the package encloses the circuit board, the semiconductor switching device and the capacitor, and exposes the plurality of electrode terminals and the heat sink. The semiconductor switch device and the capacitor are respectively arranged on two opposite sides of the circuit board to form a vertical layout, so that the area of a current loop is reduced conveniently to reduce parasitic inductance; the semiconductor switching device is thermally connected to the heat sink, which provides the module with low thermal resistance characteristics.
Description
Technical Field
The present invention relates to a power integration module; and more particularly, to a power integration module having both low parasitic inductance and low thermal resistance.
Background
GaN (gallium nitride) power devices, such as GaN MOSFETs, have a lower Figure of Merit (FOM) than conventional Si (silicon) power devices. Wherein FOM is defined as RDS,ONAnd (Q)GS+QGD) Product of (A), RDS,ONIs an on-resistance, QGSIs a gate-source charge, QGDIs the gate drain charge. This means that when having the same R as the Si power deviceDS,ONQ of GaN power deviceGS+QGDWill be much smaller than Si power devices. Lower QGS+QGDFaster rates of current and voltage change will result, i.e., di/dt and dv/dt will become larger.
In the application of a switching power supply, the GaN power device with high di/dt will cause the parasitic inductance of the circuit to generate a high peak voltage (voltage spike), which is liable to cause large electromagnetic interference (EMI) and increase the switching power loss thereof. Therefore, the layout of the power integrated module needs to minimize the parasitic inductance to achieve the desired switching characteristics of the GaN power device.
Fig. 1 is a schematic diagram of a bridge arm circuit of a typical power integrated module for a switching power supply application. As shown in fig. 1, the power integration module comprises a high-side MOSFET101, a low-side MOSFET 102, one or more decoupling capacitors 103, the drain D of the high-side MOSFET101 being connected to a power supply VINThe source S of the high-side MOSFET101 is electrically connected to the drain D of the low-side MOSFET 102 to form a switch node SW, which outputs a switch signal, the source S of the low-side MOSFET 102 is connected to ground GND, and the gates G of the high-side MOSFET101 and the low-side MOSFET 102 receive gate control signals from a controller (not shown). The two terminals of the decoupling capacitor 103 are respectively connected to the drain D of the high-side MOSFET101 and the source S of the low-side MOSFET 102, i.e., the high-side MOSFET101, the low-side MOSFET 102 and the decoupling capacitor 103 are sequentially connected to form a current loop, and reducing the area of the current loop is beneficial to reducing the parasitic inductance of the circuit.
On the one hand, for the sake of cost reduction and the like, Si is generally used as a substrate (GaN-on-Si) in fabricating a GaN power device, and electrodes and a Thermal Pad (Thermal Pad) of the GaN power device are respectively disposed on two opposite surfaces of the power device. Taking a GaN MOSFET as an example, when Si is used as a substrate, three electrodes (gate G, source S, and drain D) are disposed on a first surface of the GaN MOSFET, and a heat conducting pad is disposed on a second surface of the GaN MOSFET opposite to the first surface.
On the other hand, the Power integrated module is usually required to have a lower thermal resistance so as to have a better heat dissipation capability, and thus to improve the Power Density (Power Density), but when the conventional package layout structure is applied to a GaN Power device, the conventional package layout structure cannot simultaneously realize a lower thermal resistance and a smaller current loop area, and thus a good heat dissipation effect cannot achieve good EMI control, and vice versa. Two conventional package layout structures of the power integrated module shown in fig. 1 are taken as examples for explanation.
Fig. 2 is a schematic diagram of a conventional package structure of the power integrated module shown in fig. 1. As shown in fig. 2, the high side MOSFET101, the low side MOSFET 102 and the decoupling capacitor 103 are mounted on the same side surface of the circuit board and the current loop formed by the three is located in the X-Y plane. Obviously, when the high-side MOSFET101 and the low-side MOSFET 102 are GaN MOSFETs, in the planar layout of fig. 2, not only is the parasitic inductance high due to the difficulty in optimizing the current loop, but also the thermal conductive pad of the GaN MOSFET cannot be connected to a heat sink/heat spreader for heat dissipation, so that the module has a high thermal resistance.
Fig. 3a and 3b show another prior art package layout structure of the power integrated module shown in fig. 1. As shown in fig. 3a and 3b, the high side MOSFET101, the low side MOSFET 102 and the decoupling capacitor 103 are mounted on the same side surface of the circuit board 100, and the high side MOSFET101, the low side MOSFET 102 and the decoupling capacitor 103 form a current loop perpendicular to the X-Y plane. While the layout shown in fig. 3a and 3b can optimize the current loop to reduce the current loop area, the thermal pad of the GaN MOSFET can not be connected to a heat sink/heat spreader for heat dissipation when the high-side MOSFET101 and the low-side MOSFET 102 are GaN MOSFETs.
Therefore, there is a need for an improved packaging structure for power integrated modules.
Disclosure of Invention
In view of the deficiencies of the prior art, it is a primary object of the present invention to provide a power integration module having both low parasitic inductance and low thermal resistance.
In order to achieve the above main object, a power integration module according to an embodiment of the present invention includes:
a metal frame including a plurality of electrode terminals and a heat sink separated from each other;
a circuit board including an insulating substrate and conductive pattern layers formed on both opposite surfaces of the insulating substrate, the conductive pattern layers of the opposite surfaces of the insulating substrate being electrically connected through a conductive path penetrating the insulating substrate;
a semiconductor switching device having a plurality of electrodes on one surface thereof and a heat conductive pad on the other opposite surface; the semiconductor switching device is disposed between the circuit board and the heat sink, the heat conductive pad is thermally connected to the heat sink, and the plurality of electrodes are electrically connected to the plurality of electrode terminals via the circuit board;
a capacitor mounted on a surface of the circuit board opposite to the semiconductor switching device; a current loop is formed between the capacitor and the semiconductor switching device;
and a package body wrapping the circuit board, the semiconductor switching device and the capacitor and partially exposing the plurality of electrode terminals and the heat sink.
In the embodiment of the invention, on one hand, the semiconductor switch device and the capacitor in the current loop are respectively arranged on the two opposite sides of the circuit board, which is not only beneficial to the miniaturization of the module, but also convenient for optimizing the current loop to reduce the area of the current loop, thereby reducing the parasitic inductance; on the other hand, the heat conducting disc of the semiconductor switch device is thermally connected with the radiating fin, so that heat generated by the semiconductor switch device can be quickly diffused through the radiating fin, and the module has the advantages of small thermal resistance and good radiating performance. Therefore, the power integrated module provided by the embodiment of the invention has good heat dissipation performance and excellent EMI control at the same time.
According to an embodiment of the present invention, the circuit board is spaced apart from the plurality of electrode terminals, and the circuit board and the plurality of electrodes are electrically connected by a plurality of metal connectors.
According to another embodiment of the present invention, the plurality of electrode terminals are configured to be directly electrically connected to the circuit board. For example, the electrode terminal is electrically soldered to a conductive pattern of the circuit board so that the electrode terminal is electrically connected directly to the circuit board.
In an embodiment of the present invention, the mounting surface of the plurality of electrode terminals exposed to the package and the mounting surface of the heat sink exposed to the package may be located on the same surface side of the package. In a preferred embodiment of the present invention, the plurality of electrode terminals are flush with the mounting surface of the package and the heat sink is flush with the mounting surface of the package.
Among the above-mentioned technical scheme, with the mounting surface setting of electrode terminal and fin in the same surface side of packaging body, especially the parallel and level setting, not only can simplify the structure and the manufacture craft of module, reduce weight and the size of module, be convenient for moreover the follow-up installation of power integration module, for example be convenient for adopt SMT paster technology quick installation.
As described above, reducing the area of the current loop formed by the capacitor and the semiconductor switching device is advantageous for reducing the parasitic inductance. In order to minimize the area of the current loop, in an embodiment of the present invention, on one hand, the thickness of the circuit board is preferably less than 0.5 mm, and more preferably less than 0.3 mm; on the other hand, the capacitance and the semiconductor switching device may be arranged to at least partially overlap in a thickness direction of the circuit board. Wherein, when the number of the semiconductor switching devices is plural, the decoupling capacitance may be arranged to at least partially overlap with only one of the semiconductor switching devices or with a plurality (e.g., two) of the semiconductor switching devices in a thickness direction of the circuit board.
In an embodiment of the present invention, a chip driver electrically connected to the semiconductor switching device may be mounted on the circuit board. Further, other passive devices such as resistors, inductors, etc. may also be mounted on the circuit board.
In a preferred embodiment of the present invention, the package body is molded by a resin injection molding process.
In a preferred embodiment of the present invention, the semiconductor switching device is a GaN semiconductor switching device, such as a GaN nmosfet.
Specifically, the semiconductor switching device comprises a high-side MOSFET and a low-side MOSFET, wherein the source of the high-side MOSFET is electrically connected with the drain of the low-side MOSFET; one terminal of the capacitor is electrically connected to the drain of the high side MOSFET and the other terminal of the capacitor is electrically connected to the source of the low side MOSFET.
To more clearly illustrate the objects, technical solutions and advantages of the present invention, the present invention will be further described in detail with reference to the accompanying drawings and detailed description.
It should be noted that, for the sake of clarity, the structures shown in the drawings may not be drawn to the same scale, and therefore, unless explicitly stated otherwise, the representation in the drawings does not constitute a limitation on the size and scale of the components of the power integration module.
Drawings
FIG. 1 is a schematic diagram of a leg circuit of an exemplary power integration module for a switching power supply;
FIG. 2 is a schematic diagram of a prior art package structure of the power integration module shown in FIG. 1;
FIG. 3a is a top view of another prior art package structure of the power integration module shown in FIG. 1;
FIG. 3b is a side view of another prior art package structure of the power integration module shown in FIG. 1;
fig. 4 is a schematic diagram of a package structure of a preferred embodiment 1 of the power integrated module of the present invention;
fig. 5 is a schematic diagram of a package structure of a preferred embodiment 2 of the power integration module of the present invention.
Detailed Description
Embodiments relate to a power integrated module for, for example, a switching power supply, including a resin package body molded by, for example, a resin injection molding process, a circuit board, a semiconductor switching device, and a capacitor embedded in the package body, and a metal frame partially exposed from the package body. Wherein the capacitance may comprise, for example, a decoupling capacitance; the semiconductor switching device may be a GaN semiconductor switching device, such as a GaN MOSFET, which is typically structured to have a plurality of electrodes on one surface and a heat conducting pad on the opposite surface.
The thickness of the circuit board is preferably less than 1 mm, more preferably less than 0.5 mm, especially less than 0.3 mm. The circuit board includes an insulating substrate such as FR-4 and conductive pattern layers formed on both opposite surfaces of the insulating substrate, the two conductive pattern layers being electrically connected by a conductive path penetrating the insulating substrate. The conductive path may be a conductive via penetrating through the insulating substrate, and the conductive pattern layer may be a copper foil circuit layer with a thickness of 1OZ to 3OZ, but the invention is not limited thereto, and for example, the conductive pattern layer may be thicker or thinner.
The semiconductor switching device and the capacitor (e.g., decoupling capacitor) forming a current loop therewith are respectively mounted on two opposite surfaces of the circuit board, and are preferably arranged to at least partially overlap in a thickness direction of the circuit board. The number of semiconductor switching devices and capacitors in the current loop may be one or more, and is determined by the specific circuit design, which is not limited by the present invention.
The metal frame includes a plurality of electrode terminals and a heat sink that are separated from each other, and may be obtained by processing, for example, a copper plate; the plurality of electrode terminals are electrically connected to the circuit board directly or indirectly, and are further electrically connected to the respective electrodes of the semiconductor switching device through the circuit board. A semiconductor switching device disposed between the circuit board and the heat sink, a plurality of electrodes of the semiconductor switching device being electrically connected to the plurality of electrode terminals via the circuit board; the heat conducting plate of the semiconductor switch device is thermally connected with the heat radiating fin, and heat generated by the semiconductor switch device is quickly conducted to the heat radiating fin. The electrode terminals and the heat sink have mounting surfaces exposed to the package body, and the mounting surfaces of the electrode terminals and the heat sink are preferably disposed on the same surface side of the package body, particularly flush with each other.
The power integration module of the embodiment of the invention is not only convenient for optimizing the current loop formed by the semiconductor switch device and the capacitor, but also has excellent heat radiation performance and reduces the parasitic inductance by reducing the area of the current loop. The following describes the package structure of the power integrated module according to the preferred embodiment of the present invention in detail:
preferred embodiment 1
Referring to fig. 4, the power integrated module according to preferred embodiment 1 of the present invention includes a high-side MOSFET101, a low-side MOSFET 102, a decoupling capacitor 103 and a circuit board 104 in a package 108, wherein the high-side MOSFET101, the low-side MOSFET 102 and the decoupling capacitor 103 are connected in series to form a current loop. Specifically, referring to fig. 1, the source S of the high-side MOSFET101 is electrically connected to the drain D of the low-side MOSFET 102, one terminal 1031 of the decoupling capacitor 103 is electrically connected to the drain D of the high-side MOSFET101, and the other terminal 1032 of the decoupling capacitor 103 is electrically connected to the source S of the low-side MOSFET 102. Both high-side MOSFET101 and low-side MOSFET 102 are GaN MOSFETs having a drain D, a source S and a gate G on one surface and a heat conducting plate TP on the opposite surface.
The circuit board 104 has a thickness of, for example, about 0.2 mm, and includes an insulating substrate 1041, conductive pattern layers 1042 and 1043 formed on two opposite surfaces of the insulating substrate 1041; the conductive pattern layers 1042 and 1043 are, for example, copper foil circuit layers with a thickness of 2OZ, and the conductive pattern layers 1042 and 1043 are electrically connected through a conductive via 1044 penetrating through the insulating substrate 1041. The decoupling capacitor 103 is arranged to at least partially overlap with the high-side MOSFET101 and/or the low-side MOSFET 102 in the thickness direction of the circuit board 104. The two terminals 1031 and 1032 of the decoupling capacitor 103 are electrically soldered to the conductive pattern layer 1042, and the drains D, sources S, and gates G of the high-side MOSFET101 and the low-side MOSFET 102 are electrically soldered to the conductive pattern layer 1043, thereby forming a current loop. The circuit board 104 may also have mounted thereon a chip driver 105 for driving the respective MOSFETs, as well as other passive devices (e.g., resistors, inductors, shunt capacitors, etc.) not shown.
The metal frame 106 includes a plurality of electrode terminals 1061 and a heat sink 1062 separated from each other; the heat sink 1062 and the electrode terminal 1061 are formed as a substantially flat sheet having the same thickness, which may be 0.1 cm to 5 cm, for example, about 0.2 cm, but the present invention is not limited thereto. The electrode terminal 1061 and the heat sink 1062 are partially exposed from the package 108, and the mounting surface 10611 of the package 108 exposed from the electrode terminal 1061 and the mounting surface 10621 of the package 108 exposed from the heat sink 1062 are flush with each other. The mounting surface 10611 of the electrode terminal 1061 is located at or near the edge of the package body 108.
The circuit board 104 is disposed at intervals from the plurality of electrode terminals 1061, and the circuit board 104 and the plurality of electrode terminals 1061 are electrically connected by a plurality of metal connectors 107, such as copper blocks. The high side MOSFET101 and the low side MOSFET 102 are disposed between the circuit board 104 and the heat sink 1062, and the thermally conductive pads TP of the high side MOSFET101 and the low side MOSFET 102 are thermally connected to the heat sink 1062, for example by soldering the thermally conductive pads TP to the heat sink 1062 to establish thermal connection. It will be readily appreciated that in other, not illustrated embodiments of the invention, the metal frame may comprise a plurality of relatively independent heat sinks, and the thermally conductive pads of a plurality of semiconductor switching devices may be respectively soldered to different heat sinks.
Preferred embodiment 2
Referring to fig. 5, in the preferred embodiment 2 of the present invention, the metal frame 206 includes a heat sink 2062 and a plurality of electrode terminals 2061 separated from each other, and the electrode terminals 2061 and the heat sink 2062 are partially exposed from the package body 108. The electrode terminal 2061 is electrically soldered to the circuit board 104, the heat sink 2062 is exposed on the mounting surface 20621 of the package 108, the electrode terminal 2061 is exposed on the mounting surface 20611 of the package 108, and the mounting surface 20611 of the electrode terminal 2061 is located at or near the edge of the package 108. The thermally conductive pads TP of both the high side MOSFET101 and the low side MOSFET 102 are soldered to the heatsink 2062. For the description of the other parts of the preferred embodiment 2, please refer to the above preferred embodiment 1, which is not repeated herein.
In summary, the power integrated module disclosed in the preferred embodiment of the present invention has the characteristics of low parasitic inductance and low thermal resistance by the vertical layout of the package structure, and is small in size, light in weight, and convenient for subsequent mounting by, for example, SMT process.
Although the present invention has been described above by way of examples, it should be understood that the above examples are merely illustrative of possible embodiments of the present invention and should not be construed as limiting the scope of the present invention, and that equivalent alterations and modifications made by those skilled in the art in light of the present invention are also intended to be covered by the scope of the present invention as defined by the appended claims.
Claims (10)
1. A power integration module having low parasitic inductance and low thermal resistance, comprising:
a metal frame including a plurality of electrode terminals and a heat sink separated from each other;
a circuit board including an insulating substrate and conductive pattern layers formed on both opposite surfaces of the insulating substrate, the conductive pattern layers of the opposite surfaces of the insulating substrate being electrically connected through a conductive path penetrating the insulating substrate;
a semiconductor switching device having a plurality of electrodes on one surface thereof and a heat conductive pad on the other opposite surface; the semiconductor switching device is disposed between the circuit board and the heat sink, the heat conductive pad is thermally connected to the heat sink, and the plurality of electrodes are electrically connected to the plurality of electrode terminals via the circuit board;
a capacitor mounted on a surface of the circuit board opposite to the semiconductor switching device; a current loop is formed between the capacitor and the semiconductor switching device;
and a package body wrapping the circuit board, the semiconductor switching device and the capacitor and partially exposing the plurality of electrode terminals and the heat sink.
2. The power integration module of claim 1, wherein the circuit board is spaced apart from the plurality of electrode terminals, and the circuit board and the plurality of electrodes are electrically connected by a plurality of metal connectors therebetween.
3. The power integration module of claim 1, wherein the plurality of electrode terminals are configured to be directly electrically connected to the circuit board.
4. The power integrated module of claim 1, wherein the plurality of electrode terminals are flush with a mounting surface of the package body on which the heat sink is exposed.
5. The power integration module of claim 1, wherein the thickness of the circuit board is less than 0.5 millimeters.
6. The power integration module of claim 1, wherein the capacitance and the semiconductor switching device are arranged to at least partially overlap in a thickness direction of the circuit board.
7. The power integration module of claim 1, wherein the circuit board has mounted thereon a chip driver electrically connected to the semiconductor switching device.
8. The power integration module of claim 1, wherein the package body is molded by a resin injection molding process.
9. The power integration module of claim 1, wherein the semiconductor switching device is a GaN MOSFET.
10. The power integration module of claim 1, wherein the semiconductor switching device comprises a high-side MOSFET and a low-side MOSFET, a source of the high-side MOSFET being electrically connected to a drain of the low-side MOSFET; one terminal of the capacitor is electrically connected to the drain of the high side MOSFET and the other terminal of the capacitor is electrically connected to the source of the low side MOSFET.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010178558.4A CN111212523A (en) | 2020-03-14 | 2020-03-14 | Power integration module with low parasitic inductance and low thermal resistance |
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| CN202010178558.4A CN111212523A (en) | 2020-03-14 | 2020-03-14 | Power integration module with low parasitic inductance and low thermal resistance |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114078786A (en) * | 2020-08-12 | 2022-02-22 | 台达电子企业管理（上海）有限公司 | Power module assembling structure |
| CN114664771A (en) * | 2022-02-14 | 2022-06-24 | 致瞻科技(上海)有限公司 | Novel semiconductor capacitor packaging structure and packaging method thereof |
| WO2022205497A1 (en) * | 2021-03-30 | 2022-10-06 | 光华临港工程应用技术研发(上海)有限公司 | Power assembly |
| CN117936531A (en) * | 2024-03-04 | 2024-04-26 | 深圳市沃芯半导体技术有限公司 | Magnetic integrated power module packaging system, packaging method, device and medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114078786A (en) * | 2020-08-12 | 2022-02-22 | 台达电子企业管理（上海）有限公司 | Power module assembling structure |
| WO2022205497A1 (en) * | 2021-03-30 | 2022-10-06 | 光华临港工程应用技术研发(上海)有限公司 | Power assembly |
| CN114664771A (en) * | 2022-02-14 | 2022-06-24 | 致瞻科技(上海)有限公司 | Novel semiconductor capacitor packaging structure and packaging method thereof |
| CN117936531A (en) * | 2024-03-04 | 2024-04-26 | 深圳市沃芯半导体技术有限公司 | Magnetic integrated power module packaging system, packaging method, device and medium |
| CN117936531B (en) * | 2024-03-04 | 2024-05-28 | 深圳市沃芯半导体技术有限公司 | Packaging method, equipment and medium of magnetic integrated power module packaging system |
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