CN111211174B - SGT-MOSFET semiconductor device - Google Patents

Abstract

The invention provides a SGT-MOSFET semiconductor device, which belongs to the field of semiconductor technology, and its structure includes an N-type heavily doped semiconductor substrate and an N-type semiconductor drift region located on the upper surface of the N-type heavily doped semiconductor substrate; the N-type semiconductor drift The upper surface of the region is provided with a P-type region, and the upper surface of the P-type region is provided with an N-type heavily doped semiconductor source region. Control gate; the N-type heavily doped semiconductor source region is provided with a shielding gate that runs through the P-type region and extends to the N-type semiconductor drift region; there is at least one control gate, at least two shielding gates, and the control gates are arranged in phase Between the two adjacent shielding grids. The invention greatly improves the performance of the trench gate device by utilizing the technology of the split gate and the floating P well. The configuration of the floating P-well and the configuration of the N-drift region of the present invention has an optimized electric field distribution structure, improves device withstand voltage, reduces on-resistance, thereby reducing driving loss and switching loss.

Description

A kind of SGT-MOSFET semiconductor device

technical field

The invention relates to the technical field of power semiconductors, in particular to an SGT-MOSFET semiconductor device.

Background technique

SGT-MOSFET is a new type of power semiconductor device, which has the advantages of low conduction loss of traditional deep trench MOSFET, and has lower switching loss at the same time. As a switching device, SGT-MOSFET is used in motor drive systems, inverter systems and power management systems in new energy electric vehicles, new photovoltaic power generation, energy-saving home appliances and other fields, and is the core power control component.

SGT-MOSFET is a MOSFET with a deep trench vertical structure. It uses an independent field plate between the drain terminal and the gate terminal, and shields the source-drain parasitic capacitance formed between the gate and the drain. does not significantly increase the switching time of the device. SGT-MOSFET power devices have smaller gate-to-drain parasitic capacitance, low switching loss, faster switching speed, and better device performance.

The trench structure of a traditional SGT-MOSFET consists of two polysilicon parts: the upper part is the control gate, and the lower part is the shield gate, and the shield gate is located below the control gate, as shown in Figure 1. When the device is turned on, the drain current flows along the vertical sidewall of the trench, forming an inversion layer channel on the surface of the body region. When the source is positively biased, electrons are transported from the source region to the drain region along the inversion layer channel. After electrons pass through the channel from the source region, they enter the drift region at the bottom of the trench gate, and the current spreads across the entire cross-sectional width of the cell.

The electric field distribution structure of the traditional structure is single, the on-resistance is large, the withstand voltage performance of the device is not good, and the driving loss and switching loss are too large.

Contents of the invention

The technical task of the present invention is to solve the deficiencies of the prior art and provide an SGT-MOSFET semiconductor device.

The technical solution of the present invention is realized in the following manner. A SGT-MOSFET semiconductor device of the present invention has a structure comprising an N-type heavily doped semiconductor substrate (1) and an N-type heavily doped semiconductor substrate (1) N-type semiconductor drift region (2) on the upper surface;

The upper surface of the N-type semiconductor drift region (2) is provided with a P-type region (3),

An N-type heavily doped semiconductor source region (4) is provided on the upper surface of the P-type region (3),

The N-type heavily doped semiconductor source region (4) is provided with a control gate (5) that runs through the P-type region (3) and extends into the N-type semiconductor drift region (2);

The N-type heavily doped semiconductor source region (4) is provided with a shield gate (6) that runs through the P-type region (3) and extends into the N-type semiconductor drift region (2);

There is at least one control grid (5), and at least two shielding grids (6),

The control grid (5) is arranged between two adjacent shielding grids (6);

The control gate (5) is provided with a control gate insulating medium (7) in contact with the N-type semiconductor drift region (2), the P-type region (3) and the N-type heavily doped semiconductor source region (4), and the control gate (5 ) is provided with a control gate conductive material (9) surrounded by a control gate insulating medium (7);

The shielding gate (6) is provided with a shielding gate insulating medium (77) in contact with the N-type semiconductor drift region (2), the P-type region (3) and the N-type heavily doped semiconductor source region (4), and is insulated by the shielding gate. shielding grid conductive material (8) surrounded by medium (77);

The source electrode (12) is drawn out from the upper surface of the N-type heavily doped semiconductor source region (4),

The upper surface of the shielding grid conductive material (8) leads to the shielding grid source electrode (13);

The upper surface of the control gate conductive material (9) leads to the gate electrode (14),

A drain electrode (15) is drawn out from the lower surface of the N-type heavily doped semiconductor substrate (1).

The device may only be provided with three polysilicon parts, and the three polysilicon parts are respectively a control gate and two shielding gates, and the control gate is arranged between the two shielding gates adjacent to the left and right.

The control gate (5) penetrates the P-type region (3) layer downward from the surface of the N-type heavily doped semiconductor source region (4) layer and extends into the N-type semiconductor drift region (2) layer;

The shielding gate (6) penetrates downwardly from the surface of the N-type heavily doped semiconductor source region (4) layer to the P-type region (3) layer and extends into the N-type semiconductor drift region (2) layer.

The depth of the bottom end of the shielding gate (6) protruding downward into the layer of the N-type semiconductor drift region (2) is greater than the depth of the bottom end of the control gate (5) protruding downward into the layer of the N-type semiconductor drift region (2).

The adjacent control grid (5) and the shielding grid (6) have the separation distance of the N-type heavily doped semiconductor source region (4), the P-type region (3) and the N-type semiconductor drift region (2).

Design scheme 1 with floating P-well (10):

The bottom end of the control gate (5) protruding into the layer of the N-type semiconductor drift region (2) is provided with a floating P well (10) in the N-type semiconductor drift region (2), and the floating P well (10) at the bottom end of the control gate (5) is The P well (10) and the N-type semiconductor drift region (2) are arranged to form a PN junction.

Design scheme two with floating P-well (10):

A floating P well (10) in the N-type semiconductor drift region (2) is provided at the bottom end of the shielding gate (6) protruding into the layer of the N-type semiconductor drift region (2), and a floating P well (10) at the bottom end of the shielding gate (6) The P well (10) and the N-type semiconductor drift region (2) are arranged to form a PN junction.

Design scheme three with floating P-well (10):

The bottom ends of the control gate (5) and the shielding gate (6) penetrating into the layer of the N-type semiconductor drift region (2) are both provided with a floating P well (10) in the N-type semiconductor drift region (2);

The floating P well (10) at the bottom of the control gate (5) and the N-type semiconductor drift region (2) form a PN junction;

The floating P well (10) at the bottom end of the shielding gate (6) and the N-type semiconductor drift region (2) form a PN junction.

Expand the design plan:

An N-drift region (11) layer is provided between the bottom edge of the N-type semiconductor drift region (2) and the N-type heavily doped semiconductor substrate (1).

Optimized design scheme:

An N-drift region (11) layer is provided between the bottom edge of the N-type semiconductor drift region (2) and the N-type heavily doped semiconductor substrate (1), and the floating P well (10) at the bottom end of the shield gate (6) Set in the N-drift region (11) layer.

The beneficial effect that the present invention produces compared with prior art is:

The SGT-MOSFET semiconductor device of the present invention utilizes split gate and floating P well technology to significantly reduce on-resistance, increase device withstand voltage, and greatly improve the performance of trench gate devices.

The configuration of the floating P well in the N-type semiconductor drift region and the configuration of the N-drift region of the present invention have an optimized electric field distribution structure, improve device withstand voltage, reduce on-resistance, thereby reducing driving loss and switching loss.

The SGT-MOSFET semiconductor device of the present invention is reasonable in design, simple in structure, safe and reliable, convenient to use and easy to maintain, and has good popularization and use value.

Description of drawings

Accompanying drawing 1 is the structural representation of traditional SGT-MOSFET under prior art;

Accompanying drawing 2 is the structural representation of embodiment one of the present invention;

Accompanying drawing 3 is the structural representation of embodiment 2 of the present invention;

Accompanying drawing 4 is the structural schematic diagram of embodiment 3 of the present invention.

The marks in the accompanying drawings indicate respectively:

1. N-type heavily doped semiconductor substrate, 2. N-type semiconductor drift region, 3. P-type region, 4. N-type heavily doped semiconductor source region,

5. Control grid, 6. Shield grid,

7. Control grid insulating medium, 77. Shielding grid insulating medium,

8. Shielding grid conductive material, 9. Control grid conductive material,

10. Floating P-well,

11. N-drift zone,

12. Source electrode, 13. Shield gate source electrode, 14. Gate electrode, 15. Drain electrode.

Detailed ways

A SGT-MOSFET semiconductor device of the present invention will be described in detail below in conjunction with the accompanying drawings.

A SGT-MOSFET semiconductor device of the present invention adopts a split gate structure and consists of three polysilicon parts: a control gate and two shielding gates, the control gate is located in the middle of the two shielding gates, and the device includes N-type heavily doped semiconductor The substrate 1 and the N-type semiconductor drift region 2 located on the upper surface of the N-type heavily doped semiconductor substrate 1; the upper surface of the N-type semiconductor drift region 2 has a P-type region 3; the upper surface of the P-type region 3 has a N Type heavily doped semiconductor source region 4; the central part of the N-type heavily doped semiconductor source region 4 has a control gate 5 that runs through the P-type region 3 and extends into the N-type semiconductor drift region 2; the N-type heavily doped semiconductor Both sides of the source region 4 have a shield gate 6 that runs through the P-type region 3 and extends into the N-type semiconductor drift region 2; The shielding gate insulating dielectric 77 in contact with the semiconductor source region 4 and the shielding gate conductive material 8 surrounded by the shielding gate insulating dielectric 77; The control gate insulating dielectric 7 in contact with the hetero-semiconductor source region 4 and the control gate conductive material 9 surrounded by the control gate insulating dielectric 7; the bottom of the control gate 5 has a floating P well 10 in the N-type semiconductor drift region 2; A source electrode 12 is drawn from the upper surface of the N-type heavily doped semiconductor source region 4, a drain electrode 15 is drawn from the lower surface of the N-type heavily doped semiconductor substrate 1, and a gate electrode 14 is drawn from the upper surface of the control gate conductive material 9. The shielding grid source electrode 13 is led out from the upper surface of the shielding grid conductive material 8 .

Embodiment one:

As shown in Figure 2, it is a structural schematic diagram of this example. Compared with the traditional split gate structure, the present invention adjusts the electric field distribution in the upper part of the N-type drift region by setting a floating P well 10 at the bottom of the control gate 5, and the floating P The well 10 forms a PN junction with the N-type semiconductor drift region and depletes each other. At the same time, there is a thick gate oxide layer at the bottom of the control gate, which makes it impossible to concentrate the large electric field, which can improve the withstand voltage of the device and reduce the on-resistance; the invention will shield the gate The control gate and the control gate are placed in different trenches. By increasing the density of the conductive channel and adopting a deep trench structure, the on-resistance of the device is significantly reduced, and the nearby N-type drift region caused by the floating P well is suppressed to a certain extent. The increase in resistivity makes the device have a smaller on-resistance.

Embodiment two:

As shown in FIG. 3 , it is a schematic structural diagram of this example. Compared with the traditional split gate structure, the present invention adjusts the electric field distribution in the lower part of the N-type drift region by setting a floating P well 10 at the bottom of the shield gate 6 on both sides. The floating P well and the N-type semiconductor drift region form two PN junctions and deplete each other, which weakens the electric field at the bottom of the shield gate in the N-type semiconductor drift region, thereby improving the withstand voltage of the device; the invention places the shield gate and the control gate In different trenches, by increasing the conductive channel density and adopting a deep trench structure, the on-resistance of the device is significantly reduced.

As shown in Figure 3, the difference between this example and Example 1 is that the floating P wells are arranged at the bottom of the shield gates on both sides, which optimizes the electric field distribution structure in the lower part of the N-type drift region and improves the withstand voltage of the device.

Embodiment three:

Expand the optimized design, as shown in Figure 4, the difference between this example and Example 1 is that the floating P wells are respectively arranged at the bottom of the control gate and the shield gate, and the two floating P wells at the bottom of the shield gate are located in the N-drift region 11 Among them, the electric field distribution structure of the upper N-type drift region and the lower N-drift region is optimized to improve the withstand voltage of the device and reduce the on-resistance.

As shown in Figure 4, it is a structural schematic diagram of this example. Compared with the traditional split gate structure, the present invention adjusts the upper N Type drift region and the electric field distribution of the lower N-drift region, the floating P well at the bottom of the control gate forms a PN junction with the N-type semiconductor drift region and depletes each other, and the floating P well at the bottom of the shield gate forms a PN junction with the N-drift region Two PN junctions, and deplete each other, optimize the electric field distribution structure of the drift region at the bottom of the control gate and the bottom of the shielding gate, which can improve the withstand voltage of the device and reduce the on-resistance; the invention places the shielding gate and the control gate in different trenches , by increasing the conductive channel density and adopting a deep trench structure, the on-resistance of the device is significantly reduced.

Embodiment four:

Based on the main body structure of the above embodiments, the floating P well is connected to the bottom of the control gate.

Embodiment five:

On the basis of the main structure of the above embodiments, the floating P well is connected to the bottom of the shielding gate.

Embodiments 1 to 3 adopt a configuration in which the floating P wells are not connected. Embodiments 4 and 5 adopt a configuration in which the bottom of the floating P-well is connected to the control gate/shielding gate.

In the SGT-MOSFET structure existing in the prior art, the control gate and the shield gate are located in the same trench. The invention adopts the shield gate and the control gate to be placed in different trenches, and is an incremental MOSFET structure.

In the prior art, there is a configuration structure that adopts a P-type floating layer at the bottom of each trench, and the distance between adjacent trenches shows the discontinuity. By changing the electric field peak change at the bottom of the trench, the breakdown voltage is increased and Rsp is reduced. The setting of the floating P-well in the present invention utilizes the feature that the shield gate and the control gate are located in different trenches, as well as the difference in trench depth, to optimize the electric field distribution in different parts of the drift region, thereby increasing the withstand voltage of the device and reducing the conductivity. on-resistance.

Claims (4)

1. A SGT-MOSFET semiconductor device, characterized in that it comprises an N-type heavily doped semiconductor substrate (1) and an N-type semiconductor drift region (2) located on the upper surface of the N-type heavily doped semiconductor substrate (1); The upper surface of the N-type semiconductor drift region (2) is provided with a P-type region (3), An N-type heavily doped semiconductor source region (4) is provided on the upper surface of the P-type region (3), The N-type heavily doped semiconductor source region (4) is provided with a control gate (5) that runs through the P-type region (3) and extends into the N-type semiconductor drift region (2); The N-type heavily doped semiconductor source region (4) is provided with a shield gate (6) that runs through the P-type region (3) and extends into the N-type semiconductor drift region (2); There is at least one control grid (5), and at least two shielding grids (6), The control grid (5) is arranged between two adjacent shielding grids (6); The control gate (5) is provided with a control gate insulating medium (7) in contact with the N-type semiconductor drift region (2), the P-type region (3) and the N-type heavily doped semiconductor source region (4), and the control gate (5 ) is provided with a control gate conductive material (9) surrounded by a control gate insulating medium (7); The shielding gate (6) is provided with a shielding gate insulating medium (77) in contact with the N-type semiconductor drift region (2), the P-type region (3) and the N-type heavily doped semiconductor source region (4), and is insulated by the shielding gate. shielding grid conductive material (8) surrounded by medium (77); The source electrode (12) is drawn out from the upper surface of the N-type heavily doped semiconductor source region (4), The upper surface of the shielding grid conductive material (8) leads to the shielding grid source electrode (13); The upper surface of the control gate conductive material (9) leads to the gate electrode (14), A drain electrode (15) is drawn from the lower surface of the N-type heavily doped semiconductor substrate (1); The device adopts a split gate structure, and three polysilicon parts are arranged in the device, and the three polysilicon parts are respectively a control gate and two shielding gates, and the control gate is arranged between the two adjacent shielding gates on the left and right; The control gate (5) penetrates the P-type region (3) layer downward from the surface of the N-type heavily doped semiconductor source region (4) layer and extends into the N-type semiconductor drift region (2) layer; The shielding gate (6) penetrates downward from the surface of the N-type heavily doped semiconductor source region (4) layer to the P-type region (3) layer and extends into the N-type semiconductor drift region (2) layer; The depth of the bottom end of the shielding gate (6) protruding downward into the layer of the N-type semiconductor drift region (2) is greater than the depth of the bottom end of the control gate (5) protruding downward into the layer of the N-type semiconductor drift region (2); The distance between the adjacent control gate (5) and the shielding gate (6) is N-type heavily doped semiconductor source region (4), P-type region (3) and N-type semiconductor drift region (2); The bottom end of the control gate (5) protruding into the layer of the N-type semiconductor drift region (2) is provided with a floating P well (10) in the N-type semiconductor drift region (2), and the floating P well (10) at the bottom end of the control gate (5) is The P well (10) and the N-type semiconductor drift region (2) are arranged to form a PN junction. 2. a kind of SGT-MOSFET semiconductor device according to claim 1, is characterized in that: A floating P well (10) in the N-type semiconductor drift region (2) is provided at the bottom end of the shielding gate (6) protruding into the layer of the N-type semiconductor drift region (2), and a floating P well (10) at the bottom end of the shielding gate (6) The P well (10) and the N-type semiconductor drift region (2) are arranged to form a PN junction. 3. a kind of SGT-MOSFET semiconductor device according to claim 1, is characterized in that: The bottom ends of the control gate (5) and the shielding gate (6) penetrating into the layer of the N-type semiconductor drift region (2) are both provided with a floating P well (10) in the N-type semiconductor drift region (2); The floating P well (10) at the bottom of the control gate (5) and the N-type semiconductor drift region (2) form a PN junction; The floating P well (10) at the bottom end of the shielding gate (6) and the N-type semiconductor drift region (2) form a PN junction. 4. a kind of SGT-MOSFET semiconductor device according to claim 1, is characterized in that: An N-drift region (11) layer is provided between the bottom edge of the N-type semiconductor drift region (2) and the N-type heavily doped semiconductor substrate (1), and the floating P well (10) at the bottom end of the shield gate (6) Set in the N-drift region (11) layer.

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