CN111210751B - Display driving circuit, display screen and electronic equipment - Google Patents
Display driving circuit, display screen and electronic equipment Download PDFInfo
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- CN111210751B CN111210751B CN202010037391.XA CN202010037391A CN111210751B CN 111210751 B CN111210751 B CN 111210751B CN 202010037391 A CN202010037391 A CN 202010037391A CN 111210751 B CN111210751 B CN 111210751B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
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Abstract
The invention relates to the technical field of communication, and provides a display driving circuit, a display screen and electronic equipment, wherein the display driving circuit comprises at least one grid driving unit and at least two grid lines, the display driving circuit also comprises at least one display driving unit, each grid driving unit is connected with N grid lines through one display driving unit, N is an integer larger than 1, and the display driving unit comprises: a timing controller; a switch controller connected with the N gate lines corresponding to the time schedule controller and the gate driving unit; for each of the N gate lines corresponding to the gate driving unit, the switch controller outputs a preset voltage signal or a gate driving signal output by the gate driving unit to the gate line based on a timing signal output by the timing controller. The embodiment of the invention can reduce the non-content display area of the display screen.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a display driving circuit, a display screen, and an electronic device.
Background
With the popularization of electronic devices, the functions of the electronic devices are becoming more and more complete. When the electronic equipment is used, information interaction between people and the electronic equipment is realized through a display screen of the electronic equipment. The display screen of the electronic equipment is provided with a non-content display area which is displayed as a black edge, and specific display contents cannot be presented to a user.
Currently, a display screen of an electronic device includes gate driving units, each gate driving unit is connected to one gate line, each gate line is connected to one row of sub-pixels, and the gate driving units drive the corresponding row of sub-pixels, however, a larger number of gate driving units on the display screen results in a larger non-content display area of the display screen.
Disclosure of Invention
The embodiment of the invention provides a display driving circuit, a display screen and electronic equipment, which are used for solving the problem that a large number of grid driving units on the display screen cause a large non-content display area of the display screen in the prior art.
In order to solve the technical problems, the invention is realized as follows:
in a first aspect, an embodiment of the present invention provides a display driving circuit, where the display driving circuit includes at least one gate driving unit and at least two gate lines, the display driving circuit further includes at least one display driving unit, each gate driving unit is connected to N gate lines through one display driving unit, N is an integer greater than 1, and the display driving unit includes:
a timing controller;
a switch controller connected with the N gate lines corresponding to the time schedule controller and the gate driving unit;
for each of the N gate lines corresponding to the gate driving unit, the switch controller outputs a preset voltage signal or a gate driving signal output by the gate driving unit to the gate line based on a timing signal output by the timing controller.
In a second aspect, an embodiment of the present invention provides a display screen, which includes the display driving circuit according to the first aspect.
In a third aspect, an embodiment of the present invention provides an electronic device, including a display screen according to the second aspect.
In an embodiment of the present invention, the display driving circuit includes at least one gate driving unit and at least two gate lines, the display driving circuit further includes at least one display driving unit, each gate driving unit is connected to N gate lines through one display driving unit, N is an integer greater than 1, and the display driving unit includes: a timing controller; a switch controller connected with the N gate lines corresponding to the time schedule controller and the gate driving unit; for each of the N gate lines corresponding to the gate driving unit, the switch controller outputs a preset voltage signal or a gate driving signal output by the gate driving unit to the gate line based on a timing signal output by the timing controller. Therefore, each grid driving unit is connected with N grid lines which are adjacently arranged through one display driving unit, the number of the grid driving units can be reduced through the display driving units with simpler circuit structures, and the non-content display area of the display screen can be reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments of the present invention will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.
Fig. 1 is a schematic diagram of a display driving circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a display driving unit in a display driving circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a display screen according to an embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating timing control in a display driving circuit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a switch controller in a display driving circuit according to an embodiment of the present invention;
fig. 6 is a second timing control diagram of a display driving circuit according to an embodiment of the invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In an embodiment of the present invention, the electronic device includes, but is not limited to, a mobile phone, a tablet computer, a notebook computer, a palm computer, a vehicle-mounted mobile terminal, a wearable device, a pedometer, and the like.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a display driving circuit according to an embodiment of the present invention, as shown in fig. 1, the display driving circuit 1 includes at least one gate driving unit and at least two gate lines, the display driving circuit 1 further includes at least one display driving unit 2, each gate driving unit is connected to N gate lines through one display driving unit 2, N is an integer greater than 1, as shown in fig. 2, the display driving unit 2 includes:
a timing controller 3;
a switch controller 4 connected to the N gate lines corresponding to the timing controller 3 and the gate driving unit;
for each of the N gate lines corresponding to the gate driving unit, the switch controller 4 outputs a preset voltage signal or a gate driving signal output from the gate driving unit to the gate line based on a timing signal output from the timing controller 3.
The preset voltage signal may be a low level signal. Optionally, the display driving circuit 1 is configured to output a gate driving signal output by the gate driving unit to the gate line, so as to drive the sub-pixels on the display screen. For example, as shown in fig. 1, all the sub-pixels are arranged in a plurality of rows and columns, each sub-pixel is connected to one gate line and one source line, the sub-pixel electrodes of the sub-pixels in the same column are connected to the same source line, and the sub-pixel electrodes of the sub-pixels in the same row are connected to the same gate line. The grid lines are grid scanning lines, and the source lines are source data lines. The subpixels may include a red subpixel R, a green subpixel G, and a blue subpixel B, which may form a pixel capacitor, and the difference in voltages on the capacitors may control the deflection direction of the liquid crystal, thereby controlling how much light is projected through the liquid crystal. As shown in fig. 1, each subpixel is connected to a thin film transistor (Thin Film Transistor, TFT) switching circuit, the TFT connecting the source line, gate line and subpixel together.
In addition, the display driving circuit 1 may include a plurality of display driving units 2, each of which is connected to each of the display driving units 2 in a one-to-one correspondence. The gate driving unit may be an array substrate row driving (Gate Driver On Array, GOA) unit. Alternatively, each gate driving unit is connected to N adjacently arranged gate lines through one of the display driving units. As shown in fig. 1, N has a value of 3, and each GOA unit may be connected to 3 adjacent arranged gate lines through one of the display driving units 2. The timing controller 3 is configured to generate a timing signal for controlling the switch controller 4 to output the gate driving signal to the target gate line or to output a preset voltage signal to the target gate line. The timing signal may be generated based on a gate driving signal output from the gate driving unit, or the timing signal may be set in advance. Of course, N may alternatively be another integer. For example, if the subpixels on the display screen include four subpixels R1, R2, G, and B, N may correspond to 4, and if the display screen includes other numbers of subpixels, N may correspond to the number of subpixels. The specific value of N in the embodiment of the present invention is not particularly limited.
In the prior art, the GOA units are scanned line by line, one GOA unit corresponds to one gate line one by one, the GOA units are controlled by a time sequence to output a high level VGH or a low level VGL, and VGH and VGL can be used for controlling the on and off of the TFTs. In the GOA unit On time gate_on of one frame, the GOA unit output VGH controls the TFT to be turned On, and the source driving unit outputs a source driving signal to the source line, so that the gray scale voltage of the R, G, B sub-pixel is output.
In the embodiment of the present invention, as shown in fig. 3, one GOA unit may time-divisionally drive R, G, B three rows of sub-pixels, for example, GOA unit G1 may time-divisionally drive R, G, B three rows of sub-pixels through signals G11, G12 and G13, that is, time-divisionally drive R, G and B sub-pixel rows in original gate_on time, as shown in fig. 4, in the time-On of GOA unit of one frame, scan R sub-pixel row g_ R, G sub-pixel row g_ G, B sub-pixel row g_b may be switched row by the switch controller 4. Alternatively, each sub-pixel row control time may be 1/3gate_on. Of course, alternatively, the control time of different sub-pixel rows may also be different, which is not particularly limited in the embodiment of the present invention. For example, since the sensitivity of the human eye to green light is different from that of red light and blue light, the control time of the G sub-pixel row can be correspondingly increased, and the control time of other pixel rows can be reduced, so that the display result is more in line with the human visual experience effect.
As shown in fig. 2, taking one display driving unit 2 in the display driving circuit 1 as an example, the display driving unit 2 is configured to output the gate driving signals output by the gate driving units to 3 adjacent gate lines gn_ R, gn _ G, gn _b in a time-sharing manner, and the timing controller 3 may include three output terminals of mux_ R, mux _ G, mux _b. The switch controller 4 may include 3 second control switches 5, each of the first control switches 5 may be an alternative switch, and the first control ends sw_ R, SW _g and sw_b of the 3 first control switches 5 may control the first connection end T1 to be connected with the second connection end T2, or control the first connection end T1 to be connected with the third connection end T3. In the case where the gate driving signal is at a high level VGH, sw_r selects VGH or VGL according to the signal output by mux_r; SW_G selects VGH or VGL according to the signal output by Mux_G; sw_b selects VGH or VGL according to the signal output by mux_b. The relationship between the timing signal outputted from the timing controller 3 and the sw_ R, SW _g and sw_b is shown in table 1.
TABLE 1
In fig. 2, when the gate driving signal is at a high level VGH and sw_r is VGH, sw_g and sw_b are VGL, the display driving unit 2 outputs the gate driving signal output from the gate driving unit to gn_r and outputs the low level signal to gn_g and gn_b for controlling the R sub-pixel row TFT thin film transistors to be turned on, the G sub-pixel row TFT thin film transistors to be turned off, and the B sub-pixel row TFT thin film transistors to be turned off; in the case where the gate driving signal is at a high level VGH and sw_g selects VGH and sw_r and sw_b select VGL, the display driving unit 2 outputs the gate driving signal output from the gate driving unit to gn_g and outputs the low level signal to gn_r and gn_b for controlling the on of the G sub-pixel row TFT thin film transistors, the off of the R sub-pixel row TFT thin film transistors, and the off of the B sub-pixel row TFT thin film transistors; in the case where the gate driving signal is at a high level VGH and sw_b selects VGH, sw_r and sw_g select VGL, the display driving unit 2 outputs the gate driving signal output from the gate driving unit to gn_b and outputs the low level signal to gn_g and gn_r for controlling the on of the B sub-pixel row TFT thin film transistors, the off of the R sub-pixel row TFT thin film transistors, and the off of the G sub-pixel row TFT thin film transistors.
In fig. 2, when the gate driving signal is at a high level, mux_ R, mux _g and mux_b can control the selection state of sw_ R, SW _ G, SW _b, mux_r can be used to control sw_r to select VGH or VGL; mux_g may be used to control sw_g to select VGH or VGL; mux_b may be used to control sw_b to select VGH or VGL. The switch sw_ck is used for controlling the switch controller 4 and the timing controller 3 to be connected or disconnected, the control signal Crtl output by the gate driving unit controls the switch sw_ck, when the gate driving unit outputs VGH, the switch sw_ck is in a connected state, and when the gate driving unit outputs VGL, the switch sw_ck is in an disconnected state. The relationship between the control signal Crtl and the switch sw_ck is shown in table 2.
TABLE 2
In table 2, when the control signal Crtl output by the gate driving unit is at a high level, three groups of sub-switches S1, S2 and S3 in the switch sw_ck are closed, and mux_r and sw_ R, mux _g and sw_g and mux_b are respectively communicated; when the control signal Crtl output by the gate driving unit is at a low level, three groups of sub-switches S1, S2 and S3 in the switch sw_ck are turned off, and mux_r and sw_ R, mux _g and sw_g and mux_b and sw_b are turned off, respectively.
It should be noted that, the display driving circuit 1 includes a plurality of display driving units 2, and the timing controller 3 of each display driving unit 2 may be set separately, or in order to make the circuit structure simpler, all the timing controllers 3 of the display driving units 2 may be the same timing controller, or may be different timing controllers. In the display driving circuit 1 shown in fig. 1, the timing controllers 3 of all the display driving units 2 are the same timing controller, and as shown in fig. 5, the timing signals are used for controlling the Gate driving signals output by each display driving unit 2 to be output to 3 adjacent arranged Gate lines corresponding to the display driving unit 2 in a time sharing manner within the GOA unit On time gate_on of one frame of picture, and the driving time of each Gate line is 1/3gate_on.
In the embodiment of the present invention, the display driving circuit 1 includes at least one gate driving unit and at least two gate lines, the display driving circuit 1 further includes at least one display driving unit 2, each gate driving unit is connected to N gate lines through one display driving unit 2, N is an integer greater than 1, and the display driving unit 2 includes: a timing controller 3; a switch controller 4 connected to the N gate lines corresponding to the timing controller 3 and the gate driving unit; for each of the N gate lines corresponding to the gate driving unit, the switch controller 4 outputs a preset voltage signal or a gate driving signal output from the gate driving unit to the gate line based on a timing signal output from the timing controller 3. In this way, each gate driving unit is connected with N gate lines arranged adjacently through one display driving unit 2, and the number of gate driving units can be reduced through the display driving unit 2 with a simpler circuit structure, so that the non-content display area of the display screen can be reduced.
Optionally, the timing signal is generated based on a gate driving signal output by the gate driving unit.
Optionally, as shown in fig. 2, the switch controller 4 includes N first control switches 5, where the N first control switches 5 are connected to N gate lines corresponding to the gate driving units in a one-to-one correspondence manner, the first control switch 5 includes a first connection end, a second connection end, a third connection end, and a first control end, the first connection end is connected to the corresponding gate line, the second connection end is connected to a voltage signal line, the third connection end is connected to the gate driving unit, and the first control end is connected to the timing controller 3;
the first control end is used for controlling the first connection end to be connected with the second connection end based on the time sequence signal, or controlling the first connection end to be connected with the third connection end based on the time sequence signal.
The first control switch 5 may be an electronic switch, specifically, an electronic switch composed of a metal-oxide semiconductor field effect transistor, that is, a MOS transistor. The first connection end of the first control switch 5 is connected with a grid line corresponding to the first control switch 5. The first control end is used for controlling the first connection end to be communicated with the third connection end and transmitting the grid driving signal to the corresponding grid line; or the first control end is used for controlling the first connection end to be communicated with the second connection end and transmitting the preset voltage signal to the corresponding grid line. The voltage signal line is a signal line providing a preset voltage signal, and may be a signal line providing a low level VGL as shown in fig. 1. As shown in fig. 2, taking one display driving unit 2 in the display driving circuit 1 as an example, the value of N is 3, the display driving unit 2 is configured to output the gate driving signal output by the gate driving unit to 3 adjacent gate lines gn_ R, gn _ G, gn _b in a time-sharing manner, and 3 first control switches 5 are connected to 3gate lines corresponding to the gate driving units in a one-to-one correspondence manner.
In this embodiment, the switch controller 4 includes N first control switches 5, where the N first control switches 5 are connected to N gate lines corresponding to the gate driving units in a one-to-one correspondence manner, and the N first control switches 5 control the N gate lines to be communicated with the gate driving units or to be communicated with the voltage signal lines, so that one gate driving unit can drive sub-pixel rows corresponding to the N gate lines in a time sharing manner, and the circuit structure is simple.
Optionally, as shown in fig. 2, the timing controller 3 includes N output terminals 7, the switch controller 4 further includes N second control switches 6, where the N second control switches 6 are connected to the N output terminals 7 in a one-to-one correspondence manner and are connected to the N first control switches 5 in a one-to-one correspondence manner, the second control switches 6 include a fourth connection terminal, a fifth connection terminal, and a second control terminal, the fourth connection terminal is connected to the corresponding output terminal 7, the fifth connection terminal is connected to the first control terminal of the corresponding first control switch 5, and the second control terminal is connected to the gate driving unit;
the second control terminal is configured to control, based on the gate driving signal, the fourth connection terminal to be connected to the fifth connection terminal, or control, based on the gate driving signal, the fourth connection terminal to be disconnected from the fifth connection terminal.
The second control switch 6 may be an electronic switch, specifically, an electronic switch composed of a metal-oxide semiconductor field effect transistor, that is, a MOS transistor. The second control end is used for controlling the fourth connecting end to be communicated with or disconnected from the fifth connecting end. Each output end 7 of the N output ends 7 is connected with each first control switch 5 through a second control switch 6 in a one-to-one correspondence, and the second control switch 6 controls the output end 7 to be turned on or turned off with the first control switch 5. As shown in fig. 2, taking one display driving unit 2 in the display driving circuit 1 as an example, the value of N is 3, the timing controller 3 includes 3 output terminals 7, such as mux_ R, mux _ G, mux _b, and 3 second control switches 6 are respectively three groups of sub-switches S1, S2 and S3 in the switch sw_ck, and the gate driving unit outputs the control signal Crtl to the second control terminals.
In this embodiment, the switch controller 4 further includes N second control switches 6, where the N second control switches 6 are connected to the N output ends 7 in a one-to-one correspondence manner, and are connected to the N first control switches 5 in a one-to-one correspondence manner, and the N second control switches 6 control the connection or disconnection of the timing controller 3 and the first control switches 5, so that one gate driving unit can drive the sub-pixel rows corresponding to the N gate lines in a time sharing manner, and the circuit structure is simple.
Optionally, as shown in fig. 5, the first control switch 5 includes a first electronic switch 51, a second electronic switch 52, and a not gate 53, where a first end of the first electronic switch 51 is connected to a first connection end, a second end of the first electronic switch 51 is connected to the third connection end, and a third end of the first electronic switch 51 is connected to the first control end;
the first end of the second electronic switch 52 is connected to the first connection end, the second end of the second electronic switch 52 is connected to the second connection end, the third end of the second electronic switch 52 is connected to the output end 7 of the not gate 53, and the input end of the not gate 53 is connected to the first control end.
In this embodiment, the first electronic switch 51 and the second electronic switch 52 may be MOS transistors, and the first control switch 5 is formed by the first electronic switch 51, the second electronic switch 52 and the not gate 53, so that the circuit implementation is relatively simple.
Optionally, as shown in fig. 5, the second control switch 6 includes a third electronic switch, a first end of the third electronic switch is connected to the fourth connection end, a second end of the third electronic switch is connected to the fifth connection end, and a third end of the third electronic switch is connected to the second control end.
In this embodiment, the third electronic switch may be a MOS transistor, and the first control switch 5 is formed by the third electronic switch, so that the circuit implementation is relatively simple.
Optionally, the timing controllers 3 of all display driving units in the at least one display driving unit 2 are the same timing controller.
Alternatively, the value of N is 3.
Optionally, the three gate lines corresponding to the gate driving units are connected with the three sub-pixels of the same pixel unit in a one-to-one correspondence.
In this embodiment, as shown in fig. 1, the three sub-pixels R, G and B of the same pixel unit are driven by the same gate driving unit in a time-sharing manner, so that the conventional driving timing of the gate driving unit does not need to be changed, and the implementation is easy.
Optionally, the switch controller 4 is further configured to sequentially transmit the gate driving signal to three sub-pixels of the same pixel unit within a preset time under the control of the gate driving signal and the timing signal.
In this embodiment, as shown in fig. 6, the preset time may be the GOA unit On time gate_on of a frame, and the three sub-pixels R, G and B of the same pixel unit are driven by the same Gate driving unit in time division of gate_on, so that the driving timing of the existing Gate driving unit does not need to be changed, and the implementation is relatively simple.
The embodiment of the invention also provides a display screen, which comprises the display driving circuit 1.
Since other structures of the display screen are the prior art, the display driving circuit 1 is described in detail in the above embodiments, and therefore, the specific structure of the display screen in this embodiment is not described again.
In an embodiment of the present invention, a display driving circuit of a display screen includes at least one gate driving unit and at least two gate lines, the display driving circuit further includes at least one display driving unit, each gate driving unit is connected to N gate lines through one display driving unit, N is an integer greater than 1, and the display driving unit includes: a timing controller; a switch controller connected with the N gate lines corresponding to the time schedule controller and the gate driving unit; for each of the N gate lines corresponding to the gate driving unit, the switch controller outputs a preset voltage signal or a gate driving signal output by the gate driving unit to the gate line based on a timing signal output by the timing controller. Therefore, each grid driving unit is connected with N grid lines which are adjacently arranged through one display driving unit, the number of the grid driving units can be reduced through the display driving units with simpler circuit structures, and the non-content display area of the display screen can be reduced.
The embodiment of the invention also provides electronic equipment, which comprises the display screen.
In the embodiment of the invention, the display screen of the electronic equipment comprises the display driving circuit, so that the non-content display area of the display screen of the electronic equipment is smaller, and the user experience of the user when the electronic equipment is used is better.
The foregoing is merely illustrative embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think about variations or substitutions within the technical scope of the present invention, and the invention should be covered. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
Claims (9)
1. A display driving circuit, wherein the display driving circuit includes at least one gate driving unit and at least two gate lines, the display driving circuit further includes at least one display driving unit, each gate driving unit is connected with N gate lines through one display driving unit, N is an integer greater than 1, the display driving unit includes:
a timing controller;
a switch controller connected with the N gate lines corresponding to the time schedule controller and the gate driving unit;
for each of the N gate lines corresponding to the gate driving unit, the switch controller outputs a preset voltage signal or a gate driving signal output by the gate driving unit to the gate line based on a timing signal output by the timing controller;
the switch controller comprises N first control switches, N grid lines corresponding to the grid driving units are connected in a one-to-one correspondence mode, the first control switches comprise first connecting ends, second connecting ends, third connecting ends and first control ends, the first connecting ends are connected with the corresponding grid lines, the second connecting ends are connected with voltage signal lines, the third connecting ends are connected with the grid driving units, and the first control ends are connected with the time sequence controller;
the first control end is used for controlling the first connection end to be connected with the second connection end based on the time sequence signal, or controlling the first connection end to be connected with the third connection end based on the time sequence signal;
the time sequence controller comprises N output ends, the switch controller further comprises N second control switches, the N second control switches are connected with the N output ends in one-to-one correspondence and connected with the N first control switches in one-to-one correspondence, the second control switches comprise fourth connecting ends, fifth connecting ends and second control ends, the fourth connecting ends are connected with the corresponding output ends, the fifth connecting ends are connected with the first control ends of the corresponding first control switches, and the second control ends are connected with the grid driving unit;
the second control terminal is configured to control, based on the gate driving signal, the fourth connection terminal to be connected to the fifth connection terminal, or control, based on the gate driving signal, the fourth connection terminal to be disconnected from the fifth connection terminal.
2. The display drive circuit according to claim 1, wherein the timing signal is generated based on a gate drive signal output from the gate drive unit.
3. The display driver circuit of claim 1, wherein the first control switch comprises a first electronic switch, a second electronic switch, and a not gate, a first end of the first electronic switch is connected to a first connection terminal, a second end of the first electronic switch is connected to the third connection terminal, and a third end of the first electronic switch is connected to the first control terminal;
the first end of the second electronic switch is connected with the first connecting end, the second end of the second electronic switch is connected with the second connecting end, the third end of the second electronic switch is connected with the output end of the NOT gate, and the input end of the NOT gate is connected with the first control end.
4. A display driver circuit according to claim 3, wherein the second control switch comprises a third electronic switch, a first terminal of the third electronic switch being connected to the fourth connection terminal, a second terminal of the third electronic switch being connected to the fifth connection terminal, and a third terminal of the third electronic switch being connected to the second control terminal.
5. The display driving circuit according to claim 1, wherein the timing controllers of all display driving units in the at least one display driving unit are the same timing controller.
6. The display driving circuit according to any one of claims 1 to 5, wherein the value of N is 3, and three gate lines corresponding to the gate driving unit are connected to three sub-pixels of the same pixel unit in one-to-one correspondence.
7. The display driving circuit according to claim 6, wherein the switch controller is further configured to sequentially transmit the gate driving signal to three sub-pixels of the same pixel unit for a preset time under the control of the gate driving signal and the timing signal.
8. A display screen comprising a display drive circuit as claimed in any one of claims 1 to 7.
9. An electronic device comprising the display screen of claim 8.
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| CN103700354A (en) * | 2013-12-18 | 2014-04-02 | 合肥京东方光电科技有限公司 | Grid electrode driving circuit and display device |
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| KR20060076480A (en) * | 2004-12-29 | 2006-07-04 | 엘지.필립스 엘시디 주식회사 | Driving device of liquid crystal display |
| CN102881248B (en) * | 2012-09-29 | 2015-12-09 | 京东方科技集团股份有限公司 | Gate driver circuit and driving method thereof and display device |
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| CN103700354A (en) * | 2013-12-18 | 2014-04-02 | 合肥京东方光电科技有限公司 | Grid electrode driving circuit and display device |
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