CN111208416B - Integrated circuit process credibility detection method and circuit based on time-to-digital converter - Google Patents
Integrated circuit process credibility detection method and circuit based on time-to-digital converter Download PDFInfo
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318328—Generation of test inputs, e.g. test vectors, patterns or sequences for delay tests
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318392—Generation of test inputs, e.g. test vectors, patterns or sequences for sequential circuits
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Abstract
The invention belongs to the technical field of integrated circuit detection, and particularly relates to a method and a circuit for detecting the credibility of an integrated circuit process based on a time-to-digital converter, wherein the method comprises the following steps: acquiring a plurality of critical paths in a carrier circuit; adding a time-to-digital converter circuit on the carrier circuit according to the plurality of critical paths to obtain a carrier circuit added with a detection circuit; carrying out dynamic simulation on the carrier circuit added with the detection circuit to obtain a dynamic simulation result; obtaining an integrated circuit chip according to the carrier circuit added with the detection circuit, and performing path delay detection on the critical path of the carrier circuit in the integrated circuit chip to obtain a chip measurement result; and comparing the dynamic simulation result with the measurement result of the integrated circuit chip to obtain a judgment result. Has the advantages of small area and good concealment.
Description
Technical Field
The invention belongs to the technical field of integrated circuit detection, and particularly relates to a method and a circuit for detecting the credibility of an integrated circuit process based on a time-to-digital converter.
Background
Today's integrated circuit manufacturing chain is becoming global, and the production of an acceptable chip is often designed and manufactured by multiple companies. In addition, the use of some design tools and third party IP also speeds up the integrated circuit manufacturing process. However, hardware security is more vulnerable to hardware trojans in the integrated circuit supply chain, which may lead to leakage of confidential information or system failure. The technical trojan is one of the main attack modes of the hardware trojan, and the technical trojan is difficult to detect or is not considered as a malicious attack because the behavior of the technical trojan is gradual. The technology Trojan horse utilizes physical mechanisms such as large-amplitude excited Hot Carrier effect (HCI), gate Time Dependent Dielectric Breakdown (TDDB), Negative Bias Temperature Instability (NBTI) and the like to reduce the physical characteristics of the transistor, so that the conduction Time of the device is reduced, the service life is reduced, and even failure faults are generated.
Some reliable detection methods for integrated circuit manufacturing have been proposed. Generally, the detection method is divided into a physical effect detection structure and an aging delay detection structure. The physical effect detection is based on physical effects such as time-dependent breakdown, hot carriers, negative bias temperature instability, stress-induced leakage current, and electromigration. The physical effects are respectively aimed at, for example, the time-lapse breakdown effect is mainly aimed at the credibility of a gate dielectric process means of the MOS device; the NBTI effect mainly evaluates Shallow Trench Isolation (STI), ion implantation, Lightly Doped Drain (LDD) and uncontrolled plasma etching processes of a P-metal-oxide semiconductor (PMOS) device; evaluation of HCI effect N-metal-oxide semiconductor (NMOS) device ion implantation, LDD, and plasma etch process are not controlled. The process evaluation methods by means of physical effects are only suitable for evaluating the credibility of a certain process, generally, the test results are accurate only for a single device, and the method is not suitable for evaluating the performance of devices and circuits in a large-scale circuit. The layout of the measuring circuit manufactured based on the physical effects is obviously different from the layout of a normal digital circuit, so that the credible purpose of the detection integrated circuit is easily exposed, and the detection effect is limited.
The addition of the aging delay sensor is an effective technology for solving the delay change of a digital circuit, and the circuit failure early warning technology can realize the adjustment of parameters such as a clock and the like of circuit operation according to the delay fading rate and maintain the normal function of the circuit. The technology has the advantages that the circuit is not required to be damaged, environmental factors causing circuit degradation are not required to be comprehensively considered, and the detection accuracy is high. However, only craft trojans present on critical paths can be detected, while trojans mostly exist on non-critical paths for concealment. In addition, the aging sensor is arranged on an output node of the critical path, so that high time sequence, power and area overhead can be introduced, the delay margin of the critical path is reduced, and the circuit has time sequence faults.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a method and a circuit for detecting the credibility of an integrated circuit process based on a time-to-digital converter. The technical problem to be solved by the invention is realized by the following technical scheme:
the integrated circuit technology credibility detection method and circuit based on time-to-digital converter includes:
acquiring a plurality of critical paths in a carrier circuit;
adding a time-to-digital converter circuit on the carrier circuit according to the plurality of critical paths to obtain a carrier circuit added with a detection circuit;
carrying out dynamic simulation on the carrier circuit added with the detection circuit to obtain a dynamic simulation result;
obtaining an integrated circuit chip according to the carrier circuit added with the detection circuit, and performing path delay detection on the critical path of the carrier circuit in the integrated circuit chip to obtain a chip measurement result;
and comparing the dynamic simulation result with the measurement result of the integrated circuit chip to obtain a judgment result.
In one embodiment of the invention, obtaining a number of critical paths in a carrier circuit includes:
carrying out static time sequence analysis on the carrier circuit under the fastest process angle to obtain the delay of the longest path as a delay threshold;
carrying out static time sequence analysis on the carrier circuit under the slowest process angle to obtain a plurality of path delays;
and sequencing the plurality of path delays according to the size of the delay value, and if the path delay value is greater than the delay threshold value, taking the path corresponding to the path delay as a key path to further obtain a plurality of key paths.
In one embodiment of the present invention, adding a time-to-digital converter circuit on the carrier circuit according to the plurality of critical paths results in a carrier circuit added with a detection circuit, comprising:
the starting points of the plurality of critical paths are connected with the starting input end of the delay detection circuit, the end points of the critical paths are connected with the ending input end of the delay detection circuit, and the output end of the delay detection circuit is connected with the output port of the carrier circuit.
In an embodiment of the present invention, before performing dynamic simulation on the carrier circuit with the added detection circuit to obtain a dynamic simulation result, the method further includes:
carrying out static time sequence analysis on the carrier circuit added with the detection circuit to obtain a static time sequence analysis result;
and adjusting the distance between components and the load in the circuit according to the static time sequence analysis result, and ensuring that the influence of the time-to-digital converter circuit on the time delay of the plurality of key paths of the carrier circuit is minimum.
In an embodiment of the present invention, performing dynamic simulation on the carrier circuit with the detection circuit added thereto to obtain a dynamic simulation result includes:
dynamically simulating the plurality of key paths of the carrier circuit added with the detection circuit, and adding process deviation into a simulation environment of the dynamic simulation to obtain a plurality of key path delay simulation results;
counting the maximum value and the minimum value in the delay simulation results of the plurality of key paths to obtain the delay range of the key paths;
and dynamically simulating the plurality of key paths of the carrier circuit after the detection circuit is added, adding stress conditions such as temperature, clock duty ratio and the like into a simulation environment to simulate chip aging to obtain delay regression curves of the plurality of key paths, calculating regression slopes according to the delay regression curves, and calculating the regression slopes according to the delay regression curves to obtain a dynamic simulation result.
In an embodiment of the present invention, obtaining an integrated circuit chip according to the carrier circuit with the detection circuit added thereto, and performing path delay detection on the critical path of the carrier circuit in the integrated circuit chip to obtain a chip measurement result, includes:
inputting corresponding test excitation to the integrated circuit chip and activating signal inversion of the plurality of critical paths;
obtaining a delay value of a critical path from an output terminal of the integrated circuit chip;
respectively obtaining the delay decay curves of the critical paths of the integrated circuit chip according to the running time of the integrated circuit chip, and calculating the decay slope according to the delay decay curves.
In an embodiment of the present invention, comparing the dynamic simulation result with the measurement result of the integrated circuit chip to obtain a determination result includes:
judging whether the delay values of the plurality of key paths are in the path delay range of the dynamic simulation result, if so, carrying out the next step, otherwise, judging that the process of the integrated circuit chip in the production process is not credible, and simultaneously, the position of the key path is also the position of the integrated circuit chip with incredible process level;
judging whether the delay decay slopes of the plurality of key paths in the chip measurement result are smaller than the decay slope obtained in the dynamic simulation result, if so, determining that the process level of the chip in the production process is in a credible range; if not, the process of the integrated circuit chip in the production process is not credible, and meanwhile, the position of the critical path is also an incredible position of the process level on the integrated circuit chip.
The invention also provides a module of the integrated circuit process credible detection circuit based on the time-to-digital converter, which comprises an edge trigger module, a time measurement module, a result output module and a voltage source VDD which are connected in sequence, wherein two output input ends of the edge trigger module are respectively a start time input end start and an end time input end stop of the detection circuit:
the edge triggered module comprises a first exclusive-or gate, a first flip-flop, a first buffer unit, a second exclusive-or gate, a second flip-flop and a second buffer unit, wherein an input terminal of the first buffer unit and a first input terminal of the first exclusive-or gate are used as a start input terminal start of the edge triggered module, an input terminal of the second buffer unit and a first input terminal of the second exclusive-or gate are used as a stop input terminal stop of the edge triggered module, an output terminal of the first buffer unit is connected with a second input terminal of the first exclusive-or gate, an output terminal of the second buffer unit is connected with a second input terminal of the second exclusive-or gate, an output terminal of the first exclusive-or gate is connected with a clock terminal CLK1 of the first flip-flop, an output terminal of the second exclusive-or gate is connected with a clock terminal CLK2 of the second flip-flop, and a data input terminal D1 of the first flip-flop and a data input terminal D2 of the second flip-flop are both connected with the voltage source VDD, the output of the first flip-flop outputs a first rising edge time start1 to the time measurement module, and the output of the second flip-flop outputs a second rising edge time stop1 to the time measurement module.
In one embodiment of the invention, the time measurement module employs a gate level precision time-to-digital converter.
The invention has the beneficial effects that:
firstly, the time-to-digital converter circuit is used as the delay detection circuit, so that the problems that a large amount of area overhead is brought by adopting an aging sensor for detection, a scanning clock is difficult to realize and the like are effectively solved, and by introducing the time-to-digital converter to measure the on-chip delay, the realization mode is simple and the area overhead is reduced;
secondly, the invention adopts the time-to-digital converter as the detection circuit, the introduced layout has no obvious difference from the normal digital circuit layout, the concealment is better, and the purpose of the detection process is not exposed.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a schematic flow chart of a method for detecting the trustworthiness of an integrated circuit process based on a time-to-digital converter according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a carrier circuit with an added detection circuit in a trusted detection circuit for integrated circuit process based on time-to-digital converter according to an embodiment of the present invention;
FIG. 3 is a block diagram of an integrated circuit process confidence detection circuit based on a time-to-digital converter according to an embodiment of the present invention;
fig. 4 is a circuit diagram of an edge triggered module in a trusted detection circuit for integrated circuit process based on time-to-digital converter according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Referring to fig. 1, fig. 1 is a schematic flow chart of a method for detecting the integrated circuit process reliability based on a time-to-digital converter according to an embodiment of the present invention, including:
acquiring a plurality of critical paths in a carrier circuit;
adding a time-to-digital converter circuit on the carrier circuit according to the plurality of critical paths to obtain a carrier circuit added with a detection circuit;
carrying out dynamic simulation on the carrier circuit added with the detection circuit to obtain a dynamic simulation result;
obtaining an integrated circuit chip according to the carrier circuit added with the detection circuit, and performing path delay detection on the critical path of the carrier circuit in the integrated circuit chip to obtain a chip measurement result;
and comparing the dynamic simulation result with the measurement result of the integrated circuit chip to obtain a judgment result.
According to the invention, the time-to-digital converter circuit is used as the delay detection circuit, so that the problems of large area overhead caused by detection by an aging sensor, difficulty in realizing a scanning clock and the like are effectively solved, and by introducing the time-to-digital converter to measure the delay on the chip, the realization mode is simple and the area overhead is reduced; the invention adopts the time-to-digital converter as the detection circuit, the introduced layout has no obvious difference from the normal digital circuit layout, the concealment is better, and the purpose of the detection process can not be exposed.
In one embodiment of the invention, obtaining a number of critical paths in a carrier circuit includes:
carrying out static time sequence analysis on the carrier circuit under the fastest process angle to obtain the delay of the longest path as a delay threshold;
carrying out static time sequence analysis on the carrier circuit under the slowest process angle to obtain a plurality of path delays;
and sequencing the plurality of path delays according to the size of the delay value, and if the path delay value is greater than the delay threshold value, taking the path corresponding to the path delay as a key path to further obtain a plurality of key paths.
In an embodiment of the present invention, referring to fig. 2, fig. 2 is a schematic diagram of a carrier circuit with an added detection circuit in an integrated circuit process trusted detection circuit based on a time-to-digital converter according to an embodiment of the present invention, where the carrier circuit with the added detection circuit is obtained by adding the time-to-digital converter circuit on the carrier circuit according to a plurality of critical paths, and the carrier circuit includes:
the starting points of the plurality of critical paths are connected with the starting input end of the delay detection circuit, the end points of the critical paths are connected with the ending input end of the delay detection circuit, and the output end of the delay detection circuit is connected with the output port of the carrier circuit.
In an embodiment of the present invention, before performing dynamic simulation on the carrier circuit with the added detection circuit to obtain a dynamic simulation result, the method further includes:
carrying out static time sequence analysis on the carrier circuit added with the detection circuit to obtain a static time sequence analysis result;
and adjusting the distance between components and the load in the circuit according to the static time sequence analysis result, and ensuring that the influence of the time-to-digital converter circuit on the time delay of the plurality of key paths of the carrier circuit is minimum.
In an embodiment of the present invention, performing dynamic simulation on the carrier circuit with the detection circuit added thereto to obtain a dynamic simulation result includes:
dynamically simulating the plurality of key paths of the carrier circuit added with the detection circuit, and adding process deviation into a simulation environment of the dynamic simulation to obtain a plurality of key path delay simulation results;
counting the maximum value and the minimum value in the delay simulation results of the plurality of key paths to obtain the delay range of the key paths;
and dynamically simulating the plurality of key paths of the carrier circuit after the detection circuit is added, adding stress conditions such as temperature, clock duty ratio and the like into a simulation environment to simulate chip aging to obtain delay regression curves of the plurality of key paths, calculating regression slopes according to the delay regression curves, and calculating the regression slopes according to the delay regression curves to obtain a dynamic simulation result.
In an embodiment of the present invention, obtaining an integrated circuit chip according to the carrier circuit with the detection circuit added thereto, and performing path delay detection on the critical path of the carrier circuit in the integrated circuit chip to obtain a chip measurement result, includes:
inputting corresponding test excitation to the integrated circuit chip and activating signal inversion of the plurality of critical paths;
obtaining a delay value of a critical path from an output terminal of the integrated circuit chip;
respectively obtaining the delay decay curves of the critical paths of the integrated circuit chip according to the running time of the integrated circuit chip, and calculating the decay slope according to the delay decay curves.
In an embodiment of the present invention, comparing the dynamic simulation result with the measurement result of the integrated circuit chip to obtain a determination result includes:
judging whether the delay values of the plurality of key paths are in the path delay range of the dynamic simulation result, if so, carrying out the next step, otherwise, judging that the process of the integrated circuit chip in the production process is not credible, and simultaneously, the position of the key path is also the position of the integrated circuit chip with incredible process level;
judging whether the delay decay slopes of the plurality of key paths in the chip measurement result are smaller than the decay slope obtained in the dynamic simulation result, if so, determining that the process level of the chip in the production process is in a credible range; if not, the process of the integrated circuit chip in the production process is not credible, and meanwhile, the position of the critical path is also an incredible position of the process level on the integrated circuit chip.
Referring to fig. 3, fig. 3 is a schematic block diagram of an integrated circuit process trusted detection circuit based on a time-to-digital converter according to an embodiment of the present invention, including an edge triggering module, a time measuring module, a result output module, and a voltage source VDD, which are connected in sequence, where two input ends of an output of the edge triggering module are a start time input end start and a stop time input end stop of the detection circuit, respectively:
referring to fig. 4, fig. 4 is a circuit diagram of an edge triggered module in an integrated circuit process trusted detection circuit based on a time-to-digital converter according to an embodiment of the present invention, where the edge triggered module includes a first xor gate, a first flip-flop, a first buffer unit, a second xor gate, a second flip-flop, and a second buffer unit, an input end of the first buffer unit and a first input end of the first xor gate are used as a start input end start of the edge triggered module, an input end of the second buffer unit and a first input end of the second xor gate are used as a stop input end stop of the edge triggered module, an output end of the first buffer unit is connected to a second input end of the first xor gate, an output end of the second buffer unit is connected to a second input end of the second xor gate, an output end of the first xor gate is connected to a clock end CLK1 of the first flip-flop, the output end of the second exclusive-or gate is connected with the clock end CLK2 of the second flip-flop, the data input end D1 of the first flip-flop and the data input end D2 of the second flip-flop are both connected with the voltage source VDD, the output end of the first flip-flop outputs a first rising edge time start1 to the time measurement module, and the output end of the second flip-flop outputs a second rising edge time stop1 to the time measurement module.
In one embodiment of the invention, the time measurement module employs a gate level precision time-to-digital converter.
Specifically, two input ports of the time-to-digital converter respectively receive the first rising edge time start1 and the second rising edge time stop1, calculate a delay difference between the first rising edge time start1 and the second rising edge time stop1, and output the delay difference to the result output module.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (8)
1. The integrated circuit process credibility detection method based on the time-to-digital converter is characterized by comprising the following steps:
acquiring a plurality of critical paths in a carrier circuit;
adding a time-to-digital converter circuit on the carrier circuit according to the plurality of critical paths to obtain a carrier circuit added with a detection circuit;
carrying out dynamic simulation on the carrier circuit added with the detection circuit to obtain a dynamic simulation result;
obtaining an integrated circuit chip according to the carrier circuit added with the detection circuit, and performing path delay detection on the critical path of the carrier circuit in the integrated circuit chip to obtain a chip measurement result;
comparing the dynamic simulation result with the measurement result of the integrated circuit chip to obtain a judgment result;
and dynamically simulating the carrier circuit added with the detection circuit to obtain a dynamic simulation result, wherein the dynamic simulation result comprises the following steps:
dynamically simulating the plurality of key paths of the carrier circuit added with the detection circuit, and adding process deviation into a simulation environment of the dynamic simulation to obtain a plurality of key path delay simulation results;
counting the maximum value and the minimum value in the delay simulation results of the plurality of key paths to obtain the delay range of the key paths;
and dynamically simulating the plurality of key paths of the carrier circuit after the detection circuit is added, adding a temperature and clock duty ratio stress condition simulation chip into a simulation environment for aging to obtain delay decline curves of the plurality of key paths, calculating decline slopes according to the delay decline curves, and calculating the decline slopes according to the delay decline curves to obtain a dynamic simulation result.
2. The integrated circuit process confidence detection method based on time-to-digital converter as claimed in claim 1, characterized in that, acquiring several critical paths in the carrier circuit comprises:
carrying out static time sequence analysis on the carrier circuit under the fastest process angle to obtain the delay of the longest path as a delay threshold;
carrying out static time sequence analysis on the carrier circuit under the slowest process angle to obtain a plurality of path delays;
and sequencing the plurality of path delays according to the size of the delay value, and if the path delay value is greater than the delay threshold value, taking the path corresponding to the path delay as a key path to further obtain a plurality of key paths.
3. The method of claim 1, wherein adding a time-to-digital converter circuit to the carrier circuit according to the plurality of critical paths results in a carrier circuit with an added detection circuit, comprising:
the starting points of the plurality of critical paths are connected with the starting input end of the time-to-digital converter circuit, the end points of the critical paths are connected with the ending input end of the time-to-digital converter circuit, and the output end of the time-to-digital converter circuit is connected with the output port of the carrier circuit.
4. The integrated circuit process credible detection method based on time-to-digital converter as claimed in claim 1, wherein before the dynamic simulation of the carrier circuit added with the detection circuit to obtain the dynamic simulation result, further comprising:
carrying out static time sequence analysis on the carrier circuit added with the detection circuit to obtain a static time sequence analysis result;
and adjusting the distance between components and the load in the circuit according to the static time sequence analysis result, and ensuring that the influence of the time-to-digital converter circuit on the time delay of the plurality of key paths of the carrier circuit is minimum.
5. The integrated circuit process confidence detection method based on time-to-digital converter according to claim 1, wherein obtaining an integrated circuit chip according to the carrier circuit added with the detection circuit, and performing path delay detection on the critical path of the carrier circuit in the integrated circuit chip to obtain a chip measurement result comprises:
inputting corresponding test excitation to the integrated circuit chip and activating signal inversion of the plurality of critical paths;
obtaining a delay value of a critical path from an output terminal of the integrated circuit chip;
respectively obtaining the delay decay curves of the critical paths of the integrated circuit chip according to the running time of the integrated circuit chip, and calculating the decay slope according to the delay decay curves.
6. The integrated circuit process credible detection method based on time-to-digital converter as claimed in claim 1, wherein comparing the dynamic simulation result with the integrated circuit chip measurement result to obtain a judgment result comprises:
judging whether the delay values of the plurality of key paths are in the path delay range of the dynamic simulation result, if so, carrying out the next step, otherwise, judging that the process of the integrated circuit chip in the production process is not credible, and simultaneously, the position of the key path is also the position of the integrated circuit chip with incredible process level;
judging whether the delay decay slopes of the plurality of key paths in the chip measurement result are smaller than the decay slope obtained in the dynamic simulation result, if so, determining that the process level of the chip in the production process is in a credible range; if not, the process of the integrated circuit chip in the production process is not credible, and meanwhile, the position of the critical path is also an incredible position of the process level on the integrated circuit chip.
7. The integrated circuit process credible detection circuit based on the time-to-digital converter is characterized by comprising an edge trigger module, a time measurement module, a result output module and a voltage source (VDD) which are sequentially connected, wherein two input ends of the edge trigger module are respectively a start time input end (start) and an end time input end (stop) of the detection circuit:
the edge trigger module comprises a first exclusive-or gate, a first flip-flop, a first buffer unit, a second exclusive-or gate, a second flip-flop and a second buffer unit, wherein an input end of the first buffer unit and a first input end of the first exclusive-or gate are used as a starting input end (start) of the edge trigger module, an input end of the second buffer unit and a first input end of the second exclusive-or gate are used as a stopping input end (stop) of the edge trigger module, an output end of the first buffer unit is connected with a second input end of the first exclusive-or gate, an output end of the second buffer unit is connected with a second input end of the second exclusive-or gate, an output end of the first exclusive-or gate is connected with a clock end (CLK1) of the first flip-flop, an output end of the second exclusive-or gate is connected with a clock end (CLK2) of the second flip-flop, and a data input end (D1) of the first flip-flop and a data input end (D2) of the second flip-flop are connected with each other The output terminal of the first flip-flop outputs a first rising edge time (start1) to the time measurement module, and the output terminal of the second flip-flop outputs a second rising edge time (stop1) to the time measurement module.
8. The integrated circuit process confidence detection circuit based on time-to-digital converter as claimed in claim 7, wherein the time measurement module employs a gate-level precision time-to-digital converter.
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