CN111190644A - Embedded Flash on-chip read instruction hardware acceleration method and device - Google Patents
Embedded Flash on-chip read instruction hardware acceleration method and device Download PDFInfo
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Abstract
The invention discloses a hardware acceleration method and device for an embedded Flash chip read instruction. Wherein the method comprises the following steps: classifying the instructions at the front end of a processor pipeline based on instruction predecoding and an instruction information classifier by using a preset tightly-coupled on-chip read instruction hardware accelerator architecture; accelerating hardware of the first type of instruction based on instruction bit width expansion and a hardware prefetching mechanism; hardware acceleration of the second type of instruction based on a high-precision hybrid branch predictor mechanism, a set associative cache mechanism; constructing a parameterized ESL system model and a hardware circuit generator based on HLS, and performing performance analysis on key components of the system on chip; and adjusting the instruction reading speed on the embedded Flash chip in real time through a main frequency hardware detector and a hardware self-adaptive dynamic switching strategy. By adopting the method, the system on chip can be ensured to obtain the optimal instruction reading speed on the embedded Flash chip in different application scenes such as high frequency, low frequency and the like, and the performance of the system on chip is effectively improved.
Description
Technical Field
The embodiment of the invention relates to the field of computer processors, in particular to a hardware acceleration method and device for a read instruction on an embedded Flash chip, and further relates to electronic equipment and a computer-readable storage medium.
Background
With the rapid development of computer technology, fast and efficient computer processors have become the focus of research in this field. Among them, on-chip eFlash (i.e., embedded Flash) is being widely used as a nonvolatile memory module for instructions and data in the field of low-power-consumption embedded chip SoC design. The processor is mainly responsible for tasks such as control, operating system platform and general signal processing, and the eFlash is used for storing instructions and data. The processor needs to access the eFlash to obtain the required instructions and data to complete the corresponding task processing operation. The processor typically accesses instructions more frequently. Compared with the performance of a processor which can be improved by instruction level parallelism, superscalar design and a large number of registers, the performance of the eFlash can be improved only by a few methods such as process improvement. Therefore, with the improvement of the performance of the processor, the on-chip instruction fetching speed of the eFlash gradually becomes the bottleneck of the performance of the SoC system, and the overall performance of the SoC is directly influenced and limited by the speed of the instruction fetching speed of the eFlash.
The industry typically employs an acceleration scheme design based on cache principle to narrow the performance gap between the processor and the memory. The buffer memory has the advantages that: under the condition of high hit rate, the cache can obviously improve the reading performance of the eFlash, reduce the access of the eFlash and reduce the power consumption of the system, but the cache also has the obvious defects that: 1. the cache capacity is large, the cost is high, and large hardware overhead can be brought; 2. in an application scenario where the cycle exceeds the cache capacity and the cycle is less, the cache hit rate is low and the acceleration performance is not obvious.
With the increasing diversification of application scenarios such as AIoT, optimal performance acceleration cannot be obtained by only relying on simple prefetching or caching. Therefore, the research on how to improve the on-chip instruction reading speed of the eFlash has important significance on improving the overall performance of the SoC system.
Disclosure of Invention
Therefore, the embodiment of the invention provides a hardware acceleration method for an embedded Flash on-chip instruction reading, which aims to solve the problem that the acceleration performance aiming at the instruction reading speed on the embedded Flash is not obvious in the prior art and the actual requirements of the current user cannot be met.
In order to achieve the above object, the embodiments of the present invention provide the following technical solutions:
in a first aspect, an embodiment of the present invention provides a hardware acceleration method for a read instruction on an embedded Flash chip, including: classifying the instructions at the front end of a processor assembly line by utilizing a preset tightly-coupled on-chip instruction reading hardware accelerator architecture based on instruction predecoding and an instruction information classifier; accelerating hardware of the first type of instruction based on preset instruction bit width expansion and a hardware prefetching mechanism; accelerating the hardware of the second type of instruction based on a preset high-precision hybrid branch predictor mechanism and a set associative cache mechanism; constructing a parameterized ESL system model and a hardware circuit generator based on HLS, and performing performance analysis on key components of the embedded Flash on-chip system; and adjusting the instruction reading speed on the embedded Flash chip in real time at a hardware level through a preset main frequency hardware detector and a hardware self-adaptive dynamic switching strategy.
Further, the method for accelerating the hardware of the read instruction on the embedded Flash chip further comprises the following steps: triggering a preset main frequency hardware detector; and establishing an acceleration strategy according to the main frequency hardware detector and the time sequence of the read operation on the embedded Flash chip, and accelerating the read instruction operation on the embedded Flash chip based on the acceleration strategy.
Further, the making of an acceleration strategy according to the main frequency hardware detector and the time sequence of the read operation on the embedded Flash chip specifically includes: judging the frequency type of a master frequency clock of the system on the embedded Flash chip according to the master frequency hardware detector and the time sequence of the read operation on the embedded Flash chip; if the master frequency clock of the system on the embedded Flash chip is low frequency, reading the instruction on the embedded Flash chip by a single clock period through a read operation acceleration strategy of an embedded Flash controller; if the master frequency clock of the system on the embedded Flash chip is high frequency, determining the type of the instruction executed on the embedded Flash chip through the zone bit of the instruction classifier; and if the instruction type is a sequential instruction, reading an acceleration strategy by adopting the established sequential instruction, and if the instruction type is a jump instruction, reading the acceleration strategy by adopting the established jump instruction sheet.
Further, the first type of instruction is a sequential instruction.
Further, the second type instruction is a jump instruction.
In a second aspect, an embodiment of the present invention further provides an embedded Flash chip read instruction hardware acceleration apparatus, including: the instruction information classification unit is used for classifying the instructions at the front end of the processor pipeline based on instruction predecoding and an instruction information classifier by utilizing a preset tightly-coupled on-chip read instruction hardware accelerator architecture; the first hardware acceleration unit is used for accelerating the hardware of the first type of instruction based on preset instruction bit width expansion and a hardware prefetching mechanism; the second hardware acceleration and closed-loop feedback unit is used for accelerating the hardware of the second type of instruction based on a preset high-precision hybrid branch predictor mechanism and a set-associative cache mechanism; constructing a parameterized ESL system model and a hardware circuit generator based on HLS, and performing performance analysis on key components of the embedded Flash on-chip system; and the adjusting unit is used for adjusting the instruction reading speed on the embedded Flash chip in real time through a preset main frequency hardware detector and a hardware self-adaptive dynamic switching strategy.
Furthermore, the hardware acceleration device for reading instructions on the embedded Flash chip further comprises: the main frequency hardware detector triggering unit is used for triggering the preset main frequency hardware detector; and the acceleration strategy determining unit is used for making an acceleration strategy according to the main frequency hardware detector and the time sequence of the read operation on the embedded Flash chip and accelerating the read instruction operation on the embedded Flash chip based on the acceleration strategy.
Further, the acceleration policy determining unit is specifically configured to: if the master frequency clock of the system on the embedded Flash chip is low frequency, reading the instruction on the embedded Flash chip by a single clock period through a read operation acceleration strategy of an embedded Flash controller; if the master frequency clock of the system on the embedded Flash chip is high frequency, determining the type of the instruction executed on the embedded Flash chip through the zone bit of the instruction classifier; and if the instruction type is a sequential instruction, reading an acceleration strategy by adopting the established sequential instruction, and if the instruction type is a jump instruction, reading the acceleration strategy by adopting the established jump instruction sheet.
Further, the first type of instruction is a sequential instruction.
Further, the second type instruction is a jump instruction.
In a third aspect, an embodiment of the present invention further provides an electronic device, including: a processor and a memory; the memory is used for storing a program for executing the hardware acceleration method of the read instruction on the embedded Flash chip, and the electronic equipment is powered on and executes any one of the hardware acceleration methods for executing the read instruction on the embedded Flash chip after running the program for executing the hardware acceleration method of the read instruction on the embedded Flash chip through the processor.
In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, where the computer-readable storage medium contains one or more program instructions, and the one or more program instructions are configured to execute any one of the above hardware acceleration methods for executing an embedded Flash read-on-chip instruction.
By adopting the hardware acceleration method for the embedded Flash on-chip reading instruction, the system on the chip can be ensured to obtain the optimal instruction reading speed on the embedded Flash on-chip at both high frequency and low frequency, and the system performance improvement under different scene requirements in embedded application is realized.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It should be apparent that the drawings in the following description are merely exemplary, and that other embodiments can be derived from the drawings provided by those of ordinary skill in the art without inventive effort.
FIG. 1 is a flowchart of a hardware acceleration method for a read instruction on an embedded Flash chip according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a hardware acceleration apparatus for reading instructions on an embedded Flash chip according to an embodiment of the present invention;
fig. 3 is a schematic diagram of an electronic device according to an embodiment of the present invention;
fig. 4 is a flowchart of an acceleration strategy selected and formulated in a hardware acceleration method for a read instruction on an embedded Flash chip according to an embodiment of the present invention.
Detailed Description
The present invention is described in terms of particular embodiments, other advantages and features of the invention will become apparent to those skilled in the art from the following disclosure, and it is to be understood that the described embodiments are merely exemplary of the invention and that it is not intended to limit the invention to the particular embodiments disclosed. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The following describes an embodiment of the embedded Flash chip read instruction hardware acceleration method in detail based on the invention. As shown in fig. 1, which is a flowchart of a hardware acceleration method for a read instruction on an embedded Flash chip according to an embodiment of the present invention, a specific implementation process includes the following steps:
step S101: and classifying the instructions at the front end of the processor pipeline by utilizing a preset tightly-coupled on-chip instruction reading hardware accelerator architecture based on instruction predecoding and an instruction information classifier.
In the embodiment of the invention, the instruction at the front end of the processor pipeline can be classified by using a preset tightly-coupled on-chip read instruction hardware accelerator architecture, namely, by using a preset tightly-coupled Flash on-chip read instruction hardware accelerator architecture and based on instruction predecoding and an instruction information classifier.
Step S102: and accelerating the hardware of the first type of instruction based on preset instruction bit width expansion and a hardware prefetching mechanism.
After the instructions at the front end of the processor pipeline are classified in step S101, the instructions at the front end of the processor pipeline can be classified based on the instruction predecoding and the instruction information classifier by using a preset tightly coupled on-chip instruction reading hardware accelerator architecture in this step. Wherein the first type of instruction may be a sequential instruction.
For the first type of instruction (i.e., sequential instruction): in the specific implementation process, the hardware accelerator splices and expands a plurality of embedded Flash slices through bit width to realize single access to the embedded Flash slices and read out a plurality of instructions. The embedded Flash read operation of the sequential instruction can reach 16 times of speed-up ratio at most. Furthermore, the hardware can prefetch the instruction in advance when the fetch of the CPU processor stops by adding a proper Buffer through a hardware prefetching strategy, so that the delay caused by the Flash sequential instruction on a single reading chip is hidden. It should be noted that the embedded Flash slices may generally refer to 24 embedded Flash slices, and are not specifically limited herein.
Step S103: accelerating the hardware of the second type of instruction based on a preset high-precision hybrid branch predictor mechanism and a set associative cache mechanism; and constructing a parameterized ESL system model and a hardware circuit generator based on HLS, and performing performance analysis on the key components of the embedded Flash on-chip system.
After hardware acceleration of the first type of instruction in step S102, hardware acceleration of the second type of instruction may be performed in this step based on a preset high-precision hybrid branch predictor mechanism, a set associative cache mechanism. In addition, a parameterized ESL system model and a hardware circuit generator can be constructed based on HLS, performance analysis is carried out on key components of the embedded Flash chip system, and closed-loop feedback is further achieved. Wherein the second type of instruction may be referred to as a jump instruction.
For the second type of instruction (i.e., a jump instruction): in the specific implementation process, the proportion of the area of the CPU processor in the embedded Flash system-on-chip is smaller, so that the appropriate area can be properly increased to greatly improve the performance of the system-on-chip. In the embodiment of the invention, the branch prediction accuracy of about 99.1 percent can be realized by a high-precision mixed branch predictor mechanism formed by a preset TAGE branch predictor, a Loop predictor and the like. In step S101, the first stage of the tightly coupled read instruction hardware accelerator architecture reduces instruction misses caused by branch mispredictions.
And adopting a branch cache strategy for the jump instruction decoded by the preset instruction information analyzer, and continuing to perform next prefetching operation by reducing access delay caused by prefetching failure and correcting a prefetching address, thereby realizing acceleration of on-chip reading instruction operation of the embedded Flash.
In addition, in the process of constructing a parameterized ESL system model and a parameterized hardware circuit generator based on HLS and analyzing the performance of key components of the embedded Flash chip, the accuracy and the simulation speed of the hardware acceleration device for reading instructions on the embedded Flash chip are the key points of the performance analysis of the ESL system model.
In the embodiment of the present invention, the constructing a parameterized electronic system Level design ESL system model and a hardware circuit generator based on high-Level integrated hls (high Level synthesis) may specifically include: carrying out parameterization modeling on ESL of the processor through a high-level language, and converting the ESL into RTL codes through an HLS hardware generator; further, RTL code of the high-performance core is used as an ESL system model for CPU processor performance analysis. A special performance monitoring unit realized by a plurality of hardware counters can be added outside the high-performance core to realize the performance analysis of the processor in the micro-architecture level; the method comprises the steps of counting events of a series of behaviors of an instruction fetching component, a pre-decoding component, a branch predictor component, an instruction decoding component, an instruction distribution component and the like of a processor through a preset performance monitoring unit, outputting a counting result to a key data summarizing component, and realizing closed-loop feedback of performance analysis of a key component or a data path.
Step S104: and adjusting the instruction reading speed on the embedded Flash chip through a preset main frequency hardware detector and a hardware self-adaptive dynamic switching strategy.
After accelerating the hardware of the second type of instruction in step S103 and performing performance analysis on the key components of the system on the embedded Flash chip, in step S104, a hardware-level dynamic real-time adjustment may be performed on the instruction reading speed on the embedded Flash chip by using a preset dominant frequency hardware detector and a hardware adaptive dynamic switching policy.
Fig. 4 is a flowchart of an acceleration strategy selected and formulated in a hardware acceleration method for a read instruction on an embedded Flash chip according to an embodiment of the present invention.
In the embodiment of the invention, the method also comprises the steps of triggering the preset main frequency hardware detector, making an acceleration strategy according to the main frequency hardware detector and the time sequence of the read operation on the embedded Flash chip, and accelerating the read instruction operation on the embedded Flash chip based on the acceleration strategy. Wherein, the establishing of the acceleration strategy according to the main frequency hardware detector and the time sequence of the read operation on the embedded Flash chip may include: judging the frequency type of a master frequency clock of the system on the embedded Flash chip according to the master frequency hardware detector and the time sequence of the read operation on the embedded Flash chip; if the master frequency clock of the system on the embedded Flash chip is low frequency, reading the instruction on the embedded Flash chip by a single clock period through a read operation acceleration strategy of an embedded Flash controller; if the master frequency clock of the system on the embedded Flash chip is high frequency, determining the type of the instruction executed on the embedded Flash chip through the zone bit of the instruction classifier; and if the instruction type is a sequential instruction, reading an acceleration strategy by adopting the established sequential instruction, and if the instruction type is a jump instruction or other instructions, reading the acceleration strategy by adopting the established jump instruction or other instruction sheets.
Specifically, after the system on the Flash chip is initialized, a main frequency hardware detector is triggered and started, and a proper acceleration strategy is formulated according to the main frequency and the read operation time sequence of the embedded Flash chip. If the main frequency clock of the system on the Flash chip is low frequency, after a bus of an interconnection network on the Flash chip sends a read address and a read request through an embedded Flash controller read operation acceleration strategy, an AE control signal of the embedded Flash is pulled up by the rising edge of the next clock, and AE is pulled down by the falling edge of the clock, so that the embedded Flash chip completes the read operation in one clock cycle, and the reading of the on-chip instruction in a single clock cycle is realized. And if the main frequency clock of the system on the Flash chip is high frequency, determining the type of the instruction executed on the Flash chip through the zone bit of the instruction classifier. If the instruction type is a sequential instruction, reading an acceleration strategy on a sequential instruction sheet; and if the instruction type is a jump instruction, adopting a jump instruction sheet to read an acceleration strategy.
By adopting the hardware acceleration method for the embedded Flash on-chip reading instruction, the system on the chip can be ensured to obtain the optimal instruction reading speed on the embedded Flash on-chip at both high frequency and low frequency, and the system performance improvement under different scene requirements in embedded application is realized. Through hardware self-adaptive dynamic switching, the optimal instruction reading speed on the embedded Flash chip is obtained, and the system performance improvement under different scene requirements in embedded application is realized.
Corresponding to the method for accelerating the hardware of the read instruction on the embedded Flash chip, the invention also provides a device for accelerating the hardware of the read instruction on the embedded Flash chip. Because the embodiment of the device is similar to the embodiment of the method, the description is relatively simple, and for the relevant points, reference may be made to the description of the embodiment of the method, and the embodiment of the hardware acceleration device for the read instruction on the embedded Flash chip described below is only illustrative. Fig. 2 is a schematic diagram of a hardware acceleration apparatus for reading instructions on an embedded Flash chip according to an embodiment of the present invention.
The invention relates to an embedded Flash on-chip read instruction hardware accelerating device, which comprises the following parts:
the instruction information classification unit 201 is configured to classify an instruction at the front end of a processor pipeline based on an instruction predecoding and an instruction information classifier by using a preset tightly coupled on-chip read instruction hardware accelerator architecture.
The first hardware acceleration unit 202 is configured to accelerate hardware of the first type of instruction based on a preset instruction bit width extension and a hardware prefetching mechanism.
After the instruction information classification unit 201 classifies the instruction at the front end of the processor pipeline, the first hardware acceleration unit 202 may utilize a preset tightly coupled on-chip read instruction hardware accelerator architecture to classify the instruction at the front end of the processor pipeline based on instruction predecoding and an instruction information classifier. Wherein the first type of instruction may be a sequential instruction.
For the first type of instruction (i.e., sequential instruction): in the specific implementation process, the hardware accelerator splices and expands a plurality of embedded Flash slices through bit width to realize single access to the embedded Flash slices and read out a plurality of instructions. The embedded Flash read operation of the sequential instruction can reach 16 times of speed-up ratio at most. Furthermore, the hardware can prefetch the instruction in advance when the fetch of the CPU processor stops by adding a proper Buffer through a hardware prefetching strategy, so that the delay caused by the Flash sequential instruction on a single reading chip is hidden. It should be noted that the embedded Flash slices may generally refer to 24 embedded Flash slices, and are not specifically limited herein.
A second hardware acceleration and closed-loop feedback unit 203, configured to accelerate hardware of a second type of instruction based on a preset high-precision hybrid branch predictor mechanism and a set-associative cache mechanism; and constructing a parameterized ESL system model and a hardware circuit generator based on HLS, and performing performance analysis on the key components of the embedded Flash on-chip system.
After the hardware acceleration of the first type of instruction in the first hardware acceleration unit 202, the hardware acceleration of the second type of instruction may be performed in the second hardware acceleration and closed-loop feedback unit 203 based on a predetermined high-precision hybrid branch predictor mechanism, a set-associative cache mechanism. In addition, a parameterized ESL system model and a hardware circuit generator can be constructed based on HLS, performance analysis is carried out on key components of the embedded Flash chip system, and closed-loop feedback is further achieved. The second type of instruction may refer to a jump instruction, or may refer to other instructions such as a non-sequential instruction.
And the second hardware acceleration and closed-loop feedback unit 203 is used for adjusting the instruction reading speed on the embedded Flash chip through a preset dominant frequency hardware detector and a hardware self-adaptive dynamic switching strategy.
After accelerating the hardware of the second type of instruction and performing performance analysis on the key components of the system on the embedded Flash chip in step S103, the instruction reading speed on the embedded Flash chip can be adjusted in the adjusting unit 204 through a preset dominant frequency hardware detector and a hardware adaptive dynamic switching strategy.
In the embodiment of the invention, the method also comprises the steps of triggering the preset main frequency hardware detector, making an acceleration strategy according to the main frequency hardware detector and the time sequence of the read operation on the embedded Flash chip, and accelerating the read instruction operation on the embedded Flash chip based on the acceleration strategy. Wherein, the establishing of the acceleration strategy according to the main frequency hardware detector and the time sequence of the read operation on the embedded Flash chip may include: judging the frequency type of a master frequency clock of the system on the embedded Flash chip according to the master frequency hardware detector and the time sequence of the read operation on the embedded Flash chip; if the master frequency clock of the system on the embedded Flash chip is low frequency, reading the instruction on the embedded Flash chip by a single clock period through a read operation acceleration strategy of an embedded Flash controller; if the master frequency clock of the system on the embedded Flash chip is high frequency, determining the type of the instruction executed on the embedded Flash chip through the zone bit of the instruction classifier; and if the instruction type is a sequential instruction, reading an acceleration strategy by adopting the established sequential instruction, and if the instruction type is a jump instruction, reading the acceleration strategy by adopting the established jump instruction sheet.
By adopting the hardware accelerating device for the embedded Flash on-chip reading instruction, the system on chip can be ensured to obtain the optimal instruction reading speed on the embedded Flash on-chip at high and low frequencies, and the system performance improvement under different scene requirements in embedded application is realized.
Corresponding to the method for accelerating the hardware of the read instruction on the embedded Flash chip, the invention also provides electronic equipment. Since the embodiment of the electronic device is similar to the above method embodiment, the description is relatively simple, and please refer to the description of the above method embodiment, and the electronic device described below is only schematic. Fig. 3 is a schematic view of an electronic device according to an embodiment of the present invention.
The electronic device specifically includes: a processor 301 and a memory 302; the memory 302 is configured to run one or more program instructions, and is configured to store a processor-related program, and after the electronic device is powered on and runs the related program through the processor 301, the hardware acceleration method for the read instruction on the embedded Flash chip is executed. The electronic device of the present invention may be a program execution device in a computer.
Corresponding to the hardware acceleration method of the read instruction on the embedded Flash chip, the invention also provides a computer storage medium. Since the embodiment of the computer storage medium is similar to the above method embodiment, the description is simple, and please refer to the description of the above method embodiment, and the computer storage medium described below is only schematic.
The computer storage medium contains one or more program instructions, and the one or more program instructions are used for executing the embedded Flash on-chip reading instruction hardware acceleration method.
In an embodiment of the invention, the processor or processor module may be an integrated circuit chip having signal processing capabilities. The processor may be a general purpose processor, an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other Programmable logic device.
The various methods, steps and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the embodiments of the present invention may be embodied directly in the hardware-dependent processor pipeline, or in a combination of hardware and software modules within the processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The processor reads the information in the storage medium and completes the steps of the method in combination with the hardware.
The storage medium may be a memory, for example, which may be volatile memory or nonvolatile memory, or which may include both volatile and nonvolatile memory.
The nonvolatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable PROM (EEPROM), or a flash Memory.
The volatile Memory may be a Random Access Memory (RAM) which serves as an external cache. By way of example and not limitation, many forms of RAM are available, such as Static random access memory (Static RAM, SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), synclink DRAM (SLDRAM), and Direct Rambus RAM (DRRAM).
The storage media described in connection with the embodiments of the invention are intended to comprise, without being limited to, these and any other suitable types of memory.
Those skilled in the art will appreciate that the functionality described in the present invention may be implemented in a combination of hardware and software in one or more of the examples described above. When software is applied, the corresponding functionality may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.
The above-mentioned embodiments, objects, technical solutions and advantages of the present invention are further described in detail, it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made on the basis of the technical solutions of the present invention should be included in the scope of the present invention.
Claims (10)
1. A hardware acceleration method for reading instructions on an embedded Flash chip is characterized by comprising the following steps:
classifying the instructions at the front end of a processor assembly line by utilizing a preset tightly-coupled on-chip instruction reading hardware accelerator architecture based on instruction predecoding and an instruction information classifier;
accelerating hardware of the first type of instruction based on preset instruction bit width expansion and a hardware prefetching mechanism;
accelerating the hardware of the second type of instruction based on a preset high-precision hybrid branch predictor mechanism and a set associative cache mechanism; constructing a parameterized ESL system model and a hardware circuit generator based on HLS, and performing performance analysis on key components of the embedded Flash on-chip system;
and adjusting the instruction reading speed on the embedded Flash chip in real time at a hardware level through a preset main frequency hardware detector and a hardware self-adaptive dynamic switching strategy.
2. The embedded Flash on-chip read instruction hardware acceleration method of claim 1, further comprising:
triggering a preset main frequency hardware detector;
and establishing an acceleration strategy according to the main frequency hardware detector and the time sequence of the read operation on the embedded Flash chip, and accelerating the read instruction operation on the embedded Flash chip based on the acceleration strategy.
3. The method for accelerating the hardware of the read instruction on the embedded Flash chip according to claim 2, wherein the step of formulating an acceleration strategy according to the main frequency hardware detector and the time sequence of the read operation on the embedded Flash chip specifically comprises the steps of:
judging the frequency type of a master frequency clock of the system on the embedded Flash chip according to the master frequency hardware detector and the time sequence of the read operation on the embedded Flash chip;
if the master frequency clock of the system on the embedded Flash chip is low frequency, reading the instruction on the embedded Flash chip by a single clock period through a read operation acceleration strategy of an embedded Flash controller;
if the master frequency clock of the system on the embedded Flash chip is high frequency, determining the type of the instruction executed on the embedded Flash chip through the zone bit of the instruction classifier; and if the instruction type is a sequential instruction, reading an acceleration strategy by adopting the established sequential instruction, and if the instruction type is a jump instruction, reading the acceleration strategy by adopting the established jump instruction sheet.
4. The embedded Flash on-chip instruction hardware acceleration method of claim 1, characterized in that, the first type instruction is a sequential instruction.
5. The embedded Flash on-chip read instruction hardware acceleration method of claim 1, characterized in that the second type instruction is a jump instruction.
6. An embedded Flash on-chip read instruction hardware accelerator, comprising:
the instruction information classification unit is used for classifying the instructions at the front end of the processor pipeline based on instruction predecoding and an instruction information classifier by utilizing a preset tightly-coupled on-chip read instruction hardware accelerator architecture;
the first hardware acceleration unit is used for accelerating the hardware of the first type of instruction based on preset instruction bit width expansion and a hardware prefetching mechanism;
the second hardware acceleration and closed-loop feedback unit is used for accelerating the hardware of the second type of instruction based on a preset high-precision hybrid branch predictor mechanism and a set-associative cache mechanism; constructing a parameterized ESL system model and a hardware circuit generator based on HLS, and performing performance analysis on key components of the embedded Flash on-chip system;
and the adjusting unit is used for adjusting the instruction reading speed on the embedded Flash chip in real time at a hardware level through a preset main frequency hardware detector and a hardware self-adaptive dynamic switching strategy.
7. The embedded Flash on-chip read instruction hardware acceleration device of claim 6, further comprising:
the main frequency hardware detector triggering unit is used for triggering the preset main frequency hardware detector;
and the acceleration strategy determining unit is used for making an acceleration strategy according to the main frequency hardware detector and the time sequence of the read operation on the embedded Flash chip and accelerating the read instruction operation on the embedded Flash chip based on the acceleration strategy.
8. The embedded Flash on-chip instruction-reading hardware acceleration device of claim 7, wherein the acceleration policy determination unit is specifically configured to:
if the master frequency clock of the system on the embedded Flash chip is low frequency, reading the instruction on the embedded Flash chip by a single clock period through a read operation acceleration strategy of an embedded Flash controller;
if the master frequency clock of the system on the embedded Flash chip is high frequency, determining the type of the instruction executed on the embedded Flash chip through the zone bit of the instruction classifier; if the instruction type is a sequential instruction, adopting a set sequential instruction to read an acceleration strategy; and if the instruction type is a jump instruction, adopting a set jump instruction sheet to read an acceleration strategy.
9. An electronic device, comprising:
a processor; and the number of the first and second groups,
the memory is used for storing a program of the hardware acceleration method of the read instruction on the embedded Flash chip, and after the electronic equipment is electrified and runs the program of the hardware acceleration method of the read instruction on the embedded Flash chip through the processor, the hardware acceleration method of the read instruction on the embedded Flash chip as claimed in any one of the claims 1-5 is executed.
10. A computer-readable storage medium containing one or more program instructions for execution by a server of the embedded Flash read-on-chip instruction hardware acceleration method of any one of claims 1-5.
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