CN111199133B - Automatic wiring and winding method - Google Patents
Automatic wiring and winding method Download PDFInfo
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- CN111199133B CN111199133B CN201911374023.8A CN201911374023A CN111199133B CN 111199133 B CN111199133 B CN 111199133B CN 201911374023 A CN201911374023 A CN 201911374023A CN 111199133 B CN111199133 B CN 111199133B
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Abstract
The invention discloses an automatic wiring and winding method, and relates to the technical field of integrated circuits. The method comprises the following steps: acquiring a coordinate array of an initial winding blocking layer of a target design module; multiplying the coordinate array of the initial winding blocking layer by a preset scaling factor to obtain a scaled winding blocking layer coordinate array, and setting the array as a third variable; acquiring the coordinate arrays of the initial winding barrier layers of all pins in the target design module, performing logic operation based on the arrays to obtain the scaled winding barrier layer coordinate arrays of each pin, and setting the arrays as a fifth variable; performing logic operation on the fifth variable and the third variable to obtain a coordinate array of the winding barrier layer of the target design module and the pins of the target design module after scaling, and setting the array as a sixth variable; a layer with wound barrier information is generated based on the sixth variable. According to the technical scheme, for the design module with more pins, the workload of workers can be reduced, and the design precision can be improved.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to an automatic wiring and winding method.
Background
In the chip design process, physical positions are required to be allocated to units, macro modules and the like on a layout, so that the units, the macro modules and the like are not overlapped with each other, and the process is the layout. After placement, the exact locations of the cells and pins have been determined, as has the interconnections required. Given a set of standard cells and macro blocks, and the characteristic width, height, etc. of these components, a set of wires connecting these cells, macro blocks and pins is given as wiring. The wiring process is used for realizing the connection of each module and generating the geometric interconnection layout of all the connecting lines. The wiring rules, such as via pitch, via-to-metal line distance, etc., are followed in the wiring process. The area reserved for wiring is called a wiring area. Wiring must be performed within the wiring region, and wiring rules must be followed without causing rule violations of the wiring.
In the prior art, the chip design modules are typically laid out using tools in EDA (Electronics Design Automation, electronic design automation). However, when a part of a chip design module is laid out and routed, the constraint range of a wire-wound barrier layer for automatically routing the chip design module by using an EDA tool is insufficient, and in the physical verification stage, the space between an automatic wire-wound pattern and an adjacent design internal layout pattern is insufficient to generate a violation of DRC (Design Rule Checking, design rule check). In addition, for the design module with more pins, the manual supplementing winding blocking layer has the advantages of larger workload, low multiplexing efficiency and low accurate control.
Disclosure of Invention
The invention mainly aims to provide an automatic wiring and winding method, which aims to reduce the winding workload.
In order to achieve the above object, the present invention provides a method for automatically wiring and winding wires, comprising the steps of:
s1, acquiring a coordinate array of an initial winding blocking layer of a target design module, and setting the array as a first variable;
s2, presetting a scaling factor as a second variable, multiplying the first variable and the second variable to obtain a winding barrier layer coordinate array scaled by the target design module, and setting the array as a third variable;
s3, acquiring a coordinate array of an initial winding blocking layer of all pins in the target design module, and setting the array as a fourth variable;
s4, calculating based on the fourth variable to obtain a polygon coordinate array corresponding to each pin, multiplying the polygon coordinate array with the second variable to obtain a winding barrier layer coordinate array scaled by each pin, and setting the array as a fifth variable;
s5, carrying out logic operation on the fifth variable and the third variable to obtain a coordinate array of the winding barrier layer of the target design module and the pins of the target design module after scaling, and setting the array as a sixth variable;
s6, judging whether the sixth variable meets the design requirement or not:
if the design requirement is not met, returning to the step S2, and modifying the value of the second variable;
if the design requirement is met, generating a layer with winding barrier layer information based on the sixth variable;
and S7, displaying and storing a layer of the winding blocking layer information at the corresponding position of the target design module.
Preferably, before the step S1, the method further includes:
using a tool to automatically wire the target design module so as to obtain an initial wire winding blocking layer of the target design module and pins thereof; judging whether the initial winding blocking layer meets the design requirement or not: if the design requirement is met, step S7 is carried out; if the design requirement is not met, step S1 is performed.
Preferably, verification is performed by the tool to determine whether the wire-wound barrier meets design requirements.
Preferably, the step S1 further includes: and searching an address pointer based on the top layer attribute of the target design module according to the name of the target design module, and acquiring a coordinate array of an initial winding blocking layer of the target design module according to the address pointer.
Preferably, in step S4, calculating the polygon coordinate array corresponding to each pin based on the fourth variable further includes: and performing inverse operation on the fourth variable to obtain a polygon coordinate array corresponding to each pin.
Preferably, in the step S5, the logical operation is a nand operation.
According to the technical scheme, the initial winding blocking layer information of the target design module is obtained, and the initial winding blocking layer is scaled according to the preset scaling factor on the basis, so that new winding blocking layer information is obtained, and the shape and the constraint range of the scaling winding blocking layer can be flexibly realized; for the design module with more pins, the workload of workers can be reduced, and the design precision can be improved.
Drawings
Fig. 1 is a flow chart of the method for automatic wiring and winding of the present invention.
The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The invention is further described below with reference to the accompanying drawings.
In the embodiment of the invention, the target design module is a layout design file of the chip design module, and is generally a file in LEF (Library Exchange File ) format. The tools used are typically back end design tools in EDA tools.
As shown in fig. 1, an embodiment of the present invention provides a method for automatically wiring and winding wires, which includes the following steps:
s0, using a tool to automatically wire the target design module so as to obtain an initial wire winding blocking layer of the target design module and pins thereof; judging whether the initial winding blocking layer meets the design requirement or not: if the design requirement is met, step S7 is carried out; if the design requirement is not met, step S1 is performed.
In particular, in EDA tools, the chip design module may be automatically wire-wound for subsequent design. When the constraint range of the winding blocking layer for automatically wiring the chip design module by using the EDA tool is insufficient, the initial winding blocking layer is judged to be not in accordance with the design requirement.
S1, acquiring a coordinate array of an initial winding blocking layer of a target design module, and setting the array as a first variable;
specifically, step S1 further includes: and searching an address pointer based on the top layer attribute of the target design module according to the name of the target design module, and acquiring a coordinate array of an initial winding blocking layer of the target design module according to the address pointer.
Specifically, the format of the array of coordinates of the initial winding barrier of the target design module is generally (x 1 ，y 1 ，x 2 ，y 2 ) In the form, the graphic size of the polygon corresponding to the target design module can be obtained according to the coordinate array.
S2, presetting a scaling factor as a second variable, multiplying the first variable and the second variable to obtain a winding barrier layer coordinate array scaled by the target design module, and setting the array as a third variable;
in a specific embodiment, the scaling factor is used to control the scaling of the size of the winding blocking layer of the target design module, and the scaling factor can be specifically set according to the specific design requirement of the target design module, so that the shape and the constraint range of the winding blocking layer can be flexibly scaled, whether the set scaling factor meets the design requirement can be further verified in the subsequent step, and if not, the scaling factor can be modified again to meet the design requirement.
S3, acquiring a coordinate array of an initial winding blocking layer of all pins in the target design module, and setting the array as a fourth variable;
in a specific embodiment, the initial winding blocking layer of the pin in the target design module is generally composed of a plurality of polygons, and the corresponding coordinate arrays have a plurality of groups.
S4, calculating based on the fourth variable to obtain a polygon coordinate array corresponding to each pin, multiplying the polygon coordinate array with the second variable to obtain a winding barrier layer coordinate array scaled by each pin, and setting the array as a fifth variable;
preferably, in step S4, calculating the polygon coordinate array corresponding to each pin based on the fourth variable further includes: and performing inverse operation on the fourth variable to obtain a polygon coordinate array corresponding to each pin.
S5, carrying out logic operation on the fifth variable and the third variable to obtain a coordinate array of the winding barrier layer of the target design module and the pins of the target design module after scaling, and setting the array as a sixth variable;
preferably, in the step S5, the logical operation is a nand operation.
S6, judging whether the sixth variable meets the design requirement or not:
if the design requirement is not met, returning to the step S2, and modifying the value of the second variable;
if the design requirement is met, generating a layer with winding barrier layer information based on the sixth variable;
and S7, displaying and storing a layer of the winding blocking layer information at the corresponding position of the target design module.
Preferably, verification is performed by the tool to determine whether the wire-wound barrier meets design requirements.
According to the technical scheme, the initial winding blocking layer information of the target design module is obtained, and on the basis, the initial winding blocking layer is scaled according to the preset scaling factor to obtain new winding blocking layer information, so that the shape and the constraint range of the winding blocking layer can be flexibly scaled; for the design module with more pins, the workload of workers can be reduced, and the design precision can be improved.
The target design module in the embodiment of the invention is based on a general design exchange file, and the technical scheme of the invention is not limited by the process in the same back-end design tool environment; meanwhile, the technical scheme of the invention has good portability for different EDA tools designed at the back end, and the same function can be realized by correspondingly replacing corresponding tool command languages.
Aiming at the design flow staged requirement, the technical scheme of the invention can be used as an independent subprocess to be embedded into any stage of the design flow of the target design module, and can be repeatedly acted on the target design module until the design requirement is met.
It should be understood that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all equivalent structures or equivalent processes using the descriptions of the present invention and the accompanying drawings, or direct or indirect application in other relevant technical fields, are included in the scope of the present invention.
Claims (4)
1. A method of automatic wiring winding, comprising the steps of:
s1, acquiring a coordinate array of an initial winding blocking layer of a target design module, and setting the array as a first variable;
s2, presetting a scaling factor as a second variable, multiplying the first variable and the second variable to obtain a winding barrier layer coordinate array scaled by the target design module, and setting the array as a third variable;
s3, acquiring a coordinate array of an initial winding blocking layer of all pins in the target design module, and setting the array as a fourth variable;
s4, performing inverse operation based on the fourth variable to obtain a polygon coordinate array corresponding to each pin, performing multiplication operation with the second variable to obtain a winding barrier layer coordinate array scaled by each pin, and setting the array as a fifth variable;
s5, performing NAND operation on the fifth variable and the third variable to obtain a coordinate array of the winding barrier layer of the target design module and the pins of the target design module after scaling, and setting the array as a sixth variable;
s6, judging whether the sixth variable meets the design requirement or not, and judging that the sixth variable does not meet the design requirement when the constraint range of the winding barrier layer for automatic wiring by the chip design module is insufficient:
if the design requirement is not met, returning to the step S2, and modifying the value of the second variable;
if the design requirement is met, generating a layer with winding barrier layer information based on the sixth variable;
and S7, displaying and storing a layer of the winding blocking layer information at the corresponding position of the target design module.
2. The method of automatic wire-wrapping according to claim 1, characterized by further comprising, before said step S1:
using a tool to automatically wire the target design module so as to obtain an initial wire winding blocking layer of the target design module and pins thereof; judging whether the initial winding blocking layer meets the design requirement or not: if the design requirement is met, step S7 is carried out; if the design requirement is not met, step S1 is performed.
3. The method of automatic wire-wrapping according to claim 2, wherein verification is performed by the tool to determine if the wire-wrapping barrier meets design requirements.
4. The method of automatic wire-wrapping according to claim 1, wherein said step S1 further comprises: and searching an address pointer based on the top layer attribute of the target design module according to the name of the target design module, and acquiring a coordinate array of an initial winding blocking layer of the target design module according to the address pointer.
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| CN201911374023.8A CN111199133B (en) | 2019-12-27 | 2019-12-27 | Automatic wiring and winding method |
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| CN117422042B (en) * | 2023-11-08 | 2024-07-02 | 广芯微电子（广州）股份有限公司 | Design method and device for comb-shaped winding barrier layer |
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