CN111161659A

CN111161659A - Time sequence controller

Info

Publication number: CN111161659A
Application number: CN201811325123.7A
Authority: CN
Inventors: 吴东颖
Original assignee: Himax Technologies Ltd
Current assignee: Himax Technologies Ltd
Priority date: 2018-11-08
Filing date: 2018-11-08
Publication date: 2020-05-15

Abstract

A timing controller. The time schedule controller comprises a bit extraction circuit and a gear signal generation circuit. The bit extraction circuit is used for extracting a first part of bits from any one of a plurality of original sub-pixel data of a video stream. The shift signal generating circuit determines a shift signal associated with the current frame according to the first part of bits. The shift signal is provided to a gamma voltage generating circuit of the source driver, so that the gamma voltage generating circuit changes a plurality of gamma voltages according to the shift signal.

Description

Time sequence controller

Technical Field

The present invention relates to a display device, and more particularly, to a timing controller.

Background

With the progress of electronic technology, consumer electronics have become a necessary tool in people's life. There is also a trend to provide high quality display devices on consumer electronics products to provide good human-machine interfaces. Therefore, it is a subject of persons skilled in the art to effectively reduce the number of bits of sub-pixel data received by a Digital-to-Analog Converter (DAC) of a source driver.

Disclosure of Invention

The invention provides a time schedule controller which can effectively reduce the bit number of sub-pixel data received by a digital-to-analog converter of a source driver.

The time schedule controller comprises a bit extraction circuit and a gear signal generation circuit. The bit extraction circuit is used for extracting a first part of bits from any one of a plurality of original sub-pixel data of a video stream. The shift signal generating circuit is coupled to the bit extracting circuit to receive the first part of bits and determine a shift signal related to the current frame according to the first part of bits, wherein the shift signal is provided to the gamma voltage generating circuit of the source driver, so that the gamma voltage generating circuit changes the plurality of gamma voltages according to the shift signal.

Based on the above, the timing controller according to the embodiments of the invention can utilize the bit extraction circuit to extract the first part of bits of the original sub-pixel data, and utilize the shift signal generation circuit to determine the shift signal to be transmitted to the gamma voltage generation circuit according to the first part of bits. The gamma voltage generating circuit can adjust the gamma voltage according to the gear signal. According to the adjusted gamma voltage, the digital-to-analog converter transmits the source electrode driving signal to the display panel.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a Circuit Block diagram of a timing controller according to an embodiment of the invention.

Fig. 2 is a circuit block diagram illustrating the shift position signal generating circuit shown in fig. 1 according to an embodiment of the invention.

Fig. 3 is a circuit block diagram of a timing controller according to another embodiment of the invention.

Fig. 4 is a circuit block diagram of a timing controller according to still another embodiment of the invention.

FIG. 5 is a schematic diagram illustrating a current sub-pixel and neighboring sub-pixels according to an embodiment of the invention.

Fig. 6 is a circuit block diagram of a timing controller according to another embodiment of the invention.

FIG. 7 is a block diagram illustrating a gamma voltage generating circuit of FIG. 1 according to an embodiment of the present invention.

Fig. 8 is a flowchart illustrating an operation method of a timing controller according to an embodiment of the invention.

Description of reference numerals:

100_1 to 100_ 4: time sequence controller

110: bit extraction circuit

120: gear signal generating circuit

130: bit adjusting circuit

140: error diffusion circuit

200: source driver

210: gamma voltage generating circuit

220: latch circuit

230_1 to 230_ N: digital-to-analog converter

240_1 to 240_ N: output buffer

BUF 1-BUFn: buffer device

121: gear determining circuit

121 a: group selection unit

121 b: gear determining unit

300: display panel

C1-Cm: counting circuit

CSP: current sub-pixel

GS: gear signal

MUX 1-MUXn: multiplexer

OSPD 1-OSPDN: raw sub-pixel data

PB1_1 to PB1_ N, PB2_1 to PB2_ N: partial bit cell

SPD 1-SPDN: processed sub-pixel data

S1-SN: source driving signal

SG: selecting the result

TA 1-TAN: temporary data

RS 1-RSn: resistor string

V1-Vm: count value

VG1 to VGn: gamma voltage

S810 to S830: step (ii) of

Detailed Description

The term "coupled" as used throughout this specification, including the claims, may refer to any direct or indirect connection. For example, if a first device couples (or connects) to a second device, it should be construed that the first device may be directly connected to the second device or the first device may be indirectly connected to the second device through other devices or some means of connection. Further, wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts. Elements/components/steps in different embodiments using the same reference numerals or using the same terms may be referred to one another in relation to the description.

Fig. 1 is a block diagram of a timing controller 100_1 according to an embodiment of the invention. Referring to fig. 1, in the present embodiment, a timing controller 100_1 includes a bit extraction circuit 110 and a shift signal generation circuit 120. The bit extraction circuit 110 can extract the corresponding first partial bits PB1_1 PB1_ N and the corresponding processed sub-pixel data SPD1 SPDN from the original sub-pixel data OSPD1 OSPDN of the video stream. In this embodiment, the processed sub-pixel data SPDs 1-SPDN can be the second portion of bits of the original sub-pixel data OSPD 1-OSPDN. The number of bits of the first partial bits PB1_1 PB1_ N and the number of bits of the processed sub-pixel data SPD1 SPDN can be determined according to design requirements. For example, taking the original sub-pixel data OSPD1 as an example, the first partial bits PB1_1 may be two Least Significant Bits (LSB) in the original sub-pixel data OSPD1, and the processed sub-pixel data SPD1 may be eight Most Significant Bits (MSB) in the original sub-pixel data OSPD 1. The remaining original sub-pixel data may be analogized.

The tap signal generating circuit 120 is coupled to the bit extraction circuit 110 for receiving the first partial bits PB1_ 1-PB 1_ N. The shift signal generating circuit 120 determines the shift signal GS associated with the current frame according to the first partial bits PB1_ 1-PB 1_ N. The shift signal generation circuit 120 may provide the shift signal GS to the gamma voltage generation circuit 210 of the source driver 200.

On the other hand, the source driver 200 includes a gamma voltage generating circuit 210, a latch circuit 220, Digital-to-Analog converters (DACs) 230_1 to 230_ N, and output buffers 240_1 to 240_ N. Wherein, the N is a positive integer. The gamma voltage generating circuit 210 is coupled to the shift signal generating circuit 120 to receive the shift signal GS. The gamma voltage generating circuit 210 can provide and change a plurality of gamma voltages VG 1-VGn according to the shift signal GS. Latch circuit 220 is coupled to bit extraction circuit 110 to receive processed sub-pixel data SPDs 1-SPDN. The latch circuit 220 can latch the processed sub-pixel data SPDs 1-SPDN and provide the processed sub-pixel data SPDs 1-SPDN to the digital-to-analog converters 230_ 1-230 _ N, respectively.

The digital-to-analog converters 230_1 to 230_ N are coupled between the latch circuit 220 and the output buffers 240_1 to 240_ N. The DAC 230_ 1-230 _ N is coupled to the gamma voltage generating circuit 210 for receiving the gamma voltages VG 1-VGn. The digital-to-analog converters 230_1 to 230_ N respectively receive the processed sub-pixel data SPDs 1 to SPDN from the latch circuit 220. According to the gamma voltages VG 1-VGn, each of the digital-to-analog converters 230_ 1-230 _ N can convert the corresponding processed sub-pixel data SPD 1-SPDN into the source driving signals S1-SN, respectively. The DAC 230_ 1-230 _ N can transmit the source driving signals S1-SN to corresponding data lines (or source lines) of the display panel 300 via the output buffers 240_ 1-240 _ N.

Fig. 2 is a schematic circuit block diagram illustrating the shift position signal generating circuit 120 shown in fig. 1 according to an embodiment of the invention. Referring to fig. 1 and fig. 2, in the present embodiment, the shift signal generating circuit 120 includes a plurality of counting circuits C1-Cm and a shift determining circuit 121. The number m of the counter circuits C1-Cm can be determined according to design requirements. The counting circuits C1-Cm are coupled to the bit extraction circuit 110 for receiving the first partial bits PB1_ 1-PB 1_ N. It should be noted that the counting circuits C1-Cm may have different counting conditions, and each counting circuit C1-Cm may be configured to count the number of objects meeting the counting conditions in the first partial bits PB1_ 1-PB 1_ N to obtain the counting values V1-Vm. The counting condition may be determined according to design requirements.

For example, in the present embodiment, the counting condition of the counting circuit C1 may be "the content of the first part of bits is 00". That is, the counting circuit C1 is configured to count/count the number of the first partial bits having the bit value "00" in all the first partial bits (including the first partial bits PB1_1 to PB1_ N) of the same frame (frame), and provide the counting result (the counting value V1) to the range decision circuit 121. The counting condition of the counting circuit C2 may be "the content of the first part of bits is 01". That is, the counting circuit C2 is configured to count/count the number of the first partial bits with the bit value "01" in all the first partial bits (including the first partial bits PB1_1 to PB1_ N) of the same frame, and provide the counting result (the counting value V2) to the gear stage determining circuit 121. The counting condition of the counting circuit C3 may be "the content of the first part of bits is 10". That is, the counting circuit C3 is configured to count/count the number of the first partial bits with the bit value "10" in all the first partial bits (including the first partial bits PB1_1 to PB1_ N) of the same frame, and provide the counting result (the counting value V3) to the gear stage determining circuit 121. The counting condition of the counting circuit C4 may be "the content of the first part of bits is 11". That is, the counting circuit C4 is configured to count/count the number of the first partial bits with the bit value "11" in all the first partial bits (including the first partial bits PB1_1 to PB1_ N) of the same frame, and provide the counting result (the counting value V4) to the gear stage determining circuit 121.

According to design requirements, in some embodiments, the counting circuits C1-Cm may include a plurality of group counting circuits (e.g., group counting circuit C5 and group counting circuit C6). In such an embodiment, all the first portion bits (including the first portion bits PB1_ 1-PB 1_ N) in the same frame may be divided into a plurality of groups (e.g., the first group GA and the second group GB), and the count values V1-Vm may include a plurality of group count values (e.g., the first group count value V5 and the second group count value V6). The first group count value V5 is represented as the number of first part bits in the first group GA, and the second group count value V6 is represented as the number of first part bits in the second group GB.

For example, in the present embodiment, all the first partial bits (including the first partial bits PB1_1 to PB1_ N) in the same frame have the first bit data (e.g. bit value "00") or the second bit data (e.g. bit value "01") thereof classified as the first group GA. In addition, all the first partial bits (including the first partial bits PB1_ 1-PB 1_ N) in the same frame have the third bit data (e.g. bit value "10") or the fourth bit data (e.g. bit value "11") classified as the second group GB. In any event, other embodiments of the invention are not so limited. The counting condition of the group counting circuit C5 may be "the content of the first part of bits is 00 or 01". That is, the group counting circuit C5 is configured to count/count the number of the first partial bits having the bit value "00" or "01" in all the first partial bits (including the first partial bits PB1_1 to PB1_ N) of the same frame, and provide the count result (the first group count value V5) to the shift stage determining circuit 121. The counting condition of the group counting circuit C6 may be "the content of the first part of bits is 10 or 11". That is, the group counting circuit C6 is configured to count/count the number of the first partial bits having the bit value "10" or "11" in all the first partial bits (including the first partial bits PB1_1 to PB1_ N) of the same frame, and provide the count result (the second group count value V6) to the stage determining circuit 121.

On the other hand, the gear position determining circuit 121 is coupled to the counting circuits C1-Cm to receive the counting values V1-Vm. The shift position determining circuit 121 may determine the shift position signal GS according to the count values V1 to Vm. In this embodiment, the gear determining circuit 121 may include a group selecting unit 121a and a gear determining unit 121 b. In any event, other embodiments of the invention are not so limited. The group selection unit 121a is coupled to the counting circuits C1-Cm to receive the first group count value V5 and the second group count value V6. The group selection unit 121a determines a selected group according to the first group count value V5 and the second group count value V6, and provides a selection result SG to indicate the selected group. In addition, the gear determining unit 121b is coupled to the group selecting unit 121a to receive the selection result SG. The shift determining unit 121b can generate and determine the shift signal GS according to the selected group (the selection result SG) and the count values V1-Vm.

For example, when the group selection unit 121a determines that the difference between the first group count value V5 and the second group count value V6 is greater than the first threshold value VTH1, the group selection unit 121a may select the first group GA as the selected group and provide the selection result SG related to the selected group to the gear position determination unit 121 b. In contrast, when the group selection unit 121a determines that the difference between the first group count value V5 and the second group count value V6 is less than the second threshold value VTH2, the group selection unit 121a may select the second group GB as the selected group and provide the selection result SG related to the selected group to the gear position determination unit 121 b. The first threshold value VTH1 and the second threshold value VTH2 may be determined according to design requirements. In some embodiments, the first threshold value VTH1 is different from the second threshold value VTH2, for example, the first threshold value VTH1 is greater than the second threshold value VTH 2. In other embodiments, the first threshold value VTH1 may be the same as the second threshold value VTH 2. It is noted that when the difference between the first group count value V5 and the second group count value V6 of a current frame is neither greater than the first threshold value VTH1 nor less than the second threshold value VTH2, the group selection unit 121a may continue to use the group selection result of the previous frame as the selected group of the current frame.

The shift position determining unit 121b determines the shift position signal GS according to the selected group indicated by the selection result SG and the count values V1-Vm. For example, when the selection result SG indicates that the selected group is the first group GA, and a difference between a count value V1 of the count values V1-Vm, which is related to the first bit data (e.g., bit value "00"), and a count value V2 of the count values V1-Vm, which is related to the second bit data (e.g., bit value "01"), is greater than the third threshold value VTH3, the shift determination unit 121b may select the candidate shift signal (e.g., bit value "00") corresponding to the first bit data (e.g., bit value "00") as the shift signal GS. On the contrary, when the selection result SG indicates that the selected group is the first group GA and the difference between the count value V1 of the count values V1-Vm, which is related to the first bit data (e.g. bit value "00"), and the count value V2 of the count values V1-Vm, which is related to the second bit data (e.g. bit value "01"), is smaller than the fourth threshold value VTH4, the shift position determining unit 121b may select the candidate shift position signal (e.g. bit value "01") corresponding to the second bit data (e.g. bit value "01") as the shift position signal GS. The third threshold value VTH3 and the fourth threshold value VTH4 may be determined according to design requirements.

On the other hand, when the selection result SG indicates that the selected group is the second group GB, and the difference between the count value V3 of the count values V1-Vm, which is related to the third metadata (e.g., the bit value "10"), and the count value V4 of the count values V1-Vm, which is related to the fourth metadata (e.g., the bit value "11"), is greater than the fifth threshold value VTH5, the shift determining unit 121b may select the candidate shift signal (e.g., the bit value "10") corresponding to the third metadata (e.g., the bit value "10") as the shift signal GS. On the contrary, when the selection result SG indicates that the selected group is the second group GB, and the difference between the count value V3 of the count values V1-Vm, which is related to the third bit data (e.g. bit value "10"), and the count value V4 of the count values V1-Vm, which is related to the fourth bit data (e.g. bit value "11"), is smaller than the sixth threshold value VTH6, the shift position determining unit 121b may select the candidate shift position signal (e.g. bit value "11") corresponding to the fourth bit data (e.g. bit value "11") as the shift position signal GS. The fifth threshold value VTH5 and the sixth threshold value VTH6 may be determined according to design requirements. In some embodiments, the third to sixth threshold values VTH 3-VTH 6 are different from each other. In other embodiments, some (or all) of the threshold values VTH 3-VTH 6 may be the same as each other. It should be noted that when the gear position determining unit 121b determines that the result is not the above four cases, the gear position determining unit 121b may use the gear position signal GS of the previous frame as the gear position signal GS of the current frame.

The gamma voltage generating circuit 210 of the source driver 200 can correspondingly change the gamma voltages VG 1-VGn according to the shift signal GS provided by the shift signal generating circuit 120. The DAC 230_ 1-230 _ N can provide the source driving signals S1-SN according to the gamma voltages VG 1-VGn and the processed sub-pixel data SPD 1-SPDN. The source driving signals S1-SN are transmitted to the data lines (or source lines) of the display panel 300 through the output buffers 240_ 1-240 _ N.

Fig. 3 is a circuit block diagram of a timing controller 100_2 according to another embodiment of the invention. The timing controller 100_2 shown in fig. 3 can supply the shift signal GS and the processed sub-pixel data SPDs 1-SPDN to the source driver (e.g., the source driver 200 shown in fig. 1, which is not described herein again). In the embodiment shown in fig. 3, the timing controller 100_2 includes a bit extraction circuit 110, a shift signal generation circuit 120, and a bit adjustment circuit 130. The bit extraction circuit 110 and the shift signal generation circuit 120 shown in fig. 3 can be analogized with reference to the related descriptions of fig. 1 and fig. 2, and therefore, the description thereof is omitted. In the embodiment shown in fig. 3, the bit adjusting circuit 130 is coupled to the shift signal generating circuit 120 to receive the shift signal GS. The bit adjustment circuit 130 can receive the second partial bits PB2_1 PB2_ N of the original sub-pixel data OSPD 1-OSPDN. The number of bits of the second partial bits PB2_ 1-PB 2_ N can be determined according to design requirements. Taking the original sub-pixel data OSPD1 as an example, the second partial bit PB2_1 may be eight Most Significant Bits (MSB) of the original sub-pixel data OSPD1, for example. The remaining original sub-pixel data may be analogized.

In this embodiment, the bit adjusting circuit 130 may determine whether to adjust the second portion of bits of any one of the original sub-pixel data OSPD 1-OSPDN according to the shift signal GS, so as to obtain a plurality of processed sub-pixel data SPDs 1-SPDN. Also, bit adjustment circuit 130 may provide these processed subpixel data SPDs 1-SPDN to latch circuit 220 of source driver 200.

An example of the operation details of the bit adjusting circuit 130 is described below. When the bit value of the shift signal GS selected by the shift signal generating circuit 120 is the same as the bit value of the first part of bits (e.g., two LSBs of the current sub-pixel data) of the current sub-pixel data in the original sub-pixel data OSBD 1-OSBDN, the bit adjusting circuit 130 may not adjust the second part of bits (e.g., eight MSBs of the current sub-pixel data) of the current sub-pixel data. In contrast, when the bit value of the shift signal GS selected by the shift signal generating circuit 120 is different from the bit value of the first part of bits of a current sub-pixel data of the original sub-pixel data OSBD 1-OSBDN, the bit adjusting circuit 130 may adjust (increase or decrease) or not adjust the second part of bits of the current sub-pixel data.

For example, it is assumed that the shift signal generating circuit 120 selects a first candidate shift signal (e.g. bit value "00") corresponding to the first bit data or a second candidate shift signal (e.g. bit value "01") corresponding to the second bit data as the shift signal GS. When the assumption is satisfied, and when the first part of bits of a current sub-pixel data of the original sub-pixel data OSBD 1-OSBDN is the first bit data (e.g., bit value "00"), the second bit data (e.g., bit value "01"), the third bit data (e.g., bit value "10"), or the fourth bit data (e.g., bit value "11"), the bit adjusting circuit 130 may not adjust the second part of bits of the current sub-pixel data, i.e., the second part of bits of the current sub-pixel data is used as the processed sub-pixel data (e.g., one of processed sub-pixel data SPD 1-SPDN) corresponding to the current sub-pixel data.

In contrast, it is assumed that the shift signal generating circuit 120 selects the third candidate shift signal (e.g. bit value "10") corresponding to the third bit data or the fourth candidate shift signal (e.g. bit value "11") corresponding to the fourth bit data as the shift signal GS. When the assumption is satisfied, and when the first part of bits of the current sub-pixel data in the original sub-pixel data OSBD 1-OSBDN is the first bit data (e.g. bit value "00") or the second bit data (e.g. bit value "01"), the bit adjusting circuit 130 may reduce the second part of bits of the current sub-pixel data (e.g. reduce the bit value of the second part of bits by 1) to obtain the processed sub-pixel data corresponding to the current sub-pixel data. When the assumption is satisfied, and when the first part of bits of the current sub-pixel data in the original sub-pixel data OSBD 1-OSBDN is the third bit data (e.g. bit value "10") or the fourth bit data (e.g. bit value "11"), the bit adjusting circuit 130 may not adjust the second part of bits of the current sub-pixel data, i.e. the second part of bits of the current sub-pixel data is used as the processed sub-pixel data corresponding to the current sub-pixel data.

The details of the operation of the bit adjusting circuit 130 are not limited to the above. In another embodiment, when the shift signal GS is "00" or "01" and when the first part of bits of a current sub-pixel data of the original sub-pixel data OSBD 1-OSBDN is the third bit data (e.g. bit value "10") or the fourth bit data (e.g. bit value "11"), the bit adjustment circuit 130 may increase the second part of bits of the current sub-pixel data (e.g. bit value of the second part of bits of the current sub-pixel data plus 1) as the processed sub-pixel data corresponding to the current sub-pixel data. In other cases, the bit adjusting circuit 130 may not adjust the second part of bits of the current sub-pixel data, i.e. the second part of bits of the current sub-pixel data is used as the processed sub-pixel data corresponding to the current sub-pixel data.

In yet another embodiment, when the shift signal GS is "00" or "01", and when the first part of bits of the current sub-pixel data is the third bit data (e.g. bit value "10") or the fourth bit data (e.g. bit value "11"), the bit adjusting circuit 130 may increase the second part of bits of the current sub-pixel data (e.g. adding 1 to the bit value of the second part of bits) as the processed sub-pixel data corresponding to the current sub-pixel data. When the shift signal GS is "10" or "11" and when the first part of bits of the current sub-pixel data is the first bit data (e.g. bit value "00") or the second bit data (e.g. bit value "01"), the bit adjusting circuit 130 may adjust the second part of bits of the current sub-pixel data (e.g. decrease the bit value of the second part of bits by 1) to obtain the processed sub-pixel data corresponding to the current sub-pixel data. In other cases, the bit adjusting circuit 130 may not adjust the second part of bits of the current sub-pixel data, i.e. the second part of bits of the current sub-pixel data is used as the processed sub-pixel data corresponding to the current sub-pixel data.

Fig. 4 is a circuit block diagram of a timing controller 100_3 according to still another embodiment of the invention. The timing controller 100_3 shown in fig. 4 can supply the shift signal GS and the processed sub-pixel data SPDs 1-SPDN to the source driver (e.g., the source driver 200 shown in fig. 1, which is not described herein again). In the embodiment shown in fig. 4, the timing controller 100_3 includes a bit extraction circuit 110, a shift signal generation circuit 120, and an error diffusion circuit 140. The bit extraction circuit 110 and the shift signal generation circuit 120 shown in fig. 4 can be analogized with reference to the related descriptions of fig. 1 and fig. 2, and therefore, the description thereof is omitted. In the embodiment shown in fig. 4, the error diffusion circuit 140 is coupled to the shift position signal generating circuit 120 to receive the shift position signal GS. The error diffusion circuit 140 also receives the original sub-pixel data OSPD 1-OSPDN. The error diffusion circuit 140 may adjust the original sub-pixel data of the current sub-pixel according to an error value associated with at least one neighboring sub-pixel to obtain the processed sub-pixel data of the current sub-pixel.

Specifically, FIG. 5 is a schematic diagram illustrating a current sub-pixel and neighboring sub-pixels according to an embodiment of the invention. The embodiment shown in FIG. 5 illustrates the current sub-pixel Cur, the neighboring sub-pixel Cur1, the neighboring sub-pixel Cur2, the neighboring sub-pixel Cur3 and the neighboring sub-pixel Cur 4. The current sub-pixel Cur and the neighboring sub-pixels Cur 1-Cur 4 may have the same color (e.g., red, green or blue).

Referring to FIG. 4 and FIG. 5, the error diffusion circuit 140 can calculate gray level errors of each of the neighboring sub-pixels Cur 1-Cur 4. The gray scale error may be a difference between original sub-pixel data of the neighboring sub-pixel and new sub-pixel data of the neighboring sub-pixel. The new sub-pixel data may be composed of the second part of bits of the original sub-pixel data of the adjacent sub-pixels (e.g. eight MSBs of the original sub-pixel data) and the shift level signal GS. For example, assuming that the shift signal GS of the current frame is "00", the original sub-pixel data of the neighboring sub-pixel Cur4 is "1111010111", the new sub-pixel data of the neighboring sub-pixel Cur4 is "1111010100" (i.e. the composition of "11110101" and "00"), and the gray scale error of the neighboring sub-pixel Cur4 is the difference of "1111010111" minus "1111010100". The calculation of the gray scale errors of the remaining neighboring sub-pixels Cur 1-Cur 3 can be analogized by referring to the description of the neighboring sub-pixel Cur 4.

In the embodiment shown in FIG. 4, the error diffusion circuit 140 may adjust the current sub-pixel Cur according to an error value associated with a neighboring sub-pixel of the current sub-pixel Cur, so as to obtain the processed sub-pixel data of the current sub-pixel Cur. Error diffusion circuit 140 may then transmit these processed subpixel data SPDs 1-SPDN to source driver 200. In some embodiments, the error value may be a weighted sum of gray scale errors of the neighboring sub-pixels Cur 1-Cur 4. It should be noted that, in the neighboring sub-pixels Cur 1-Cur 4, the closer to the current sub-pixel Cur, the larger the weight of the neighboring sub-pixel is, the farther away from the current sub-pixel Cur, the smaller the weight of the neighboring sub-pixel is, but other embodiments of the invention are not limited thereto.

For example, assuming that the second part of bits (e.g. eight MSBs of the original sub-pixel data) of the original sub-pixel Cur is D0, the gray scale errors and weights of the neighboring sub-pixel Cur1 are D1 and W1; the gray scale error and weight of the adjacent sub-pixel Cur2 are D2 and W2; the gray scale error and weight of the adjacent sub-pixel Cur3 are D3 and W3; the gray-scale error and the weight of the neighboring subpixel Cur4 are D4 and W4, and the processed subpixel data SPD of the current subpixel Cur is D0+ D1 × W1+ D2 × W2+ D3 × W3+ D4 × W4. Wherein "D1W 1+ D2W 2+ D3W 3+ D4W 4" may be considered as the error value associated with the at least one neighboring sub-pixel. The weights W1-W4 may be determined according to design requirements. For example, but not limited to, weight W1 may be 7/16, weight W2 may be 5/16, weight W3 may be 3/16, and weight W4 may be 1/16.

Fig. 6 is a circuit block diagram of a timing controller 100_4 according to another embodiment of the invention. The timing controller 100_4 shown in fig. 6 can supply the shift signal GS and the processed sub-pixel data SPDs 1-SPDN to the source driver (e.g., the source driver 200 shown in fig. 1, which is not described herein again). In the embodiment shown in fig. 6, the timing controller 100_4 includes a bit extraction circuit 110, a shift signal generation circuit 120, a bit adjustment circuit 130, and an error diffusion circuit 140. The bit extraction circuit 110 and the shift signal generation circuit 120 shown in fig. 6 can be analogized with reference to the related descriptions of fig. 1 and fig. 2, and therefore, the description thereof is omitted.

The bit adjustment circuit 130 shown in fig. 6 can be analogized with reference to the related description of fig. 3, and therefore, the description thereof is omitted. In the embodiment shown in FIG. 6, "processed sub-pixel data SPDs 1-SPDN" originally output by the bit adjusting circuit 130 shown in FIG. 3 are used as "temporary data TA 1-TAN" shown in FIG. 6. The bit adjustment circuit 130 shown in FIG. 6 can determine whether to adjust the second partial bits PB2_ 1_ PB2_ N of the original sub-pixel data OSPD 1-OSPDN according to the shift signal GS to obtain a plurality of temporary data TA 1-TAN.

The error diffusion circuit 140 shown in fig. 6 can be analogized with reference to the description of fig. 4 and 5. The error diffusion circuit 140 shown in FIG. 6 is coupled to the bit adjusting circuit 130 to receive the temporary data TA1 TAN. In addition, the error diffusion circuit 140 shown in FIG. 6 also receives the original sub-pixel data OSPD 1-OSPDN.

The error diffusion circuit 140 shown in FIG. 6 may adjust the temporal data of the current sub-pixel (e.g., the current sub-pixel Cur shown in FIG. 5) according to the error values associated with a plurality of neighboring sub-pixels (e.g., the neighboring sub-pixels Cur 1-Cur 4) of the current sub-pixel to obtain the processed sub-pixel data. For example, assume that the temporary data of the current subpixel Cur is TA; the gray scale error and weight of the adjacent sub-pixel Cur1 are D1 and W1; the gray scale error and weight of the adjacent sub-pixel Cur2 are D2 and W2; the gray scale error and weight of the adjacent sub-pixel Cur3 are D3 and W3; the gray-scale error and the weight of the neighboring subpixel Cur4 are D4 and W4, and the processed subpixel data SPD of the current subpixel Cur is TA + D1 × W1+ D2 × W2+ D3 × W3+ D4 × W4. The error diffusion circuit 140 shown in fig. 6 can be analogized with reference to the related descriptions of fig. 4 and fig. 5, and therefore, the description thereof is omitted.

FIG. 7 is a block diagram illustrating the gamma voltage generating circuit 210 of FIG. 1 according to an embodiment of the present invention. Referring to fig. 1 and 7, the gamma voltage generating circuit 210 includes resistor strings RS 1-RSn, multiplexers MUX 1-MUXn, and buffers BUF 1-BUFn. Each of the resistor strings RS1 through RSn may be formed by connecting a plurality of resistors in series. These resistor strings RS1 RSn are connected in series to provide a divided voltage. In the embodiment, the multiplexers MUX 1-MUXn are coupled to the shift signal generating circuit 120 for receiving the shift signal GS. The input terminals of each of the multiplexers MUX 1-MUXn are respectively coupled to different voltage-dividing nodes of a corresponding one of the string RS 1-RSn, as shown in FIG. 7. Each of the multiplexers MUX 1-MUXn can select a corresponding divided voltage from the plurality of divided voltages of the corresponding bank string as a corresponding gamma voltage of the gamma voltages VG 1-VGn according to the shift signal GS. The output terminals of the multiplexers MUX 1-MUXn can provide the gamma voltages VG 1-VGn to the input terminals of the buffers BUF 1-BUFn.

On the other hand, the buffers BUF1 BUFn are respectively coupled to the output terminals of the multiplexers MUX1 MUXn to receive the corresponding gamma voltages VG1 VGn. The output terminals of the buffers BUF1 BUFn are coupled to the reference voltage input terminals of the digital-to-analog converters 230_1 to 230_ N to provide the gamma voltages VG1 VGn. In addition, each of the DAC 230_ 1-230 _ N can generate the source driving signals S1-SN according to the processed sub-pixel data SPD 1-SPDN provided by the latch circuit 220 and the gamma voltages VG 1-VGn, respectively.

Fig. 8 is a flowchart illustrating an operation method of a timing controller according to an embodiment of the invention. Referring to fig. 1 and 8, in step S810, the timing controller 100_1 can extract a first partial bit PB1_1 to PB1_ N from any one of a plurality of original sub-pixel data OSPD1 to OSPDN of a video stream through the bit extraction circuit 110. In step S820, the timing controller 100_1 can determine the shift signal GS associated with a current frame via the shift signal generating circuit 120 according to the first partial bits PB1_1 to PB1_ N. In step S830, the timing controller 100_1 can provide the shift signal GS to the gamma voltage generating circuit 210 of the source driver 200 via the shift signal generating circuit 120, so that the gamma voltage generating circuit 210 changes the plurality of gamma voltages VG 1-VGn according to the shift signal GS. The details of the steps are elaborated in the foregoing examples and embodiments, and are not repeated herein.

In summary, the timing controller according to the embodiments of the invention can utilize the bit extraction circuit 110 to extract the first part of bits of the original sub-pixel data, and utilize the shift signal generation circuit 120 to determine the shift signal GS transmitted to the gamma voltage generation circuit 210 according to the first part of bits. The gamma voltage generating circuit can adjust the gamma voltages VG 1-VGn according to the shift signal GS. The DAC converts the processed sub-pixel data into source driving signals according to the adjusted gamma voltages VG 1-VGn, and transmits the source driving signals to the display panel. Therefore, the bit number of the sub-pixel data received by the digital-to-analog converter can be effectively reduced, and the quality of the display picture is further improved.

Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, and that various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A timing controller, comprising:

a bit extraction circuit for extracting a first portion of bits from any one of a plurality of original sub-pixel data of a video stream; and

a shift signal generating circuit coupled to the bit extraction circuit for receiving the first part of bits and determining a shift signal associated with a current frame according to the first part of bits, wherein the shift signal is provided to a gamma voltage generating circuit of a source driver, so that the gamma voltage generating circuit changes a plurality of gamma voltages according to the shift signal.

2. The timing controller of claim 1, wherein the shift signal generating circuit comprises:

a plurality of counting circuits coupled to the bit extraction circuit, wherein each of the plurality of counting circuits has a different counting condition, and any one of the plurality of counting circuits is used for counting the number of the first part of bits meeting the counting condition to obtain a counting value; and

a gear determining circuit coupled to the plurality of counting circuits for receiving the counting value and determining the gear signal according to the counting value.

3. The timing controller as claimed in claim 2, wherein the first portion of bits is divided into a plurality of groups, the count value comprises a plurality of group count values, any one of the plurality of group count values is the number of the first portion of bits in a corresponding one of the plurality of groups, and the range decision circuit comprises:

a group selection unit coupled to the plurality of counting circuits for receiving the plurality of group count values to determine a selected group according to the plurality of group count values; and

a shift determining unit coupled to the group selecting unit for determining the shift signal according to the selected group and the count value.

4. The timing controller of claim 3, wherein the plurality of groups comprises a first group and a second group, the plurality of group count values comprises a first group count value and a second group count value,

wherein the group selection unit selects the first group as the selected group when a difference between the first group count value and the second group count value is greater than a first threshold value,

wherein the group selection unit selects the second group as the selected group when a difference between the first group count value and the second group count value is less than a second threshold value.

5. The timing controller of claim 4, wherein the first portion of bits belonging to the first group comprises a first bit data and a second bit data, the first portion of bits belonging to the second group comprises a third bit data and a fourth bit data,

wherein, when the selected group is the first group and a difference value between a count value related to the first bit data in the count value and a count value related to the second bit data in the count value is larger than a third threshold value, the gear position determining unit selects a candidate gear position signal corresponding to the first bit data as the gear position signal,

wherein, when the selected group is the first group and the difference between the count value related to the first bit data in the count value and the count value related to the second bit data in the count value is smaller than a fourth threshold, the gear position determining unit selects a candidate gear position signal corresponding to the second bit data as the gear position signal,

wherein when the selected group is the second group and a difference between a count value related to the third bit data in the count value and a count value related to the fourth bit data in the count value is greater than a fifth threshold, the shift determination unit selects a candidate shift signal corresponding to the third bit data as the shift signal, an

When the selected group is the second group and the difference between the count value related to the third bit data in the count value and the count value related to the fourth bit data in the count value is smaller than a sixth threshold, the gear determination unit selects a candidate gear signal corresponding to the fourth bit data as the gear signal.

6. The timing controller of claim 1, further comprising:

a bit adjusting circuit coupled to the shift signal generating circuit for receiving the shift signal and determining whether to adjust a second portion of bits of any of the original sub-pixel data according to the shift signal to obtain processed sub-pixel data, wherein the processed sub-pixel data is provided to the source driver.

7. The timing controller of claim 6, wherein the first portion of bits comprises a first bit, a second bit, a third bit and a fourth bit,

when the shift signal generating circuit selects a first candidate shift signal corresponding to the first bit data as the shift signal, and when the first part of bits of a current sub-pixel data in the plurality of original sub-pixel data is the first bit data, the bit adjusting circuit takes a second part of bits of the current sub-pixel data as the processed sub-pixel data corresponding to the current sub-pixel data; and

when the shift signal generating circuit selects the first candidate shift signal corresponding to the first bit data as the shift signal, and when the first part of bits of the current sub-pixel data in the plurality of original sub-pixel data is the third bit data, the bit adjusting circuit adjusts up or down the second part of bits of the current sub-pixel data to obtain the processed sub-pixel data corresponding to the current sub-pixel data.

8. The timing controller of claim 1, further comprising:

an error diffusion circuit, coupled to the shift signal generation circuit to receive the shift signal, for adjusting the original sub-pixel data of a current sub-pixel according to an error value associated with at least one neighboring sub-pixel of the current sub-pixel to obtain a processed sub-pixel data of the current sub-pixel, wherein the processed sub-pixel data is provided to the source driver.

9. The timing controller of claim 8, wherein the at least one neighboring sub-pixel comprises a plurality of neighboring sub-pixels, each of the plurality of neighboring sub-pixels has a gray scale error, the gray scale error is a difference between the original sub-pixel data of the neighboring sub-pixel and a new sub-pixel data of the neighboring sub-pixel, the new sub-pixel data is composed of a second portion of bits of the original sub-pixel data of the neighboring sub-pixel and the shift signal, and the error value is a weighted sum of the gray scale errors.

10. The timing controller of claim 1, further comprising:

a bit adjusting circuit, coupled to the shift signal generating circuit to receive the shift signal, for determining whether to adjust a second portion of bits of any of the original sub-pixel data according to the shift signal to obtain a plurality of temporary data; and

an error diffusion circuit coupled to the shift signal generating circuit for receiving the shift signal and coupled to the bit adjusting circuit for receiving the plurality of temporary data, wherein the error diffusion circuit is configured to adjust the temporary data of a current sub-pixel according to an error value associated with at least one neighboring sub-pixel of the current sub-pixel to obtain a processed sub-pixel data of the current sub-pixel, wherein the processed sub-pixel data is provided to the source driver.