CN111147828A - Low-delay video optical fiber transmission device - Google Patents
Low-delay video optical fiber transmission device Download PDFInfo
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- CN111147828A CN111147828A CN201911340755.5A CN201911340755A CN111147828A CN 111147828 A CN111147828 A CN 111147828A CN 201911340755 A CN201911340755 A CN 201911340755A CN 111147828 A CN111147828 A CN 111147828A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/22—Adaptations for optical transmission
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/18—Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast
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Abstract
The invention relates to a low-delay video optical fiber transmission device which comprises a sending end and a receiving end, wherein the sending end comprises an input interface circuit, an input decoding circuit, an input FPGA signal processing circuit and an optical module sending circuit; the receiving end comprises an optical module receiving circuit, a main FPGA signal processing circuit, at least two sub FPGA signal processing circuits, an output coding circuit and an output interface circuit, wherein the optical module receiving circuit is connected with the main FPGA signal processing circuit, the main FPGA signal processing circuit is connected with the at least two sub FPGA signal processing circuits, the sub FPGA signal processing circuits are connected with the output coding circuit, and the output coding circuit is connected with the output interface circuit. The method is used for optimizing the signal processing process of the original video, reducing the buffer image, optimizing the system delay and enhancing the running reliability of the device.
Description
Technical Field
The invention relates to the technical field of video signal optical fiber transmission, in particular to a low-delay video optical fiber transmission device.
Background
In the prior art, a general method for video transmission processing is to transmit through an ethernet network after passing through a video compression coding/decoding chip, so as to realize remote video transmission. At present, the real-time requirement on video source pictures in the field of video monitoring is high, and the uncertain time delay in the prior art brings great inconvenience to real-time monitoring.
In the prior art, in a sending apparatus for video fiber transmission, a process of processing a video signal stream in the prior art is as follows: the video signal is converted into an input video signal format set by the encoder through the receiver and is input into the video encoder, the video encoder performs compression coding on the input video signal, the input video signal is input into an IP network through a port of the switch, and finally the input video signal is sent to a receiving end through a network cable or an optical fiber. In the video signal stream of the device, an original video signal is subjected to format conversion, compression coding and IP network transmission, wherein signal delay mainly occurs in the compression coding process of the video, and the compression coding process buffers multi-frame images to improve the quality of coded images so as to generate delay.
In a receiving apparatus for video fiber transmission, a process of processing a video signal stream in the prior art is as follows: the method comprises the steps of firstly accessing an Ethernet through a switch chip, then decoding and restoring received video signals by using a proprietary decoding chip or FPGA, then transmitting the video signals to a video transmitting interface chip in a specific format, and driving and transmitting the video signals to a display unit by the interface chip to complete the receiving process of optical fiber video signal streams. In the video signal stream of the device, the video signal stream is transmitted based on a network protocol, and the video signal stream is decoded and restored in a video decoder and main video signal processing is completed. Because the multi-frame images need to be cached in the decoding process, different degrees of time delay exist between the video signal source and the output real-time video, and because the processing process of the video signal is highly concentrated at a special decoding chip, the requirement on the chip is high, the requirement on the heat dissipation condition is high, and the reliability of the system is reduced.
Disclosure of Invention
The present invention is directed to overcoming at least one of the above-mentioned drawbacks of the prior art and providing a low-latency video fiber transmission apparatus for optimizing the signal processing of the original video, reducing the buffered images, optimizing the system latency, and enhancing the reliability of the apparatus operation.
The technical scheme adopted by the invention is that,
a low-delay video optical fiber transmission device comprises a transmitting end and a receiving end, wherein the transmitting end comprises an input interface circuit, an input decoding circuit, an input FPGA signal processing circuit and an optical module transmitting circuit,
the input interface circuit is connected with the decoding circuit and is used for receiving the video electrical signal transmitted by the optical fiber and transmitting the video electrical signal to the input decoding circuit;
the input decoding circuit is connected with the input FPGA signal processing circuit and is used for decoding the video electric signal and transmitting the decoded video electric signal to the input FPGA signal processing circuit;
the input FPGA signal processing circuit is connected with the optical module sending circuit and is used for carrying out serialized coding on the decoded video electrical signal and transmitting the serialized coded serial video electrical signal to the optical module sending circuit;
the optical module sending circuit is used for converting the serial video electric signal into a serial video optical signal and sending the serial video optical signal to a receiving end of the device;
the receiving end comprises an optical module receiving circuit, a main FPGA signal processing circuit, at least two sub FPGA signal processing circuits, an output coding circuit and an output interface circuit,
the optical module receiving circuit is connected with the main FPGA signal processing circuit and used for receiving the serial video optical signal sent by the optical module sending circuit, converting the serial video optical signal into a serial video electrical signal and inputting the serial video electrical signal to the main FPGA signal processing circuit; the main FPGA signal processing circuit is connected with the at least two sub FPGA signal processing circuits and is used for deserializing the serial video electrical signal, reducing the clock frequency of the video electrical signal and respectively transmitting the processed video electrical signal to the at least two sub FPGA signal processing circuits;
the sub FPGA signal processing circuit is connected with the output coding circuit and is used for completing time sequence conversion on the video electric signal processed by the main FPGA signal processing circuit and transmitting the video electric signal to the output coding circuit;
the output coding circuit is connected with the output interface circuit and is used for synthesizing the plurality of video electric signals after the time sequence conversion is finished;
and the output interface circuit is used for outputting the complete video electric signal synthesized by the output coding circuit.
The invention discloses a low-delay video optical fiber transmission device, which comprises a sending end circuit module and a receiving end circuit module, wherein the sending end circuit module comprises an input interface circuit, an input decoding circuit, an input FPGA signal processing circuit and an optical module sending circuit, the receiving end circuit module comprises an optical module receiving circuit, a main FPGA signal processing circuit, at least two sub FPGA signal processing circuits, an output coding circuit and an output interface circuit, and the specific processing process of a video signal stream in the whole device is as follows: the input interface circuit receives video electrical signals in the transmission optical fiber in real time, inputs the video electrical signals to the input decoding circuit, the input decoding circuit decodes the real-time video electrical signals and then restores original video signals, the original video signals are input into the input FPGA signal processing circuit, the input FPGA signal processing circuit carries out serialization coding on the video electrical signals to form serial video electrical signals, the serial video electrical signals are input to the optical module sending circuit, the serial video electrical signals are converted into serial video optical signals in the optical module sending circuit, and the serial video optical signals are transmitted to the receiving end circuit module through optical fiber transmission; an optical module receiving circuit in the receiving end circuit module receives a real-time serial video optical signal, converts the real-time serial video optical signal into a serial video electric signal, inputs the serial video electric signal into a main FPGA signal processing circuit for deserialization, reduces the clock frequency of the video electric signal and completes the main signal processing process. The invention relates to a low-delay video optical fiber transmission device, which is based on the real-time processing technology of FPGA, compared with the prior art, the signal processing process finished by an original video data stream in the whole process from sending to receiving is greatly simplified, and simultaneously, the delay between the sending and receiving of video signals is greatly optimized due to the great reduction of cache data; in the whole signal processing process, the image quality of the original video signal is highly reserved, and the image quality reduction caused by different video coding is reduced; an optical module sending circuit and an optical module receiving circuit of the device are connected with the FPGA signal processing circuit, so that video signals do not need to be converted through an Ethernet protocol, and system design is simplified; and the maximum resolution supported by the device can reach 4k ultrahigh definition resolution. In addition, the receiving end circuit module of the device adopts a plurality of FPGA signal processing circuits to respectively complete different signal processing, compared with the situation that the whole function is completed by a single FPGA, the signal processing pressure of a main FPGA is reduced, the integration requirement of the main FPGA is reduced, the FPGA combination and the type selection are more flexible, the power consumption of the main FPGA is reduced, and the running reliability of the device is enhanced.
A control method of a low-latency video optical fiber transmission device comprises the following steps:
s1, a sending end receives a video electric signal;
s2, decoding the video electric signal;
s3, serializing and coding the decoded video electric signal to obtain a serial video electric signal;
s4, converting the serial video electric signal into a serial video optical signal;
s5, sending the serial video optical signal to a receiving end;
s6, a receiving end receives the serial video optical signals and converts the serial video optical signals into serial video electrical signals;
s7, deserializing the serial video electrical signal, reducing the clock frequency of the deserialized video electrical signal, and shunting the processed video electrical signal into at least two sub video electrical signals;
s8, respectively carrying out time sequence conversion processing on the at least two sub video electric signals;
s9, synthesizing at least two sub-video electric signals after time sequence conversion into a complete video electric signal and carrying out coding processing;
and S10, outputting the coded complete video electric signal.
The control method is used for controlling the transceiving and scheduling of the video electric signals of the sending end and the receiving end, and the processing process of the video electric signals by adopting the control device of the method of the invention comprises the following steps: firstly, a sending end is controlled to receive a real-time video electrical signal transmitted by an optical fiber, the real-time video electrical signal is decoded and restored to form an original video electrical signal, then the original video electrical signal after being decoded is serialized and encoded to form a serial video electrical signal, the serial video electrical signal is converted into a serial video optical signal by a control optical module, and finally the serial video optical signal is transmitted to a receiving end through the optical fiber; in the process of controlling the receiving end to process the video signals, firstly, the receiving end is controlled to receive real-time serial video optical signals sent by the sending end and convert the real-time serial video optical signals into serial video electric signals, secondly, the serial video electric signals are deserialized, the clock frequency of the video electric signals is reduced, the main signal processing process is completed, a plurality of sub video electric signals are divided according to the screen division rule of a display screen, then the plurality of sub video electric signals are respectively subjected to time sequence conversion and then are synthesized into a complete video electric signal, and the complete video electric signal is output and displayed by the receiving end. The invention relates to a control method of a low-delay video optical fiber transmission device, which is based on the real-time processing technology of FPGA, controls the signal processing process of a video signal in the whole process from a sending end to a receiving end to be greatly simplified compared with the prior art, and simultaneously greatly optimizes the delay problem in the sending and receiving period of the video signal due to the great reduction of cache data; in the whole signal processing process, the image quality of the original video signal is highly reserved, and the image quality reduction caused by different video coding is reduced; and the control method of the device enables the maximum resolution supported by the device to reach 4k ultra-high definition resolution. In addition, the method reduces the power consumption of main signal processing by shunting a plurality of sub-video electric signals, so that the running reliability of the system is enhanced.
Compared with the prior art, the invention has the beneficial effects that:
the invention provides a low-delay video optical fiber transmission device and a control method, based on the real-time processing technology of FPGA, compared with the prior art, the signal processing process finished by the original video data stream in the whole process from sending to receiving is greatly simplified, and simultaneously, because the cache data is greatly reduced, the delay between the sending and receiving of the video signal is greatly optimized; in the whole signal processing process, the image quality of the original video signal is highly reserved, and the image quality reduction caused by different video coding is reduced; an optical module sending circuit and an optical module receiving circuit of the device are connected with the FPGA signal processing circuit, so that video signals do not need to be converted through an Ethernet protocol, and system design is simplified; and the maximum resolution supported by the device can reach 4k ultra-high definition resolution. In addition, the receiving end circuit module of the device adopts a plurality of FPGA signal processing circuits to respectively complete different signal processing, compared with the situation that the single FPGA is used for completing the whole function, the signal processing pressure of the main FPGA is reduced, the integration requirement of the main FPGA is reduced, the FPGA combination and the type selection are more flexible, the power consumption of the main FPGA is reduced, and the operation reliability of the device is enhanced.
Drawings
FIG. 1 is a diagram showing the structure of an apparatus according to an embodiment of the present invention.
Fig. 2 is a system block diagram of a transmitting end according to an embodiment of the present invention.
Fig. 3 is a system block diagram of a receiving end according to an embodiment of the present invention.
Fig. 4 is a diagram of a signal processing process of the FPGA group when the display screen is divided into two left and right split screen areas.
FIG. 5 is a flowchart illustrating steps of a control method according to an embodiment of the present invention.
Detailed Description
The drawings are only for purposes of illustration and are not to be construed as limiting the invention. For a better understanding of the following embodiments, certain features of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
Example 1
As shown in fig. 1, fig. 1 is a structural diagram of a low-latency video optical fiber transmission apparatus according to an embodiment of the present invention, which includes a sending end circuit module and a receiving end circuit module, where the sending end circuit module includes an input interface circuit, an input encoding circuit, an input FPGA signal processing circuit, and an optical module sending circuit, and the receiving end includes an optical module receiving circuit, a main FPGA signal processing circuit, at least two sub FPGA signal processing circuits, an output encoding circuit, and an output interface circuit,
as shown in fig. 2, fig. 2 is a process of processing a video signal by each circuit module at a transmitting end according to the embodiment of the present invention:
and the input interface circuit is connected with the decoding circuit and is used for receiving the video electric signal transmitted by the optical fiber and transmitting the video electric signal to the input decoding circuit. Specifically, in the embodiment of the present invention, the input interface circuit employs an HDMI input interface circuit and/or a DP input interface circuit.
In the embodiment of the invention, the adopted HDMI (high definition multimedia interface) is a digital video/audio interface technology, is a special digital interface suitable for image transmission, has the highest data transmission speed of 2.25GB/s, and does not need digital/analog or analog/digital conversion before signal transmission. DP is also a high-definition digital display interface technology, in terms of performance, the transmission bandwidth of 10.8Gb/S, and DP has ultrahigh bandwidth and resolution, and is completely suitable for the development of display screens. The embodiment of the invention adopts the HDMI interface and DP interface technology, has high signal transmission speed and low video signal quality loss, and can provide the best video quality.
And the input decoding circuit is connected with the input FPGA signal processing circuit and is used for decoding the video electric signal and transmitting the decoded video electric signal to the input FPGA signal processing circuit.
In the embodiment of the invention, the HDMI interface circuit and the DP interface circuit receive the coded video electric signals and then decode the coded video electric signals in the input decoding circuit, the decoded video electric signals are restored to original video electric signals, and the restored video electric signals transmit the video signals to the input FPGA signal processing circuit through the LVDS differential bus.
And the input FPGA signal processing circuit is connected with the optical module sending circuit and is used for serializing and coding the decoded video electrical signal and transmitting the serialized and coded serial video electrical signal to the optical module sending circuit.
In the embodiment of the invention, the input FPGA signal processing circuit carries out serialization coding on the restored video electric signal in real time to obtain a serial video electric signal, and the serial video electric signal with high bandwidth is transmitted to the optical module transmitting circuit through an SERDES interface of an FPGA chip.
And the optical module sending circuit is used for converting the serial video electric signal into a serial video optical signal and sending the serial video optical signal to a receiving end of the device. Specifically, the optical module transmitting circuit and the optical module receiving circuit are connected by an optical fiber.
As shown in fig. 3, fig. 3 is a process of processing a video signal by each circuit module at a receiving end according to an embodiment of the present invention:
and the optical module receiving circuit is connected with the main FPGA signal processing circuit and used for receiving the serial video optical signal sent by the optical module sending circuit, converting the serial video optical signal into a serial video electrical signal and inputting the serial video electrical signal into the main FPGA signal processing circuit. Specifically, the optical module receiving circuit is connected to an optical fiber and receives a serial video optical signal transmitted from the optical fiber.
The main FPGA signal processing circuit is connected with the at least two sub FPGA signal processing circuits and is used for deserializing the serial video electrical signal, reducing the clock frequency of the video electrical signal and respectively transmitting the processed video electrical signal to the at least two sub FPGA signal processing circuits;
in the embodiment of the invention, the high-speed serial video electrical signal input by the optical module receiving circuit completes main signal processing processes such as deserializing and OSD superposition of the signal at the main FPGA signal processing circuit, the clock frequency of the video electrical signal is reduced, and then the video signal after the main signal processing is completed is transmitted to at least two sub FPGA signal processing circuits according to the actual screen splitting condition.
The sub FPGA signal processing circuit is connected with the output coding circuit and is used for completing time sequence conversion on the video electric signal processed by the main FPGA signal processing circuit and transmitting the video electric signal to the output coding circuit;
preferably, the embodiment of the present invention at least includes two sub-FPGA signal processing circuits, and the number of the sub-FPGA signal processing circuits is determined by the following method:
dividing a display screen displayed correspondingly to the video signal into at least two screen division areas, and correspondingly determining the number of the FPGA signal processing circuits according to the number of the screen division areas.
Preferably, in the embodiment of the present invention, the display screen is divided into an upper split screen area, a lower split screen area, a left split screen area, a right split screen area, and a plurality of sub FPGA signal processing circuits, where the sub FPGA signal processing circuits include two sub FPGA signal processing circuits corresponding to the two split screen areas, and the two sub FPGA signal processing circuits respectively complete video signal timing conversion of the two split screen areas and then transmit the video signal to the output encoding circuit.
In the embodiment of the invention, as shown in fig. 4, the display screen is divided into a left split screen area and a right split screen area, after the main FPGA signal processing circuit finishes signal processing of the high-speed serial electrical signal, the high-speed serial electrical signal is divided into a left split screen video signal and a right split screen video signal according to the split screen area and is input into the two split FPGA signal processing circuits, the left split FPGA signal processing circuit and the right split FPGA signal processing circuit respectively receive the left half image video signal and the right half image video signal, the signal time sequence conversion processing process of the left half screen image area and the right half screen image data area is.
The output coding circuit is connected with the output interface circuit and is used for synthesizing the plurality of video electric signals after the time sequence conversion is finished;
in the embodiment of the invention, the output coding circuit adopts an HDMI output coding circuit, and the HDMI output coding circuit comprises an HDMI coding and equalizing chip and is used for realizing the coding function of the serial video electric signals. For a plurality of video signals after the two sub FPGA signal processing circuits complete the time sequence conversion processing of the video electric signals, the HDMI output coding circuit codes the video electric signals and synthesizes a complete image signal and then transmits the complete image signal to the output interface circuit.
And the output interface circuit is used for outputting the complete video electric signal synthesized by the output coding circuit.
Preferably, the embodiment of the invention further comprises a sending end control circuit and a receiving end control circuit, wherein the sending end control circuit is connected with the input FPGA signal processing circuit, and the receiving end control circuit is connected with the main FPGA signal processing circuit and is used for controlling the receiving, sending and dispatching of the video signals in the device.
Preferably, in the embodiment of the present invention, the sending-end control circuit and the receiving-end control circuit each include an MPU master controller and a peripheral circuit connected to the MPU master controller. The MPU is used as a main controller of the control circuit, and has the functions of controlling the sending and dispatching of video signals and controlling the processing process of the video signals by the device. And the peripheral circuit connected with the MPU main controller is controlled by the MPU main controller and is used for completing a series of seat functions.
Preferably, the peripheral circuit in the embodiment of the present invention includes a USB interface circuit and a USB HUB interface circuit, where the USB interface circuit is used to import an external existing video data signal;
and the USB HUB interface circuit is used for accessing keyboard and mouse information and finishing the interaction between the optical fiber seats.
The embodiment of the invention comprises a USB interface circuit and a USB HUB interface circuit, wherein the USB interface circuit can lead in USB flash disk data signals, so that the device can read not only a real-time video source but also an existing video file, the specific signal processing process of the existing video signal is the same as the real-time video signal processing process, the signal processing process is completed through an FPGA signal processing circuit, and finally, the complete video signal is output through an HDMI output encoding circuit and an HDMI output interface circuit. The two USB HUB interface circuits are used for accessing keyboard and mouse information and finishing interaction between the optical fiber seats through the keyboard and mouse information.
Preferably, in the embodiment of the present invention, the peripheral circuit may further include a storage chip set circuit, an ethernet interface circuit, an RS232 debug circuit, an LCD control circuit, and an audio receiving and looping-out circuit, wherein a developer may simply debug the operating condition of the serial port real-time observation device through the RS232 debug circuit or debug the device circuit through the ethernet interface circuit in real time; the LCD control circuit is adopted to directly output the configuration information of the display device, so that the running state of the device can be observed conveniently in real time; and the audio receiving and loop-out circuit is used for accessing an audio signal to the video signal processing based on the embodiment, processing the audio signal and realizing the effect of outputting a complete image by combining the video and the audio.
Compared with the prior art, the embodiment of the invention has the beneficial effects that:
the embodiment of the invention provides a low-delay video optical fiber transmission device, based on the real-time processing technology of FPGA, compared with the prior art, the signal processing process finished by the original video data stream in the whole process from sending to receiving is extremely precise and simple, and simultaneously, the delay between the sending and receiving of video signals is greatly optimized due to the great reduction of cache data; in the whole signal processing process, the image quality of the original video signal is highly reserved, and the image quality reduction caused by different video coding is reduced; an optical module sending circuit and an optical module receiving circuit of the device are connected with the FPGA signal processing circuit, so that video signals do not need to be converted through an Ethernet protocol, and system design is simplified; and the maximum resolution supported by the device can reach 4k ultrahigh definition resolution. In addition, the receiving end circuit module of the device adopts a plurality of FPGA signal processing circuits to respectively complete different signal processing, compared with the situation that the whole function is completed by a single FPGA, the signal processing pressure of the main FPGA is reduced, the integration requirement of the main FPGA is reduced, the FPGA combination and the type selection are more flexible, the power consumption of the main FPGA is reduced, and the running reliability of the device is enhanced.
Example 2
As shown in fig. 5, fig. 5 is a control method of a low-latency video fiber transmission apparatus according to embodiment 2 of the present invention, where the control method includes the following steps:
s1, a sending end receives a video electric signal;
s2, decoding the video electric signal;
s3, serializing and coding the decoded video electric signal to obtain a serial video electric signal;
s4, converting the serial video electric signal into a serial video optical signal;
s5, sending the serial video optical signal to a receiving end;
s6, a receiving end receives the serial video optical signals and converts the serial video optical signals into serial video electrical signals;
s7, deserializing the serial video electrical signal, reducing the clock frequency of the deserialized video electrical signal, and shunting the processed video electrical signal into at least two sub video electrical signals;
s8, respectively carrying out time sequence conversion processing on the at least two sub video electric signals;
s9, synthesizing at least two sub-video electric signals after time sequence conversion into a complete video electric signal and carrying out coding processing;
and S10, outputting the coded complete video electric signal.
Preferably, in step S7 in this embodiment of the present invention, the number of the sub video electrical signals is determined as follows: the display screen corresponding to the video signal is divided into an upper split screen area, a lower split screen area, a left split screen area and a right split screen area, and the two split video electric signals are divided from the upper split screen area, the lower split screen area, the left split screen area and the right split screen area corresponding to the video electric signal.
In the embodiment of the method, the process of controlling the device to process the video signal comprises the following steps: firstly, a sending end is controlled to receive a real-time video electrical signal transmitted by an optical fiber, the real-time video electrical signal is decoded and restored to form an original video electrical signal, then the original video electrical signal after being decoded is serialized and encoded to form a serial video electrical signal, the serial video electrical signal is converted into a serial video optical signal through a control optical module, and finally the serial video optical signal is transmitted to a receiving end through the optical fiber; in the process of controlling the receiving end to process the video signals, firstly, the receiving end is controlled to receive real-time serial video optical signals sent by the sending end and convert the real-time serial video optical signals into serial video electrical signals, secondly, the serial video electrical signals are deserialized, the clock frequency of the video electrical signals is reduced, the main signal processing process is completed, two sub video electrical signals are divided into two sub video electrical signals according to the upper and lower or left and right sub screens of a display screen, then the two sub video electrical signals are respectively subjected to time sequence conversion and then are combined into a complete video electrical signal, and the receiving end outputs and displays the complete video electrical signal.
Compared with the prior art, the embodiment 2 of the invention has the following beneficial effects:
the invention relates to a control method of a low-delay video optical fiber transmission device, which is characterized in that a signal processing process performed on a video signal in the whole process from a sending end to a receiving end is controlled based on the real-time processing technology of an FPGA (field programmable gate array), compared with the prior art, the signal processing process is extremely precise and simple, and meanwhile, the delay problem in the sending and receiving periods of the video signal is greatly optimized due to the great reduction of cache data; in the whole signal processing process, the image quality of the original video signal is highly reserved, and the image quality reduction caused by different video coding is reduced; and the control method of the device enables the maximum resolution supported by the device to reach 4k ultra-high-definition resolution. In addition, the method reduces the power consumption of main signal processing by shunting a plurality of sub-video electric signals, so that the operation reliability of the system is enhanced.
It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the technical solutions of the present invention, and are not intended to limit the specific embodiments of the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the claims of the present invention should be included in the scope of protection of the claims of the present invention.
Claims (10)
1. A low-delay video optical fiber transmission device is characterized by comprising a transmitting end and a receiving end, wherein the transmitting end comprises an input interface circuit, an input decoding circuit, an input FPGA signal processing circuit and an optical module transmitting circuit,
the input interface circuit is connected with the decoding circuit and is used for receiving the video electrical signal transmitted by the optical fiber and transmitting the video electrical signal to the input decoding circuit;
the input decoding circuit is connected with the input FPGA signal processing circuit and is used for decoding the video electric signal and transmitting the decoded video electric signal to the input FPGA signal processing circuit;
the input FPGA signal processing circuit is connected with the optical module sending circuit and used for serializing and coding the decoded video electrical signal and transmitting the serialized and coded serial video electrical signal to the optical module sending circuit;
the optical module sending circuit is used for converting the serial video electric signal into a serial video optical signal and sending the serial video optical signal to a receiving end of the device;
the receiving end comprises an optical module receiving circuit, a main FPGA signal processing circuit, at least two sub FPGA signal processing circuits, an output coding circuit and an output interface circuit,
the optical module receiving circuit is connected with the main FPGA signal processing circuit and used for receiving the serial video optical signal sent by the optical module sending circuit, converting the serial video optical signal into a serial video electrical signal and inputting the serial video electrical signal to the main FPGA signal processing circuit;
the main FPGA signal processing circuit is connected with the at least two sub FPGA signal processing circuits and is used for deserializing the serial video electrical signal, reducing the clock frequency of the video electrical signal and respectively transmitting the processed video electrical signal to the at least two sub FPGA signal processing circuits;
the sub FPGA signal processing circuit is connected with the output coding circuit and is used for completing time sequence conversion on the video electric signal processed by the main FPGA signal processing circuit and transmitting the video electric signal to the output coding circuit;
the output coding circuit is connected with the output interface circuit and is used for synthesizing the plurality of video electric signals after the time sequence conversion is finished;
and the output interface circuit is used for outputting the complete video electric signal synthesized by the output coding circuit.
2. The low-latency video fiber transmission device according to claim 1, wherein the number of the sub-FPGA signal processing circuits is determined as follows: dividing a display screen displayed correspondingly to the video signal into at least two screen division areas, and correspondingly determining the number of the FPGA signal processing circuits according to the number of the screen division areas.
3. The low-latency video fiber transmission device according to claim 2, wherein the display screen is divided into two split screen areas, an upper split screen area, a lower split screen area, a left split screen area, a right split screen area, and a plurality of the sub FPGA signal processing circuits comprise two sub FPGA signal processing circuits corresponding to the two split screen areas,
and the two sub FPGA signal processing circuits respectively complete the time sequence conversion of the video signals of the two sub screen areas and then transmit the video signals to the output coding circuit.
4. The low-latency video fiber optic transmission device according to claim 1, further comprising a transmitting end control circuit and a receiving end control circuit,
the transmitting terminal control circuit is connected with the input FPGA signal processing circuit and is used for controlling the transceiving and scheduling of the video electric signals of the transmitting terminal;
and the receiving end control circuit is connected with the main FPGA signal processing circuit and is used for controlling the receiving, sending and dispatching of the video electric signals of the receiving end.
5. The low-latency video optical fiber transmission device according to claim 4, wherein the sending end control circuit and the receiving end control circuit each comprise an MPU master controller and a peripheral circuit connected with the MPU master controller, the MPU master controller of the sending end is connected with the input FPGA signal processing circuit, and the MPU master controller of the receiving end is connected with the main FPGA signal processing circuit.
6. The apparatus according to claim 5, wherein the peripheral circuit comprises a USB interface circuit and a USB HUB interface circuit,
the USB interface circuit is used for importing an external existing video data signal;
and the USB HUB interface circuit is used for accessing keyboard and mouse information and finishing the interaction between the optical fiber seats.
7. The apparatus according to claim 1, wherein the input interface circuit is an HDMI input interface circuit and/or a DP input interface circuit.
8. The apparatus according to claim 1, wherein the output interface circuit is an HDMI output interface circuit.
9. A control method of a low-latency video optical fiber transmission device is characterized by comprising the following steps:
s1, a sending end of a video optical fiber transmission device receives a video electric signal;
s2, decoding the video electric signal;
s3, serializing and coding the decoded video electric signal to obtain a serial video electric signal;
s4, converting the serial video electric signal into a serial video optical signal;
s5, sending the serial video optical signal to a receiving end of a video optical fiber transmission device;
s6, a receiving end receives the serial video optical signals and converts the serial video optical signals into serial video electrical signals;
s7, deserializing the serial video electrical signal, reducing the clock frequency of the deserialized video electrical signal, and shunting the processed video electrical signal into at least two sub video electrical signals;
s8, respectively carrying out time sequence conversion processing on the at least two sub video electric signals;
s9, synthesizing at least two sub-video electric signals after time sequence conversion into a complete video electric signal and carrying out coding processing;
and S10, outputting the coded complete video electric signal.
10. The method for controlling a low latency video fiber optic transmission apparatus according to claim 9, wherein in step S7, the number of the sub video electrical signals is determined by:
the display screen corresponding to the video signal is divided into an upper split screen area, a lower split screen area, a left split screen area and a right split screen area, and the video signal is divided into two split video signals corresponding to the upper split screen area, the lower split screen area, the left split screen area and the right split screen area.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111757128A (en) * | 2020-07-16 | 2020-10-09 | 威创集团股份有限公司 | Video coding system |
| WO2021129887A1 (en) * | 2019-12-23 | 2021-07-01 | 威创集团股份有限公司 | Video optical fiber seat receiving device |
| CN113784100A (en) * | 2021-09-30 | 2021-12-10 | 中国兵器装备集团上海电控研究所 | Modular GMSL video signal optical fiber transmission system |
| WO2022116352A1 (en) * | 2020-12-01 | 2022-06-09 | 威创集团股份有限公司 | 4k high-definition receiver box and video output system thereof |
| CN115942019A (en) * | 2021-08-20 | 2023-04-07 | 广州视源电子科技股份有限公司 | Information playing device |
| CN116193180A (en) * | 2022-12-15 | 2023-05-30 | 中国航空工业集团公司西安航空计算技术研究所 | Digital video transmission time sequence control method based on optical fiber channel |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150078383A1 (en) * | 2013-09-13 | 2015-03-19 | Smg Holdings--Anova Technologies, Inc. | High Payload Data Packet Transmission System and Relay to Lower Latency |
| CN108183749A (en) * | 2017-12-20 | 2018-06-19 | 中国航空工业集团公司洛阳电光设备研究所 | A kind of fiber optic communications devices of DVI videos and communication signal mixed transport |
| CN109413398A (en) * | 2018-12-05 | 2019-03-01 | 中航光电科技股份有限公司 | A kind of low delay resolution ratio adaptive video optical fiber transmission coding/decoding device |
| CN109413397A (en) * | 2018-12-05 | 2019-03-01 | 中航光电科技股份有限公司 | A kind of low delay resolution ratio adaptive video optical fiber transmission coding/decoding method |
-
2019
- 2019-12-23 CN CN201911340755.5A patent/CN111147828A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150078383A1 (en) * | 2013-09-13 | 2015-03-19 | Smg Holdings--Anova Technologies, Inc. | High Payload Data Packet Transmission System and Relay to Lower Latency |
| CN108183749A (en) * | 2017-12-20 | 2018-06-19 | 中国航空工业集团公司洛阳电光设备研究所 | A kind of fiber optic communications devices of DVI videos and communication signal mixed transport |
| CN109413398A (en) * | 2018-12-05 | 2019-03-01 | 中航光电科技股份有限公司 | A kind of low delay resolution ratio adaptive video optical fiber transmission coding/decoding device |
| CN109413397A (en) * | 2018-12-05 | 2019-03-01 | 中航光电科技股份有限公司 | A kind of low delay resolution ratio adaptive video optical fiber transmission coding/decoding method |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021129887A1 (en) * | 2019-12-23 | 2021-07-01 | 威创集团股份有限公司 | Video optical fiber seat receiving device |
| CN111757128A (en) * | 2020-07-16 | 2020-10-09 | 威创集团股份有限公司 | Video coding system |
| CN111757128B (en) * | 2020-07-16 | 2021-12-07 | 威创集团股份有限公司 | Video coding system |
| WO2022116352A1 (en) * | 2020-12-01 | 2022-06-09 | 威创集团股份有限公司 | 4k high-definition receiver box and video output system thereof |
| CN115942019A (en) * | 2021-08-20 | 2023-04-07 | 广州视源电子科技股份有限公司 | Information playing device |
| CN113784100A (en) * | 2021-09-30 | 2021-12-10 | 中国兵器装备集团上海电控研究所 | Modular GMSL video signal optical fiber transmission system |
| CN116193180A (en) * | 2022-12-15 | 2023-05-30 | 中国航空工业集团公司西安航空计算技术研究所 | Digital video transmission time sequence control method based on optical fiber channel |
| CN116193180B (en) * | 2022-12-15 | 2024-06-04 | 中国航空工业集团公司西安航空计算技术研究所 | Digital video transmission time sequence control method based on optical fiber channel |
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