CN111137846B - Preparation method of micron-level step height standard sample block - Google Patents
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- CN111137846B CN111137846B CN201911348036.8A CN201911348036A CN111137846B CN 111137846 B CN111137846 B CN 111137846B CN 201911348036 A CN201911348036 A CN 201911348036A CN 111137846 B CN111137846 B CN 111137846B
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- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
- B81C1/00523—Etching material
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Abstract
The invention is suitable for the technical field of standard substance preparation, and provides a preparation method of a micron-level step height standard sample block, which comprises the following steps: obtaining a first silicon wafer, growing a silicon dioxide oxidation layer on the first silicon wafer, and bonding a second silicon wafer on the silicon dioxide oxidation layer to obtain a first sample; thinning and polishing a second silicon wafer on the first sample to obtain a second sample; the thickness of the thinned second silicon wafer is the same as the preset nominal height; etching a preset area of a second silicon wafer on the second sample until the silicon dioxide oxide layer is exposed to obtain a third sample; and sputtering a metal protective layer on the upper surface of the third sample to obtain a micron-level step height standard sample block. The preparation method of the micron-sized step height standard sample block has relatively low preparation cost, and can obtain good surface roughness while obtaining the micron-sized step height standard sample block with the preset nominal height.
Description
Technical Field
The invention belongs to the technical field of standard substance preparation, and particularly relates to a preparation method of a micron-level step height standard sample block.
Background
A step height standard sample block with micron magnitude developed abroad is prepared by using a mask as a substrate and adopting a dry etching process. The sample block prepared by the method has good parallelism and uniformity and small roughness, and can meet the requirement of calibrating step measuring instruments in the semiconductor industry. But the processing technology for preparing the standard sample block with the step height by using the mask as the substrate is complex and has high cost. The nominal height range of the step height sample block with the micron magnitude developed in China is 2-100 mu m. The preparation of the sample block is based on an integrated circuit and a Micro-Electro-Mechanical Systems (MEMS) etching process, and a silicon wafer is used as a substrate, and the step height standard sample block is obtained by etching on the silicon wafer. Wherein, a Reactive-Ion-Etching (RIE) process is generally adopted for the step height standard sample block with the nominal height of less than 10 μm, and the Etching depth is the nominal height of the step height standard sample block; for the step height standard sample block with the nominal height of more than 10 μm, a Deep-Reactive-Ion-Etching (DRIE) process is generally adopted, and when the Etching depth is close to the expected size, a wet Etching process is adopted to smooth the bottom surface of the step.
However, the surface roughness of the step height standard block having a nominal height of 10 μm or less prepared by the RIE process is generally about 0.5nm. The surface roughness range of the step height standard sample block with the nominal height of more than 10 mu m prepared by combining the DRIE process and the wet etching process is about 6 nm-10 nm, and the step height standard sample block with the nominal height of more than 10 mu m has the surface roughness still far higher than that of the step height standard sample block with the nominal height of less than 10 mu m prepared by the RIE process although the bottom surface of the step is subjected to smooth treatment by using the wet etching process to reduce the surface roughness. However, the limit size of the RIE etching process is 10 μm, and it is difficult to etch deeper steps.
Disclosure of Invention
In view of this, the embodiment of the present invention provides a method for preparing a micron-scale step height standard sample block, so as to solve the problems that in the prior art, the preparation cost of the micron-scale step height standard sample block is high, and the thickness and the surface roughness of the prepared micron-scale step height standard sample block cannot be considered at the same time.
The first aspect of the embodiment of the invention provides a method for preparing a micron-scale step height standard sample block, which comprises the following steps:
obtaining a first silicon wafer, growing a silicon dioxide oxidation layer on the first silicon wafer, and bonding a second silicon wafer on the silicon dioxide oxidation layer to obtain a first sample;
thinning and polishing the second silicon wafer on the first sample to obtain a second sample; the thickness of the thinned second silicon wafer is the same as the preset nominal height;
etching a preset area of a second silicon wafer on the second sample until the silicon dioxide oxide layer is exposed to obtain a third sample;
and sputtering a metal protective layer on the upper surface of the third sample to obtain a micron-level step height standard sample block.
Optionally, the obtaining the first silicon wafer includes:
and carrying out double-sided polishing on the silicon wafer, and cleaning and spin-drying the silicon wafer after double-sided polishing to obtain a first silicon wafer.
Optionally, the bonding a second silicon wafer on the silicon dioxide oxide layer to obtain a first sample includes:
cleaning the first silicon wafer and the second silicon wafer after the silicon dioxide oxide layer grows by using a first electronic cleaning solution to obtain a cleaned first silicon wafer and a cleaned second silicon wafer;
and bonding a second cleaned silicon wafer on the silicon dioxide oxide layer of the first cleaned silicon wafer to obtain a first sample.
Optionally, the performing polishing treatment to obtain a second sample includes:
putting the thinned first sample into an etching solution to etch the damaged layer of the second silicon wafer on the first sample;
cleaning the first sample with ultrasonic waves after the damage layer is corroded;
and polishing the second silicon wafer on the first sample after ultrasonic cleaning based on a chemical mechanical polishing process to obtain a second sample.
Optionally, the etching a preset region of a second silicon wafer on the second sample until the silicon dioxide oxide layer is exposed to obtain a third sample, including:
spin-coating a layer of photoresist on a second silicon wafer of the second sample, and performing photoetching on the photoresist to obtain a photoresist mask, wherein the photoresist mask is a hollow rectangular frame;
etching a second silicon wafer, which is not covered by the photoresist mask, on the second sample based on a deep reactive ion etching process until the silicon dioxide oxide layer is exposed;
and removing the photoresist mask to obtain a third sample.
Optionally, spin-coating a layer of photoresist on the second silicon wafer of the second sample, and performing photolithography on the photoresist to obtain a photoresist mask, including:
spin-coating a layer of photoresist on a second silicon wafer of the second sample and baking;
exposing the photoresist by using deep ultraviolet light;
and developing and baking the exposed photoresist in NaOH solution to obtain a photoresist mask.
Optionally, the etching, based on the deep reactive ion etching process, the second silicon wafer on the second sample that is not covered by the photoresist mask includes:
and etching the second silicon wafer which is not covered by the photoresist mask on the second sample by using etching gas at a preset etching rate.
Optionally, the etching gas includes: sulfur hexafluoride and octafluorocyclobutane;
the preset etching rate is 3-5 mu m/min.
Optionally, the thickness of the silicon dioxide oxide layer is 100nm to 200nm;
the thickness of the metal protective layer is 80 nm-150 nm.
Optionally, the sputtering of the metal protective layer on the upper surface of the third sample to obtain the micron-sized step height standard sample block includes:
and sputtering metal chromium with the thickness of 90nm on the upper surface of the third sample to obtain a micron-scale step height standard sample block.
Compared with the prior art, the embodiment of the invention has the following beneficial effects: the method comprises the steps of growing a silicon dioxide oxidation layer on a first silicon wafer by taking the first silicon wafer as a substrate, bonding a second silicon wafer on the silicon dioxide oxidation layer to obtain a first sample, thinning and polishing the second silicon wafer on the first sample to obtain a second sample, obtaining the second silicon wafer with the same preset nominal height by thinning, and obtaining better surface roughness by polishing the thinned second silicon wafer. On the basis, a preset area of a second silicon wafer on a second sample is etched until a silicon dioxide oxide layer is exposed, a third sample with a preset nominal height and good surface roughness can be obtained, a metal protective layer is sputtered on the upper surface of the third sample to protect the third sample with the preset nominal height, and a micron-scale step height standard sample block with better stability is obtained. The micron-scale step height standard sample block prepared by the embodiment of the invention has relatively low preparation cost, and can obtain better surface roughness while obtaining the desired nominal height.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic flow chart of an implementation of a method for preparing a micrometer-scale step height standard sample block according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a first silicon wafer according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a silicon dioxide oxide layer grown on a first silicon wafer according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a first sample provided in an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a second silicon wafer on a first sample after thinning processing according to an embodiment of the present invention;
FIG. 6 is a schematic flow chart of obtaining a third sample according to an embodiment of the present invention;
FIG. 7 is a schematic diagram illustrating a structure of spin-coating a layer of photoresist on a second silicon wafer of a second sample according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of an embodiment of the present invention for exposing a photoresist with deep ultraviolet light;
FIG. 9 is a schematic diagram of a developed structure according to an embodiment of the present invention;
FIG. 10 is a schematic structural diagram of a second silicon wafer on a second sample that is not covered by a photoresist mask after etching according to an embodiment of the present invention;
FIG. 11 is a schematic structural diagram illustrating a photoresist mask removal process according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram after sputtering a metal protection layer according to an embodiment of the present invention.
In the figure, 1-a first silicon wafer; 2-a silicon dioxide oxide layer; 3-a second silicon wafer; 31-the thinned second silicon wafer; 4-photoresist; 41-photoresist mask; 5-metal protective layer.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
In order to explain the technical means of the present invention, the following description will be given by way of specific examples.
Fig. 1 is a schematic flow chart of an implementation of a method for preparing a standard sample block with a micron-scale step height according to an embodiment of the present invention, which is described in detail below.
Step S101, a first silicon wafer is obtained, a silicon dioxide oxide layer grows on the first silicon wafer, and a second silicon wafer is bonded on the silicon dioxide oxide layer, so that a first sample is obtained.
Alternatively, referring to fig. 2, the silicon wafer may be subjected to double-sided polishing, and the silicon wafer after double-sided polishing is cleaned and spun to obtain a first silicon wafer 1. The silicon wafer with double-sided polishing is used as a substrate material, and is cleaned and dried, so that different impurities can be cleaned, and a good base is provided for the subsequent growth of a silicon dioxide oxide layer.
Alternatively, referring to fig. 3, a silicon dioxide oxide layer 2 is grown on the first silicon wafer 1, the silicon dioxide oxide layer 2 may be grown by using a thermal oxidation process, and the thickness of the silicon dioxide oxide layer 2 may be 100nm to 200nm.
The silicon dioxide oxide layer is grown by a thermal oxidation process, namely, a compact silicon dioxide film is generated on the surface of the first silicon wafer 1 when the first silicon wafer 1 and the gas containing the oxide substance are subjected to chemical reaction at high temperature. The thermal oxidation process can be divided into dry oxygen oxidation, water vapor oxidation and wet oxygen oxidation according to the used oxidation atmosphere, wherein the dry oxygen oxidation takes dry pure oxygen as the oxidation atmosphere, and the oxygen directly reacts with silicon at high temperature to generate silicon dioxide. The steam oxidation is to take high-purity steam as an oxidation atmosphere and react silicon atoms on the surface of a silicon wafer with water molecules to generate silicon dioxide. The oxidation rate of the water vapor oxidation is greater than that of the dry oxygen oxidation. Whereas wet oxygen oxidation is essentially a mixture of dry oxygen oxidation and water vapor oxidation, with oxidation rates in between. In the embodiment of the invention, a proper oxidation mode can be selected according to actual conditions.
Optionally, referring to fig. 4, bonding a second silicon wafer 3 on the silicon dioxide oxide layer 2 to obtain a first sample, and cleaning the first silicon wafer 1 and the second silicon wafer 3 after growing the silicon dioxide oxide layer 2 with a first electronic cleaning solution to obtain a cleaned first silicon wafer and a cleaned second silicon wafer; and bonding the cleaned second silicon wafer on the silicon dioxide oxide layer of the cleaned first silicon wafer to obtain a first sample.
Optionally, in this step, after the first sample is obtained, a high-temperature annealing treatment may be performed on the obtained first sample.
The cleaned second silicon wafer is bonded on the silicon dioxide oxide layer of the cleaned first silicon wafer, namely the cleaned first silicon wafer and the cleaned second silicon wafer are adhered together at room temperature, and then the upper surface of the cleaned first silicon wafer and the cleaned second silicon wafer are subjected to severe physical and chemical reactions through high-temperature annealing treatment, so that chemical covalent bonds with high strength are formed, and the bonding strength is increased to form a unified whole.
And step S102, performing thinning processing and polishing processing on the second silicon wafer on the first sample to obtain a second sample.
Referring to fig. 5, after the second silicon wafer 3 on the first sample is thinned, a thinned second silicon wafer 31 is obtained, wherein the thickness of the thinned second silicon wafer 31 is the same as the preset nominal height. For example, if a micrometer-scale step height standard block with a preset nominal height of 150 μm is desired, a thinning machine can be used to thin the second silicon wafer on the first sample to 150 μm.
Optionally, in this step, polishing is performed on the second silicon wafer on the first sample, and the thinned first sample may be placed in an etching solution to etch the damaged layer of the second silicon wafer on the first sample; cleaning the first sample after corroding the damaged layer by using ultrasonic; and polishing the second silicon wafer on the first sample after ultrasonic cleaning based on a chemical mechanical polishing process to obtain a second sample.
And putting the thinned first sample into a corrosive liquid, corroding the damaged layer of the second silicon wafer caused by thinning, and removing the damaged layer of the second silicon wafer on the first sample. And the first sample after the damage layer is corroded is cleaned by ultrasonic, so that residual corrosive liquid on the corroded first sample can be removed.
After the above treatment, the first sample after ultrasonic cleaning is put into a polishing machine, and the second silicon wafer on the first sample after ultrasonic cleaning is polished by using a Chemical-Mechanical polishing (CMP) process, so that the roughness of the second silicon wafer on the first sample after ultrasonic cleaning is reduced.
The CMP process is a process of planarizing a silicon wafer or other substrate material during processing by chemical etching and mechanical force. The CMP process integrates the advantages of chemical grinding and mechanical grinding, is simple in chemical grinding, high in surface precision, low in damage, good in integrity, not easy to cause surface/sub-surface damage, but low in grinding speed, low in material removal efficiency, incapable of correcting surface type precision and poor in grinding consistency. The grinding consistency is good, the surface flatness is high, the grinding efficiency is high, but the surface layer/sub-surface layer damage is easy to occur, and the surface roughness value is lower. The CMP process absorbs the respective advantages of the two, can obtain a perfect surface while ensuring the material removal efficiency, obtains the flatness 1-2 orders of magnitude higher than that of the two grinding methods, and can realize the surface roughness from nano level to atomic level.
Optionally, after the second sample is obtained by the polishing process, the second sample is washed in a second washing solution.
Step S103, etching the preset area of the second silicon wafer on the second sample until the silicon dioxide oxide layer is exposed, and obtaining a third sample.
After the second silicon wafer with the preset nominal height and the better surface roughness is obtained, the preset area of the second silicon wafer on the second sample can be etched until the silicon dioxide oxide layer is exposed, so that preparation is made for preparing the micron-level step height standard sample block.
Alternatively, referring to fig. 6, etching a predetermined region of the second silicon wafer on the second sample until the silicon dioxide oxide layer is exposed to obtain a third sample may include the following steps.
And step S1031, spin-coating a layer of photoresist on the second silicon wafer of the second sample, and performing photoetching on the photoresist to obtain a photoresist mask.
The photoresist mask is a hollow rectangular frame, the rectangular frame comprises an inner rectangle and an outer rectangle, the length of the inner rectangle is 2 mm-3 mm, the width of the inner rectangle is 0.5 mm-1.5 mm, and the inner rectangle and the outer rectangle are not in contact with each other.
Optionally, referring to fig. 7, in this step, a layer of photoresist 4 may be spin-coated on a second silicon wafer of a second sample and baked, the photoresist 4 is exposed by using deep ultraviolet light, and the exposed photoresist is developed and baked in a NaOH solution, so as to obtain a photoresist mask 41.
Referring to fig. 8 and 9, when exposing the photoresist 4 with deep ultraviolet light, the mask used may be a negative mask, and the image area of the mask is a light-transmitting area. When the exposed photoresist is developed in NaOH solution, the photoresist corresponding to the image area of the mask is removed, and the photoresist mask 41 in the form of a hollow rectangular frame is obtained.
Step S1032 etches the second silicon wafer not covered by the photoresist mask on the second sample based on the deep reactive ion etching process until the silicon dioxide oxide layer is exposed.
Referring to fig. 10, for the step height standard sample block with a preset nominal height of more than 10 μm, a deep reactive ion etching process is generally used for etching, and the etching is stopped when a silicon dioxide oxide layer is etched. Because the surface roughness of the silicon dioxide oxide layer is good, and the second silicon wafer which is not etched is polished, a step-shaped structure with good surface roughness and a preset nominal thickness can be obtained after a preset area of the second silicon wafer is etched.
Optionally, in this step, etching gases of sulfur hexafluoride SF6 and octafluorocyclobutane C4F8 may be used to etch the second silicon wafer, which is not covered by the photoresist mask 41, on the second sample at an etching rate of 3 μm/min to 5 μm/min until the silicon dioxide oxide layer is exposed.
Step S1033, the photoresist mask is removed, and a third sample is obtained.
Fig. 11 is a schematic structural diagram after the photoresist mask is removed, and the photoresist mask 41 may be removed by using an acetone solution to obtain a third sample.
And step S104, sputtering a metal protective layer on the upper surface of the third sample to obtain a micron-level step height standard sample block.
The thickness of the metal protection layer 5 may be 80nm to 150nm, and as the metal protection layer is as shown in fig. 12, a layer of the metal protection layer 5 is uniformly covered on the third sample, that is, the stepped upper surface of the third sample block is increased by the same height, so that the height of the step of the third sample block is not affected after the metal protection layer is sputtered.
Optionally, metal chromium with a thickness of 90nm may be sputtered on the upper surface of the third sample to obtain a micron-scale step height standard sample block.
The sputtering metal protection layer can protect the third sample, after the second silicon wafer on the second sample is etched, the upper surface of the obtained step-shaped third sample is silicon, part of the third sample is silicon dioxide, the silicon is easy to oxidize, if the metal protection layer is not sputtered, the third sample is directly exposed in the air, the part of the upper surface of the third sample, which is silicon, can be subjected to oxidation reaction, the step-shaped height of the third sample can be changed, the micron-level step height standard sample block is used as a standard substance, and the stability of the micron-level step height standard sample block cannot be guaranteed.
In addition, the application range of the micron-level step height standard sample block can be increased by sputtering the metal protective layer, the step instrument generally calibrated by using the micron-level step height standard sample block comprises a contact pin type step instrument and an optical type step instrument, the optical step instrument measurement has certain limitation, and can not measure semi-permeable membranes such as silicon dioxide and the like, the prepared micron-level step height standard sample block can not be used for calibrating the optical step instrument, the limitation of the optical step instrument measurement can be avoided after sputtering a layer of metal protective layer, and the application range of the micron-level step height standard sample block is expanded.
The preparation method of the micron-scale step height standard sample block comprises the steps of obtaining a first silicon wafer, growing a silicon dioxide oxidation layer on the first silicon wafer by taking the first silicon wafer as a substrate, bonding a second silicon wafer on the silicon dioxide oxidation layer to obtain a first sample, thinning and polishing the second silicon wafer on the first sample to obtain a second sample, obtaining the second silicon wafer with the same preset nominal height through thinning, and enabling the surface roughness of the thinned second silicon wafer to be lower through polishing to obtain better surface roughness. On the basis, a preset area of a second silicon wafer on a second sample is etched until a silicon dioxide oxide layer is exposed, a third sample with a preset nominal height and good surface roughness can be obtained, a metal protective layer is sputtered on the upper surface of the third sample to protect the third sample with the preset nominal height, and a micron-scale step height standard sample block with better stability is obtained.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by functions and internal logic of the process, and should not limit the implementation process of the embodiments of the present invention in any way.
The above-mentioned embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the embodiments of the present invention, and they should be construed as being included therein.
Claims (10)
1. A preparation method of a micron-level step height standard sample block is characterized by comprising the following steps:
obtaining a first silicon wafer, growing a silicon dioxide oxide layer on the first silicon wafer, and bonding a second silicon wafer on the silicon dioxide oxide layer to obtain a first sample;
thinning and polishing the second silicon wafer on the first sample to obtain a second sample; the thickness of the second thinned silicon wafer is the same as the preset nominal height; the preset nominal height is more than 10 mu m;
etching a preset area of a second silicon wafer on the second sample until the silicon dioxide oxide layer is exposed to obtain a third sample;
and sputtering a metal protective layer on the upper surface of the third sample to obtain a micron-level step height standard sample block.
2. The method of claim 1, wherein the obtaining a first silicon wafer comprises:
and carrying out double-sided polishing on the silicon wafer, and cleaning and spin-drying the silicon wafer after double-sided polishing to obtain a first silicon wafer.
3. The method according to claim 1, wherein the step of bonding a second silicon wafer on the silicon dioxide oxide layer to obtain a first sample comprises:
cleaning the first silicon wafer and the second silicon wafer after the silicon dioxide oxide layer grows by using a first electronic cleaning solution to obtain a first cleaned silicon wafer and a second cleaned silicon wafer;
and bonding the cleaned second silicon wafer on the silicon dioxide oxide layer of the cleaned first silicon wafer to obtain a first sample.
4. The method for preparing a micrometer-scale step height standard block according to claim 1, wherein the polishing process to obtain a second sample comprises:
putting the thinned first sample into an etching solution to etch the damaged layer of the second silicon wafer on the first sample;
cleaning the first sample after corroding the damaged layer by using ultrasonic;
and polishing the second silicon wafer on the first sample after ultrasonic cleaning based on a chemical mechanical polishing process to obtain a second sample.
5. The method for preparing the micron-sized step height standard sample block as claimed in claim 4, wherein the step of etching the predetermined region of the second silicon wafer on the second sample until the silicon dioxide oxide layer is exposed to obtain a third sample comprises the steps of:
spin-coating a layer of photoresist on a second silicon wafer of the second sample, and performing photoetching on the photoresist to obtain a photoresist mask, wherein the photoresist mask is a hollow rectangular frame;
etching a second silicon wafer, which is not covered by the photoresist mask, on the second sample based on a deep reactive ion etching process until the silicon dioxide oxide layer is exposed;
and removing the photoresist mask to obtain a third sample.
6. The method according to claim 5, wherein spin-coating a layer of photoresist on the second silicon wafer of the second sample and performing photolithography on the photoresist to obtain a photoresist mask comprises:
spin-coating a layer of photoresist on a second silicon wafer of the second sample and baking;
exposing the photoresist by using deep ultraviolet light;
and developing and baking the exposed photoresist in NaOH solution to obtain a photoresist mask.
7. The method for preparing a micrometer-scale step height standard sample block according to claim 5, wherein the etching a second silicon wafer on the second sample that is not covered by the photoresist mask based on a deep reactive ion etching process comprises:
and etching the second silicon wafer which is not covered by the photoresist mask on the second sample by using etching gas at a preset etching rate.
8. The method of preparing a micron-sized step height master piece according to claim 7,
the etching gas includes: sulfur hexafluoride and octafluorocyclobutane;
the preset etching rate is 3-5 mu m/min.
9. The method for preparing a micro-scale step height master piece according to any one of claims 1 to 8,
the thickness of the silicon dioxide oxide layer is 100 nm-200 nm;
the thickness of the metal protective layer is 80 nm-150 nm.
10. The method according to claim 9, wherein the step height block is obtained by sputtering a metal protective layer on the third sample, and the step height block comprises:
and sputtering metal chromium with the thickness of 90nm on the upper surface of the third sample to obtain a micron-scale step height standard sample block.
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| CN107993956A (en) * | 2017-11-29 | 2018-05-04 | 中国电子科技集团公司第十三研究所 | The preparation method of line-spacing standard sample of photo |
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