CN111083716A - Cell searching method and device based on FPGA - Google Patents
Cell searching method and device based on FPGA Download PDFInfo
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- CN111083716A CN111083716A CN201811228708.7A CN201811228708A CN111083716A CN 111083716 A CN111083716 A CN 111083716A CN 201811228708 A CN201811228708 A CN 201811228708A CN 111083716 A CN111083716 A CN 111083716A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W24/00—Supervisory, monitoring or testing arrangements
- H04W24/02—Arrangements for optimising operational condition
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2655—Synchronisation arrangements
- H04L27/2657—Carrier synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W56/00—Synchronisation arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
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- H04W56/0035—Synchronisation arrangements detecting errors in frequency or phase
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Abstract
The application discloses a cell searching method based on an FPGA, which comprises the following steps: changing the search period of the physical cell identity PCI from 10ms to 40ms, and sharing a cell search module by multiple cells; when the cell search is carried out for the first time, the correlation of the primary synchronization sequence is completed within the time length of 5ms, and the timing position is determined after the correlation of the secondary synchronization sequence is completed; for the cell search except for the first time, only the correlation of the primary synchronization sequence is needed, and the timing position is updated by searching within the time length set near the last determined timing position. The application also discloses corresponding cell search equipment based on the FPGA. By applying the technical scheme disclosed by the application, the PCI detection, the real-time synchronization and the frequency synchronization of multiple cells can be realized under the LTE multi-cell scene, and the resource allocation is optimized.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a cell search method and device based on an FPGA in an LTE multi-cell scenario.
Background
At present, the instruments used for network construction, maintenance and optimization in the market mainly comprise: road tester, protocol analyzer, frequency scanner, spectrum analyzer, base station tester, error code meter, etc. The instrument equipment can provide perfect supporting support for the radio frequency index test of the construction, operation and maintenance departments of operators and network excellent departments of equipment manufacturers, and the frequency spectrum monitoring, management and interference elimination of the national wireless committee. Since there are multiple operators and multiple cells simultaneously covered in a wireless environment, the capability of supporting multi-cell monitoring by a meter device is required.
The existing cell search process includes:
1. performing down-sampling and FIR filtering;
2. performing primary synchronization correlation, and confirming a 5ms timing position and a sector ID;
3. performing coarse frequency offset estimation by using the master synchronization sequence, and outputting frequency offset for frequency offset compensation;
4. performing secondary synchronization sequence correlation, and confirming a timing position of 10 ms;
5. and determining a Physical Cell Identity (PCI) according to the correlation result of the primary and secondary synchronization sequences.
A current 4-cell parallel monitoring method is shown in fig. 1.
According to fig. 1, the existing solution needs to instantiate four cell search modules respectively to complete the cell search process in parallel. Because DDC, FIR, correlation and other algorithms are involved in the cell search process, the consumption of multipliers is high, and therefore the resource overhead of the parallel instantiated four cell search modules to the FPGA is high.
Disclosure of Invention
The application provides a cell search method and device based on an FPGA (field programmable gate array), which can realize PCI (peripheral component interconnect) detection, real-time synchronization and frequency synchronization of multiple cells and optimize resource allocation in an LTE (long term evolution) multi-cell scene.
The application provides a cell search method based on an FPGA, which comprises the following steps:
changing the search period of the physical cell identity PCI from 10ms to 40ms, and sharing a cell search module by multiple cells;
when the cell search is carried out for the first time, the correlation of the primary synchronization sequence is completed within the time length of 5ms, and the timing position is determined after the correlation of the secondary synchronization sequence is completed;
for the cell search except for the first time, only the correlation of the primary synchronization sequence is needed, and the timing position is updated by searching within the time length set near the last determined timing position.
Preferably, the method further comprises:
and in the time period for carrying out the secondary synchronization sequence correlation, utilizing an idle primary synchronization sequence correlation module to carry out the timing calibration of multiple cells.
Preferably, the method further comprises:
and in the time period relevant to the auxiliary synchronization sequence, serially performing coarse frequency offset estimation and outputting a frequency offset result of multiple cells.
Preferably, the independent instantiated cell search module processes the cell search process of each cell in series.
The application also discloses a cell search device based on FPGA, a cell search module in the device is shared by multiple cells, including: the device comprises a main synchronization sequence correlation module, an auxiliary synchronization sequence correlation module and a coarse frequency offset estimation module, wherein:
the primary synchronization sequence correlation module completes primary synchronization sequence correlation within a time length of 5ms when cell search is carried out for the first time, and determines a timing position after secondary synchronization sequence correlation is completed; for the cell search except for the first time, only the correlation of the primary synchronization sequence is needed, the search is carried out within the time length set near the timing position determined last time, and the timing position is updated;
the cell search module is used for changing the search period of the PCI from 10ms to 40 ms.
Preferably, the primary synchronization sequence correlation module is configured to perform timing calibration of multiple cells by using idle in a time period when the secondary synchronization sequence correlation module performs secondary synchronization sequence correlation.
Preferably, the coarse frequency offset estimation module is configured to perform coarse frequency offset estimation in series and output a frequency offset result of multiple cells.
Preferably, the cell search module is instantiated independently for serially processing the cell search process of each cell.
The present application also discloses a non-transitory computer readable storage medium storing instructions that, when executed by a processor, cause the processor to perform the steps of the FPGA-based cell search method as previously described.
The application also discloses an electronic device comprising the non-volatile computer-readable storage medium as described above, and the processor having access to the non-volatile computer-readable storage medium.
According to the technical scheme, the method and the device for searching the cell based on the FPGA under the LTE multi-cell scene utilize the timing position during the first cell search to take out data near the timing position for processing, so that the search data volume is reduced, the synchronization is carried out by utilizing the main synchronization sequence, and the timing calibration is carried out on the basis, so that the search operation volume during the second search is reduced. The cell search module is instantiated independently, the main synchronization sequence correlation module and the auxiliary synchronization sequence correlation module are controlled independently, multiple cells share one cell search module, the main synchronization sequence correlation module is used for carrying out timing correction when the auxiliary synchronization sequence correlation is carried out by utilizing the characteristic of FPGA parallel operation, and coarse frequency offset estimation is carried out. The scheme is easy to realize and convenient to control, and reduces the resource consumption of the FPGA instantiated cell search module.
In the LTE timing synchronization process, after 10ms timing synchronization is finished, data near the synchronization position can be taken out by using the last timing synchronization position, the data searching amount is reduced, synchronization is carried out by using a main synchronization sequence, and timing calibration is carried out on the basis, so that the searching calculation amount in the secondary searching process is reduced.
In addition, the method utilizes the time related to the auxiliary synchronization, multiplexes a main synchronization sequence related module in a second half frame of the LTE, combines a protection point one method to perform secondary search so as to reduce the operation amount, multiplexes a down-sampling and coarse frequency offset estimation module, and performs serial processing to perform timing position calibration and frequency offset estimation of multiple cells.
Drawings
Fig. 1 is a schematic diagram of a conventional 4-cell parallel monitoring method;
FIG. 2 is a timing diagram of a conventional cell search procedure implemented in modules;
FIG. 3 is a schematic diagram of the present application searching for a timing position;
FIG. 4 is a timing diagram illustrating a block-based implementation of a cell search process according to the present application;
fig. 5 is a schematic diagram illustrating division of modules for cell search according to the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is further described in detail below by referring to the accompanying drawings and examples.
The conventional cell search procedure is: firstly, DDC and FIR are carried out, then, 5ms data is used for carrying out primary synchronization sequence correlation, 5ms synchronization position and sector ID results are determined, then, coarse frequency offset estimation and auxiliary synchronization sequence correlation are carried out, the operations can be carried out in parallel, afterwards, a frequency offset estimation module outputs frequency offset, and an auxiliary synchronization correlation module confirms 10ms synchronization position and PCI. The timing diagram of the sub-block implementation is shown in fig. 2.
In order to reduce FPGA resource consumption, the architecture of the cell search module is modified to support the cell search function of multiple cells. The output items of the cell search function are PCI, timing position and frequency offset estimation results, and the improvement of the application on the prior art comprises the following steps:
1. since the PCI of the cell is determined, and the PCI will not change frequently unless the location of the cell changes and the surrounding cells change, the search period of the PCI may be changed from 10ms to 40 ms. This allows serial utilization of the cell search modules to reduce resource consumption.
2. For the timing position, besides the first search needs to complete the correlation of the primary synchronization sequence in 5ms and determine the timing position after completing the correlation of the secondary synchronization sequence, the subsequent search can be performed near the last timing position based on the last result, as shown in fig. 3, so that the data length used for the search is reduced, and only the primary synchronization sequence needs to be used for timing calibration. In addition, the method and the device can utilize an idle main synchronization sequence correlation module to carry out timing calibration of multiple cells in a time period for carrying out secondary synchronization sequence correlation.
3. The coarse frequency offset estimation can also be performed in series in the time period related to the secondary synchronization sequence, and the frequency offset result of multiple cells is output.
Specifically, the cell search method based on the FPGA provided in the present application includes:
changing the search period of Physical Cell Identity (PCI) from 10ms to 40ms, and sharing a cell search module by multiple cells;
when the cell search is carried out for the first time, the correlation of the primary synchronization sequence is completed within the time length of 5ms, and the timing position is determined after the correlation of the secondary synchronization sequence is completed;
for the cell search except for the first time, only the correlation of the primary synchronization sequence is needed, and the timing position is updated by searching within the time length set near the last determined timing position.
Preferably, the method further comprises: and in the time period for carrying out the secondary synchronization sequence correlation, utilizing an idle primary synchronization sequence correlation module to carry out the timing calibration of multiple cells. And in the time period relevant to the auxiliary synchronization sequence, serially performing coarse frequency offset estimation and outputting a frequency offset result of multiple cells.
In addition, the independent instantiated cell search module serially processes the cell search process of each cell.
A timing diagram of a modified cell search flow sub-module implementation of the present application is shown in fig. 4. According to the modified timing sequence, a complete cell search process of 1 cell and a timing calibration and frequency offset estimation process of 3 cells can be processed in a 10ms period.
Referring to fig. 4, a complete procedure is performed in the cell 0, and only the frequency offset compensation and timing calibration procedures are performed in the other cells, where the left oblique line shows the time that the cell 0 occupies the module, the right oblique line shows the time that the cell 1 occupies the module, the grid line shows the time that the cell 2 occupies the module, and the dot shows the time that the cell 3 occupies the module. Therefore, the complete cell search process of one cell, the frequency offset estimation and the timing calibration functions of three cells can be completed within one 10ms period. And in the next 10ms period, the frequency is converted into a cell 1 to carry out a complete search process, and cells 0,2 and 3 only carry out frequency offset compensation and timing calibration processes, and so on. Therefore, the period for updating the PCI of each cell is 40ms, and only frequency offset compensation and timing calibration are performed in each of the remaining 10ms periods.
The modified module division is shown in fig. 5:
the cell search module is instantiated independently, serially processes the cell search process of each cell, needs to add a function of acquiring a timing position from the current cell during timing calibration, takes out data near the timing position according to the current timing condition to perform the timing calibration process, and outputs a coarse frequency offset estimation result of the cell.
All modules are serially multiplexed, so that a multi-cell scheme can be realized under the condition of not increasing resource consumption, the resource consumption of the FPGA is greatly saved, the resource consumption of a 4-cell scheme can be saved by 25% of the original resource consumption, and more resources can be reserved to support the processing capacity of more cells.
According to fig. 5, the cell search device based on FPGA provided in the present application, where a cell search module is shared by multiple cells, includes: the device comprises a main synchronization sequence correlation module, an auxiliary synchronization sequence correlation module and a coarse frequency offset estimation module, wherein:
the primary synchronization sequence correlation module completes primary synchronization sequence correlation within a time length of 5ms when cell search is carried out for the first time, and determines a timing position after the secondary synchronization sequence correlation is completed; for the cell search except for the first time, only the correlation of the primary synchronization sequence is needed, the search is carried out within the time length set near the timing position determined last time, and the timing position is updated;
the cell search module is used for changing the search period of the PCI from 10ms to 40 ms.
Preferably, the primary synchronization sequence correlation module is configured to perform multi-cell timing calibration by using idle in a time period when the secondary synchronization sequence correlation module performs secondary synchronization sequence correlation.
The coarse frequency offset estimation module is used for performing coarse frequency offset estimation in series and outputting frequency offset results of multiple cells.
The cell search module is instantiated independently for serially processing the cell search process of each cell.
Furthermore, the present application also provides a non-transitory computer readable storage medium storing instructions that, when executed by a processor, cause the processor to perform the steps of the FPGA-based cell search method as described above.
Further, the present application provides an electronic device comprising the non-volatile computer-readable storage medium as described above, and the processor having access to the non-volatile computer-readable storage medium.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.
Claims (10)
1. A cell search method based on FPGA is characterized by comprising the following steps:
changing the search period of the physical cell identity PCI from 10ms to 40ms, and sharing a cell search module by multiple cells;
when the cell search is carried out for the first time, the correlation of the primary synchronization sequence is completed within the time length of 5ms, and the timing position is determined after the correlation of the secondary synchronization sequence is completed;
for the cell search except for the first time, only the correlation of the primary synchronization sequence is needed, and the timing position is updated by searching within the time length set near the last determined timing position.
2. The method of claim 1, further comprising:
and in the time period for carrying out the secondary synchronization sequence correlation, utilizing an idle primary synchronization sequence correlation module to carry out the timing calibration of multiple cells.
3. The method according to claim 1 or 2, characterized in that the method further comprises:
and in the time period relevant to the auxiliary synchronization sequence, serially performing coarse frequency offset estimation and outputting a frequency offset result of multiple cells.
4. The method according to claim 1 or 2, characterized in that:
and the independent instantiated cell searching module serially processes the cell searching process of each cell.
5. An FPGA-based cell search device, wherein a cell search module in the device is shared by multiple cells, comprising: the device comprises a main synchronization sequence correlation module, an auxiliary synchronization sequence correlation module and a coarse frequency offset estimation module, wherein:
the primary synchronization sequence correlation module completes primary synchronization sequence correlation within a time length of 5ms when cell search is carried out for the first time, and determines a timing position after secondary synchronization sequence correlation is completed; for the cell search except for the first time, only the correlation of the primary synchronization sequence is needed, the search is carried out within the time length set near the timing position determined last time, and the timing position is updated;
the cell search module is used for changing the search period of the PCI from 10ms to 40 ms.
6. The apparatus of claim 5, wherein:
and the primary synchronization sequence correlation module is used for utilizing idle time to carry out timing calibration of multiple cells in a time period when the secondary synchronization sequence correlation module carries out secondary synchronization sequence correlation.
7. The apparatus of claim 5 or 6, wherein:
the coarse frequency offset estimation module is used for performing coarse frequency offset estimation in series and outputting frequency offset results of multiple cells.
8. The apparatus of claim 5 or 6, wherein:
the cell search module is instantiated independently for serially processing the cell search process of each cell.
9. A non-transitory computer readable storage medium storing instructions which, when executed by a processor, cause the processor to perform the steps of the FPGA-based cell search method of any one of claims 1 to 4.
10. An electronic device comprising the non-volatile computer-readable storage medium of claim 9, and the processor having access to the non-volatile computer-readable storage medium.
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| CN201811228708.7A CN111083716A (en) | 2018-10-22 | 2018-10-22 | Cell searching method and device based on FPGA |
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| CN201811228708.7A CN111083716A (en) | 2018-10-22 | 2018-10-22 | Cell searching method and device based on FPGA |
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| US9609585B1 (en) * | 2016-03-30 | 2017-03-28 | Intel IP Corporation | Devices and method for cell search and detection |
| US20170280374A1 (en) * | 2016-03-24 | 2017-09-28 | Intel IP Corporation | Methods and communication devices for performing cell search and detection |
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Patent Citations (5)
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| CN101330318A (en) * | 2007-06-20 | 2008-12-24 | 中兴通讯股份有限公司 | Method for scrambling and descrambling assistant synchronous channel sequence in a down synchronous system |
| US20110243104A1 (en) * | 2010-04-02 | 2011-10-06 | Francis Swarts | Method and system for tracking timing drift in multiple frequency hypothesis testing |
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Application publication date: 20200428 |