CN111063624B

CN111063624B - Semiconductor test structure, preparation method and semiconductor test method

Info

Publication number: CN111063624B
Application number: CN201911065483.2A
Authority: CN
Inventors: 肖亮
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2019-11-04
Filing date: 2019-11-04
Publication date: 2022-07-26
Anticipated expiration: 2039-11-04
Also published as: CN111063624A

Abstract

The invention provides a semiconductor test structure, a preparation method and a semiconductor test method, wherein the preparation method comprises the following steps: providing a test substrate, forming a test device layer, forming a first interconnection contact part, a second interconnection contact part and at least one metal layer, forming a contact hole and a test hole, forming a through contact part on the inner wall surface of the contact hole, and forming an insulation test part in the test hole, wherein the test substrate is isolated based on the insulation test part, the test substrate is electrically led out through the first interconnection contact part, the metal layer and the second interconnection contact part, so that the test of the isolation structure is realized, the test of the isolation structure can be performed at an early stage, such as the test performed in the WAT stage, and further, the electrical test between the contact columns can be performed based on the scheme of the invention, the VBD test can be performed based on a scheme design, i.e., a test function having both a VBD test function and an isolation structure (e.g., TSI).

Description

Semiconductor test structure, preparation method and semiconductor test method

Technical Field

The invention belongs to the technical field of semiconductor testing, and particularly relates to a semiconductor testing structure, a preparation method of the semiconductor testing structure and a semiconductor testing method.

Background

Reliability assessment is an important part of process development in integrated circuit manufacturing. However, it is difficult to effectively monitor the isolation structure in the device, especially in the early stage, for example, the monitoring of the through isolation structure (TSI) for isolating the Well region (Well) and preventing the leakage current has the above-mentioned problems, and at present, the Well leakage can only be detected by the Sort test and can be used to reversely deduce whether the TSI process is problematic, and it is also possible that the Well leakage caused by the TSI process problem can not be directly distinguished because it is covered by other problems, and it is difficult to effectively monitor whether the TSI is problematic in the early stage.

Therefore, it is necessary to provide a semiconductor test structure, a method for manufacturing the same, and a method for testing a semiconductor device to solve the above-mentioned problems in the prior art.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, the present invention provides a semiconductor test structure, a manufacturing method and a semiconductor test method, which are used to solve the problems that the isolation structure is difficult to be effectively monitored in the prior art.

To achieve the above and other related objects, the present invention provides a method for fabricating a semiconductor test structure, the method comprising the steps of:

providing a test substrate, wherein the test substrate is provided with a first face and a second face which are opposite;

forming a test device layer on the first surface, wherein a first interconnection contact part, a second interconnection contact part and at least one metal layer are formed in the test device layer, one end of the first interconnection contact part is in contact with the test substrate, and the other end of the first interconnection contact part is electrically connected with the second interconnection contact part through the metal layer;

forming a contact hole and a test hole in the test substrate, wherein the contact hole and the test hole both penetrate through the upper surface and the lower surface of the test substrate and have a distance therebetween, and the contact hole exposes the second interconnection contact part and enables the second interconnection contact part to be insulated from the test substrate; and

and forming an isolation layer on the surface of the inner wall of the contact hole, forming a through contact part on at least the inner wall of the isolation layer, and forming an insulation test part in the test hole, wherein the insulation test part isolates the test substrate, and the through contact part is electrically connected with the second interconnection contact part to form a test unit.

Optionally, the method further includes, after forming the test device layer: and forming an insulating medium layer on the second surface of the test substrate, wherein the penetrating contact part also extends through the upper surface and the lower surface of the insulating medium layer.

Optionally, the step of forming the insulating dielectric layer, the contact hole and the test hole includes:

forming an insulating medium material layer on the second surface of the test substrate;

forming a patterned mask layer on the insulating medium material layer;

and etching the insulating medium material layer and the test substrate based on the patterned mask layer to form the insulating medium layer, the contact hole and the test hole.

Optionally, the method further includes, after forming the through contact portion: and forming an electrical leading-out structure electrically connected with the through contact part on the insulating medium layer.

Optionally, the shape of the test hole comprises a ring shape, the ring-shaped test hole is sleeved on the periphery of the contact hole, and the first interconnection contact part is in contact with the test substrate in a ring-shaped area defined by the test hole.

Optionally, the annular region is divided into a body region and a contact via region, and the number of the first interconnect contacts is the same as that of the second interconnect contacts, where the first interconnect contacts are formed in the test device layer corresponding to the body region, and the second interconnect contacts are formed in the test device layer corresponding to the contact via region.

Optionally, the method for manufacturing a semiconductor test structure includes a step of manufacturing at least two test units, wherein the through contacts of different test units are connected to different test voltages for semiconductor testing.

Optionally, the method for manufacturing a semiconductor test structure further includes a step of manufacturing a first metal comb tooth portion and a second metal comb tooth portion, where the first metal comb tooth portion and the second metal comb tooth portion are arranged in an interdigital manner, and the first metal comb tooth portion and the second metal comb tooth portion are electrically connected to the through contact portions of different test units, respectively.

Optionally, the contact hole, the test hole and the well region isolation structure of the device region are formed on the basis of the same process; the insulation test part and the isolation layer are formed based on the same process.

Optionally, the insulation test portion and the isolation layer are formed using an oxidation process.

Optionally, the width of the test hole is less than twice the thickness of the isolation layer.

The invention also provides a semiconductor test structure, which is preferably prepared by the preparation method of the semiconductor test structure provided by the invention, and of course, can also be prepared by other preparation methods, wherein the semiconductor test structure comprises at least one test unit, and the test unit comprises:

the testing device comprises a testing substrate, a first electrode and a second electrode, wherein the testing substrate is provided with a first surface and a second surface which are opposite to each other, a contact hole and a testing hole are formed in the testing substrate, the contact hole and the testing hole penetrate through the upper surface and the lower surface of the testing substrate, and a space is formed between the contact hole and the testing hole;

the test device layer is formed on the first surface, a first interconnection contact part, a second interconnection contact part and at least one metal layer are formed in the test device layer, one end of the first interconnection contact part is in contact with the test substrate, the other end of the first interconnection contact part is electrically connected with the second interconnection contact part through the metal layer, and the second interconnection contact part is exposed in the contact hole phase and is insulated from the test substrate;

the isolating layer is formed on the surface of the inner wall of the contact hole;

the through contact part is filled in the contact hole, and the through contact part is at least formed on the inner wall of the isolation layer and is electrically connected with the second interconnection contact part; and

and the insulation test part is filled in the test hole and isolates the test substrate.

Optionally, the test unit further includes an insulating dielectric layer formed on the second surface of the test substrate, and the through contact portion further extends through upper and lower surfaces of the insulating dielectric layer.

Optionally, an electrical lead-out structure electrically connected to the through contact portion is further formed on the insulating dielectric layer.

Optionally, the semiconductor test structure comprises at least two test units, and the through contacts of different test units are connected with different test voltages to perform semiconductor testing.

Optionally, the semiconductor test structure further includes a first metal comb portion and a second metal comb portion, the first metal comb portion and the second metal comb portion are arranged in an interdigital manner, and the first metal comb portion and the second metal comb portion are electrically connected to the through contact portions of different test units respectively.

The invention also provides a semiconductor device structure, which comprises the semiconductor test structure according to any one of the above aspects, wherein the semiconductor test structure is formed in a cutting path of the semiconductor device structure.

The invention also provides a semiconductor test method, which comprises the following steps:

providing a semiconductor test structure according to any of the above aspects;

and applying a test voltage to the through contact portion to perform an electrical test of the insulation test portion, and applying different test voltages to the through contact portions of different test units to perform an electrical test of the insulation test portion when at least two test units are formed.

As described above, the semiconductor test structure and method of the present invention isolate the test substrate based on the insulation test portion, and electrically extract the test substrate through the first interconnection contact portion, the metal layer, and the second interconnection contact portion, thereby realizing the test of the isolation structure.

Drawings

FIG. 1 is a flow chart illustrating a process for fabricating a semiconductor test structure according to an embodiment of the present invention.

FIG. 2 shows a schematic representation of providing a test substrate in the fabrication of a semiconductor test structure provided for embodiments of the present invention.

FIG. 3 shows a schematic representation of the formation of test device layers in the fabrication of a semiconductor test structure provided for embodiments of the present invention.

FIG. 4 is a schematic representation showing the formation of an insulating dielectric layer in the fabrication of a semiconductor test structure provided in an embodiment of the present invention.

FIG. 5 is a schematic diagram illustrating the formation of test holes and contact holes in the fabrication of a semiconductor test structure according to an embodiment of the present invention.

FIG. 6 is a diagram illustrating the formation of an insulation test portion in the fabrication of a semiconductor test structure according to an embodiment of the present invention.

FIG. 7 is a diagram illustrating the formation of a through contact in the fabrication of a semiconductor test structure provided in accordance with an embodiment of the present invention.

FIG. 8 is a schematic representation of the formation of electrical lead-out structures in the fabrication of semiconductor test structures provided in accordance with an embodiment of the present invention.

Fig. 9 is a schematic structural diagram illustrating an example of a semiconductor test structure according to an embodiment of the present invention.

FIG. 10 illustrates a top view of an example of a semiconductor test structure provided for embodiments of the present invention.

Fig. 11 shows a schematic structural view of an example of a semiconductor test structure provided for a comparative example of the present invention.

Fig. 12 is a schematic structural view showing another example of the semiconductor test structure provided for the comparative example of the present invention.

Fig. 13 shows a top view of an example of a semiconductor test structure provided for a comparative example of the present invention.

FIG. 14 is a flowchart illustrating a semiconductor testing method according to an embodiment of the present invention.

Description of the element reference

101,301 test substrate

101a first side

101b second side

102,302 test device layer

103 first interconnect contact

103a first transition

104,303 second interconnection contact

104a second transition portion

105,304 Metal layer

106,305 insulating medium layer

107 test hole

108 contact hole

109,306 barrier layer

110 insulation test part

111,307 through contact

112,308 electric lead-out structure

201,401 first electrical lead-out structure

202,402 second electrical lead-out structure

203,403 first metal comb tooth part

204,404 second metal comb tooth part

S1-S6 steps

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structure are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.

The first embodiment is as follows:

as shown in fig. 1, the present invention provides a method for fabricating a semiconductor test structure, the method comprising the steps of:

The method for fabricating the semiconductor test structure of the present invention will be described in detail with reference to the accompanying drawings.

As shown in S1 in fig. 1 and fig. 2, a test substrate 101 is provided, the test substrate 101 having a first side 101a and a second side 101b opposite to each other.

Specifically, the test substrate 101 may be a semiconductor material, such as a single crystal silicon substrate, a single crystal germanium substrate, an SOI (silicon on insulator) substrate, or a GOI (germanium on insulator) substrate, and the test substrate 101 may also be an N-type or P-type doped substrate as needed. The skilled person can select suitable substrate materials according to practical requirements, and the substrate materials are not limited herein. In this embodiment, the test substrate 101 is a single crystal silicon wafer. In an example, the test substrate 101 includes a front surface for preparing the test device layer 102 and a back surface for electrical extraction, where the first surface 101a is the front surface and the second surface 101b is the back surface.

As shown in S2 of fig. 1 and fig. 3, a test device layer 102 is formed on the first surface 101a, a first interconnection contact 103, a second interconnection contact 104 and at least one metal layer 105 are formed in the test device layer 102, one end of the first interconnection contact 103 is in contact with the test substrate 101, and the other end is electrically connected to the second interconnection contact 104 through the metal layer 105.

Specifically, a test device layer 102 is formed on the test substrate 101, in an example, the test substrate 101 has a front surface and a back surface opposite to each other, and the test device layer 102 is formed on the front surface of the test substrate 101, that is, the front surface refers to a surface on which a device is formed, that is, device preparation is performed on the front surface of the test substrate 101, and optionally, ion implantation and other operations may be performed on the front surface of the test substrate 101 to form an active region and the like in preparation for forming the test device layer 102 subsequently. In an alternative example, other structures may also be formed in the test device layer 102 to perform semiconductor testing, such as contact pillars ct (contact). In an example, the material of the first interconnect contact 103 and the second interconnect contact 104 are both W, and the material of the metal layer 105 may be Cu, and in an example, a first transition portion 103a and a second transition portion 104a may be further formed, as shown in fig. 3, and the material of both may be the same as the material of the corresponding interconnect contact, for example, the material of both may be W.

Specifically, the first interconnection contact 103 and the second interconnection contact 104 may be contact portions of an interconnection structure, the interconnection structure is used for wiring connection in the test device layer 102, the first interconnection contact 103 and the second interconnection contact 104 may be connection vias ct (contact), the first interconnection contact 103 is in contact with the test substrate 101, and electrical leading-out of the test substrate 101 may be achieved based on the first interconnection contact 103, in this case, in this step, the second interconnection contact 104 may or may not be in contact with the test substrate 101, for example, a gap may be provided between an end surface of the second interconnection contact 104 facing the test substrate 101 and the test substrate 101.

In addition, the metal layer 105 may be a metal wiring layer in a test device, wherein the first interconnection contact 103 and the second interconnection contact 104 may both be connected to the same metal layer 105 to achieve electrical connection therebetween, the first interconnection contact 103 and the second interconnection contact 104 may be connected to different metal layers, the different metal layers 105 are electrically connected through a connection post (e.g., CT) and a conductive structure such as a metal layer to achieve electrical connection therebetween, and the number and the positions of the first interconnection contact 103, the second interconnection contact 104, and the metal layer 105 may be set according to actual requirements. In one example, the first interconnect contact 103 is disposed parallel to the second interconnect contact 104 and perpendicular to a plane of the metal layer 105.

As shown in S3 in fig. 1 and fig. 4-5, a contact hole 108 and a test hole 107 are formed in the test substrate 101, the contact hole 108 and the test hole 107 both penetrate through the upper and lower surfaces of the test substrate 101 with a space therebetween, the contact hole 108 exposes the second interconnection contact 104 and insulates the second interconnection contact 104 from the test substrate 101.

Specifically, the test hole 107 is formed for forming a test structure of an isolation structure subsequently, wherein the second interconnection contact 104 is insulated from the test substrate 101, and the diameter of the contact hole 108 may be larger than the diameter of the second interconnection contact 104, so as to insulate the second interconnection contact 104 from the test substrate 101, where the diameter may be understood as the size of the largest contact where the contact hole 108 contacts the second interconnection structure, so as to achieve the effect of insulation and no contact.

As an example, after forming the test device layer 102, the method further includes the steps of: an insulating dielectric layer 106 is formed on the second surface 101b of the test substrate 101, and the through contact 111 further extends through the upper and lower surfaces of the insulating dielectric layer 106.

As an example, the step of forming the insulating medium layer 106, the contact hole 108, and the test hole 107 includes:

forming an insulating medium material layer on the surface of the second surface 101b of the test substrate 101;

forming a graphical mask layer on the insulating medium material layer;

and etching the insulating medium material layer and the test substrate 101 based on the patterned mask layer to form the insulating medium layer 106, the contact hole 108 and the test hole 107.

As an example, before forming the insulating dielectric material layer, a step of thinning a side of the test substrate 101 away from the test device layer 102 is further included.

Specifically, in an example, the method further includes a step of forming the insulating medium layer 106, where the test device layer 102 is formed on the front surface of the test substrate 101, and the insulating medium layer 106 is formed on the back surface of the test substrate 101. The contact holes 108 are integrally formed at corresponding positions above and below the insulating dielectric layer 106 and the test substrate 101, and simultaneously penetrate through the upper and lower surfaces of the insulating dielectric layer 106 and the upper and lower surfaces of the test substrate 101.

In an example of forming the insulating dielectric layer 106, the insulating dielectric material layer may be formed through a chemical vapor deposition process or the like, the insulating dielectric material layer is used for protecting the test substrate 101 on one hand, and is used as an interlayer dielectric layer on the top of the test substrate 101 on the other hand, and subsequently, a structure such as an interconnection line may be formed on the surface of the insulating dielectric material layer. The material of the insulating dielectric material layer may be silicon oxide, silicon nitride, silicon oxynitride or other insulating dielectric materials commonly used in semiconductor processes. Then, the insulating dielectric material layer and the test substrate 101 are etched, in an example, a photoresist layer may be formed on the insulating dielectric material layer, and patterned by photolithography to form the patterned mask layer, and then the insulating dielectric material layer and the test substrate 101 are sequentially etched using the patterned mask layer as a mask to form a through hole penetrating through the insulating dielectric material layer and the test substrate 101, that is, the Contact hole 108, and the insulating dielectric layer 106 is formed at the same time, where the Contact hole 108 may be a tsc (through Si Contact), which is a Contact penetrating from the back after the wafer is thinned, where the Contact hole 108 exposes the interconnect structure, in an example, the Contact hole 108 exposes a Contact portion of the interconnect structure, and the Contact hole 108 exposes the second interconnect Contact 104, in a specific embodiment, the contact part surface is covered with an adhesion layer, such as a TiN layer or a TaN layer, and the like, and is easily silicided in a chemical vapor deposition or other high-temperature process to form titanium silicide or tantalum silicide and the like, and the resistance is high. In order to reduce the contact resistance between the contact portion and the contact portion formed later, the metal silicide layer on the surface of the contact portion may be further etched and removed after the contact portion is exposed during the formation of the contact hole 108.

In an optional example, after the test device layer 102 is formed on the front surface of the test substrate 101 and before the insulating medium layer 106 is formed, the back surface of the test substrate 101 is thinned, a chemical mechanical polishing process may be adopted to thin the back surface of the test substrate 101, so as to reduce the thickness of the test substrate 101, thereby reducing the etching depth of the through hole penetrating through the test substrate 101 in the subsequent formation process.

As shown in S4 of fig. 1 and fig. 6 to 8, an isolation layer 109 is formed on the inner wall surface of the contact hole 108, a through contact 111 is formed at least on the inner wall of the isolation layer 109, and an insulation test portion is formed in the test hole 107, wherein the insulation test portion isolates the test substrate 101, and the through contact 111 is electrically connected to the second interconnection contact 104 to form a test cell.

As an example, the step of forming the through contact 111 further includes: an electrical lead-out structure 112 electrically connected to the through contact 111 is formed on the insulating dielectric layer 106. The electrical lead-out structure 112 can realize electrical lead-out of the through contact portion 111, wherein the electrical lead-out structure 112 may include a pad and a lead electrically connected to the pad, or a directly fabricated pad, the layout of the electrical lead-out structure 112 may be selected according to actual requirements, and in an example, the material of the electrical lead-out structure 112 may be aluminum.

Specifically, this step is to prepare a test cell test structure, form the insulation test portion 110 in the test hole 107 to achieve insulation between the test substrates 101, isolate the test substrate 101 into at least two parts insulated from each other, and form an Isolation structure in the test substrate 101, so that a test of the Isolation structure based on the insulation test portion 110 can be performed, that is, different voltages are applied to the test substrates 101 on both sides of the insulation test portion 110, respectively, to perform a test of the Isolation structure, for example, a test of an insulation Isolation structure (TSI, Through Si Isolation) that isolates a well region in a semiconductor device structure region can be performed based on the insulation test portion 110, the present invention forms a Through contact portion 111 in the contact hole 108 to be electrically connected to the second interconnection contact portion 104, so that the Through contact portion 111 can pass Through the second interconnection contact portion 104, the first interconnection contact portion, the second interconnection contact portion 104, and the second interconnection portion, The electrical connection between the metal layer 105 and the first interconnection contact 103 in contact with the test substrate 101 leads out the test substrate 101, so that a voltage can be applied at one end of the through contact 111 for testing the insulation test part in the test substrate 101, leading out one end of both sides of the insulation test part 110 is provided, and an effective test of an isolation structure is achieved, and further, based on the above-mentioned scheme of the present invention, a test voltage is applied at one end of the through contact 111, a voltage is applied at one end of the first interconnection contact 103, and an electrical test between the first interconnection contact 103 and the second interconnection contact 104 can be performed to perform a test of two interconnection parts in a semiconductor device structure, such as an electrical test between two ct (contact) contact pillars, and further, the test unit of the present invention can be prepared in a scribe line, namely, the test TSI structure of one WAT is independently prepared, the current process flow can be compatible, the test is carried out at the WAT (wafer Acceptance test) stage, if the isolation structure has problems, the problem caused by the well leakage test at the sort test stage can be effectively solved without waiting for the test at the sort test stage, for example, in the main chip region, TSI (Through Si Isolation, used to isolate Well leakage) can only detect Well leakage until the start test stage, and therefore whether there is a problem in the TSI process can be deduced, and the problem of the TSI process can not be solved, and the problem that whether the well region leakage is caused by the TSI process problem can not be directly distinguished because the leakage is covered by other problems.

As shown in fig. 9 and 10, the method for fabricating the semiconductor test structure includes, as an example, a step of fabricating at least two test units, wherein the through contacts 111 of different test units are connected to different test voltages to perform a semiconductor test.

Specifically, as shown in fig. 9 and 10, the top view of fig. 9 can refer to fig. 10, which includes at least two test units, fig. 9 shows two test units as an example, in the test structure, different voltage applications are performed on the through contacts 111 of the two test units, that is, two portions of the test substrate 101, which isolate the insulation test portion 110, are electrically extracted through the respective first interconnection contacts 103 of the test units, so that whether the insulation test portion between the two portions of the test substrate 101 has a problem or not can be measured, and whether the isolation structure has a problem such as leakage or not can be measured, in one example, a voltage can be gradually applied to the two through extraction portions 111, and the voltage is increased by 2V (step is 2V) each time to 50V, and if the current is greater than 10E in the process ^-7 A is considered leakage, and in other examples, it may be empirically determined that no current indicates no problem and current indicates leakage. Of course, when there are a plurality of the test units, two of the test units may be used based on different test voltagesSimilar to the testing of isolation structures.

As shown in fig. 10, as an example, the method for fabricating the semiconductor test structure further includes a step of fabricating a first metal comb portion 203 and a second metal comb portion 204, wherein the first metal comb portion 203 and the second metal comb portion 204 are disposed in an interdigital manner, and the first metal comb portion 203 and the second metal comb portion 204 are electrically connected to the through

contacts

201 and 202 of different test units, respectively.

Specifically, as shown in fig. 10, when there are at least two test units, the method further includes a step of forming two test units as an example, where the two test units form an interdigital test electrode, the first metal comb tooth portion 203 is electrically connected to the through contact portion 111 of one test unit, and the second metal comb tooth portion is electrically connected to the through contact portion 111 of the other test unit, so that different test voltages can be applied to the through contact portions 111 of the two test units to perform a VBD test, and a function of the breakdown voltage test is realized, for example, electrical leading-out is performed through the electrical leading-out

structures

201 and 202 of different test units, in an example, the structure for performing the VBD test may be an original device test structure, and by the design of the present invention, the VBD test structure (Padout 3K level VBD, e.g., VBD between TSCs) can be monitored, increasing the ability to monitor the TSI structure while preserving the original functionality.

As an example, the shape of the test hole 107 includes a ring shape, the ring-shaped test hole 107 is sleeved on the periphery of the contact hole 108, and the first interconnection contact portion 103 is in contact with the test substrate 101 in a ring-shaped area defined by the test hole 107.

As an example, the annular region is divided into adjacent body regions 110a and contact via regions 110b, and referring to fig. 10, the number of the first interconnection contacts 103 is the same as that of the second interconnection contacts 104, wherein the first interconnection contacts 103 are formed in the test device layer 102 corresponding to the body regions, and the second interconnection contacts 104 are formed in the test device layer 102 corresponding to the contact via regions.

Specifically, in an example, the shape of the test hole 107 is configured to be an annular shape, which may be a circular ring, a square ring, a polygonal ring, an irregular ring, and so on, and the insulation test portion 110 formed subsequently is also configured to be an annular structure, of course, in other examples, the test hole 107 may also be a bar-shaped structure, and further may be configured to be a plurality of bar-shaped structures, and may also be configured to be other structures for realizing isolation of the test substrate 101, according to actual settings, in this example, the shape of the test hole 107 is configured to be an annular shape, further, the contact hole 108 is configured within an area defined by the annular shape and has a distance from an inner edge of the annular test hole 107, and the annular test hole 107 is configured to facilitate the provision of two isolated portions of the test substrate 101 at a desired position, thereby facilitating the preparation of subsequent test structure portions, the lead-out of the wiring is facilitated, and at this time, the through contact 111 formed subsequently is also arranged in the annular region defined by the insulation test portion 110, and at the same time, the first interconnection contact 103 in the test device layer 102 is in contact with the test substrate 101 in the annular region defined by the test substrate 101, so as to achieve the electrical connection with the test substrate 101.

Further, in an optional example, the annular region is divided into adjacent body regions 110a and contact via regions 110b, as shown in fig. 10, for example, the body regions 110a and the contact via regions 110b are arranged in left and right, in an example, the body regions and the contact via regions have the same area, the test substrate 101 of the body regions is used for realizing electrical connection with the first interconnection contacts 103, the test substrate 101 of the contact via regions is used for realizing electrical leading out of the body regions based on the through contacts 111, that is, the first interconnection contacts 103 correspond to the body regions, the second interconnection contacts 104 and the through contacts 111 correspond to the contact via regions, the contact holes 108 are arranged in the contact via regions, in an optional example, the number of the first interconnection contacts 103 is the same as that of the second interconnection contacts 104, of course, in other examples, the number of the first interconnection contacts 103 is at least one, and the number of the second interconnection contacts 104 is at least one, so as to realize the electrical leading-out of the test substrate 101.

As an example, the contact holes 108, the test holes 107 and a well region isolation structure of the device region (e.g., TSI for well region leakage isolation of the device region) are formed based on the same process.

As an example, the insulation test portion is formed based on the same process as the isolation layer 109.

As an example, the insulation test part 110 and the isolation layer 109 are formed using an oxidation process.

As an example, the width of the test hole 107 is less than twice the thickness of the isolation layer 109.

Specifically, in an example, the contact hole 108, the test hole 107, and a well isolation structure of a device region are formed based on the same process, the well isolation structure may refer to an isolation through hole of a well in an isolation device region, and the three are prepared based on the same process, so that a test on the well isolation structure can be implemented.

In addition, in an example, the insulation test portion 110 and the isolation layer 109 are formed based on the same process, in an optional example, the two materials are the same and may be silicon oxide, and optionally, the two materials are formed by a dry oxidation process, such as an ISSG (in situ steam generation) process, so that a required material layer may be directly formed, an etching process is not required, and an influence on a device caused by movement of residual charges in a conductive structure in the etching process may be effectively alleviated, and in an optional example, the width of the test hole 107 is less than twice the thickness of the isolation layer 109, so that effective filling of the insulation test portion 110 may be facilitated, oxidation process time and raw materials are not wasted, and operation efficiency is improved, and the width of the test hole 107 is between 120 and 200nm, and may be selected as 160 nm. The width of the contact hole 108 is between 700-750nm, and can be selected as 720nm, so as to facilitate the preparation of the semiconductor test structure.

The second embodiment:

as shown in fig. 8 to 10 and referring to fig. 1 to 7, the present invention further provides a semiconductor test structure, which is preferably prepared by using the preparation method of the semiconductor test structure according to the first embodiment of the present invention, but may also be prepared by using other preparation methods, wherein the semiconductor test structure includes at least one test unit, and the test unit includes:

the testing device comprises a testing substrate 101 with a first face 101a and a second face 101b which are opposite, wherein a contact hole 108 and a testing hole 107 are formed in the testing substrate 101, and the contact hole 108 and the testing hole 107 penetrate through the upper surface and the lower surface of the testing substrate 101 with a space therebetween;

a test device layer 102 formed on the first surface 101a, wherein a first interconnection contact 103, a second interconnection contact 104 and at least one metal layer 105 are formed in the test device layer 102, one end of the first interconnection contact 103 is in contact with the test substrate 101, the other end of the first interconnection contact is electrically connected with the second interconnection contact 104 through the metal layer 105, and the second interconnection contact 104 is exposed in the contact hole 108 and insulated from the test substrate 101;

an isolation layer 109 formed on an inner wall surface of the contact hole 108;

a through contact 111 filled in the contact hole 108, the through contact 111 being formed at least on an inner wall of the isolation layer 109 and electrically connected to the second interconnection contact 104; and

and an insulation test portion filled in the test hole 107, the insulation test portion isolating the test substrate 101.

Specifically, the test substrate 101 may be a semiconductor material, such as a single crystal silicon substrate, a single crystal germanium substrate, an SOI (silicon on insulator) substrate, a GOI (germanium on insulator) substrate, or the like, and the test substrate 101 may also be an N-type or P-type doped substrate as needed. The skilled person can select suitable substrate materials according to practical requirements, and the substrate materials are not limited herein. In this embodiment, the test substrate 101 is a single crystal silicon wafer. In an example, the test substrate 101 includes a front surface for preparing the test device layer 102 and a back surface for electrical extraction, where the first surface 101a is the front surface and the second surface 101b is the back surface.

In an example, the test substrate 101 has opposite front and back surfaces, the test device layer 102 is formed on the front surface of the test substrate 101, that is, the front surface refers to a surface on which devices are formed, that is, device preparation is performed on the front surface of the test substrate 101, and optionally, ion implantation or the like may be performed on the front surface of the test substrate 101 to form an active region or the like in preparation for forming the test device layer 102 subsequently. In an alternative example, other structures may also be formed in the test device layer 102 to perform semiconductor testing, such as contact pillars ct (contact). In an example, the material of the first interconnection contact 103 and the second interconnection contact 104 is W, the material of the metal layer 105 may be Cu, and in an example, a first transition portion 103a and a second transition portion 104a may be formed, as shown in fig. 3, and may be the same as the corresponding interconnection contact, for example, W.

In addition, the metal layer 105 may be a metal wiring layer in a test device, the first interconnection contact 103 and the second interconnection contact 104 may be connected to the same metal layer 105 to achieve electrical connection therebetween, the first interconnection contact 103 and the second interconnection contact 104 may be connected to different metal layers 105, the different metal layers 105 are electrically connected through conductive structures such as a connection stud and a metal layer 105 to achieve electrical connection between the first contact interconnection and the second interconnection contact 104, and the number and the positions of the first interconnection contact 103, the second interconnection contact 104, and the metal layers 105 may be set according to actual requirements. In an alternative example, the first interconnection contact 103 is arranged parallel to the second interconnection contact 104 and perpendicular to the plane of the metal layer 105.

As an example, the test unit further includes an insulating dielectric layer 106 formed on the second face 101b of the test substrate 101, and the through contact 111 further extends through upper and lower surfaces of the insulating dielectric layer 106.

As an example, an electrical lead-out structure 112 electrically connected to the through contact portion 111 is further formed on the insulating dielectric layer 106, and the electrical lead-out structure 112 may implement electrical lead-out of the through contact portion 111, where the electrical lead-out structure 112 may include a pad and a lead electrically connected to the pad, or may be a directly fabricated pad, the layout of the electrical lead-out structure 112 may be selected according to practical requirements, and in an example, the material of the electrical lead-out structure 112 may be aluminum.

Specifically, in an example, the test device layer 102 is formed on the front surface of the test substrate 101, and the insulating medium layer 106 is formed on the back surface of the test substrate 101. The contact holes 108 are integrally formed at corresponding positions above and below the insulating dielectric layer 106 and the test substrate 101, and simultaneously penetrate through the upper and lower surfaces of the insulating dielectric layer 106 and the upper and lower surfaces of the test substrate 101.

Specifically, this step is to prepare a test cell test structure, form the insulation test portion 110 in the test hole 107 to achieve insulation between the test substrates 101, isolate the test substrate 101 into at least two parts insulated from each other, and form an Isolation structure in the test substrate 101, so that a test of the Isolation structure based on the insulation test portion 110 can be performed, that is, different voltages are applied to the test substrates 101 on both sides of the insulation test portion 110, respectively, to perform a test of the Isolation structure, for example, a test of an insulation Isolation structure (TSI, Through Si Isolation) that isolates a well region in a semiconductor device structure region can be performed based on the insulation test portion 110, the present invention forms a Through contact portion 111 in the contact hole 108 to be electrically connected to the second interconnection contact portion 104, so that the Through contact portion 111 can pass Through the second interconnection contact portion 104, the first interconnection contact portion, the second interconnection contact portion 104, and the second interconnection portion, The electrical connection between the metal layer 105 and the first interconnection contact 103 in contact with the test substrate 101 leads out the test substrate 101, so that a voltage can be applied to one end of the through contact 111 to test the insulation test portion in the test substrate 101, thereby realizing an effective test of the isolation structure. In addition, according to the above-mentioned aspect of the present invention, a test voltage is applied to one end of the through contact 111, and a voltage is applied to one end of the first interconnection contact 103, and an electrical test between the first interconnection contact 103 and the second interconnection contact 104 may be performed to perform a test of two interconnection parts in a semiconductor device structure, for example, a test between two ct (contact) contacts. In addition, the test unit of the present invention can be prepared in the scribe line, and can test the scribe line at the WAT stage, and if the Isolation structure has a problem, it is not necessary to wait for the Sort test stage to test the Isolation structure, and it can also effectively solve the problem caused by the Well leakage test at the Sort test stage, for example, the Well leakage can only be detected at the Sort test stage, and it is determined whether the TSI (Through Si Isolation) process has a problem, and it is also possible that the TSI process cannot be directly distinguished from the Well leakage caused by the TSI process problem because the TSI process is covered by other problems.

As an example, the annular region is divided into adjacent body regions 110a and contact penetrating regions 110b, and referring to fig. 10, the number of the first interconnection contacts 103 is the same as that of the second interconnection contacts 104, wherein the first interconnection contacts 103 are formed in the test device layer 102 corresponding to the body regions, and the second interconnection contacts 104 are formed in the test device layer 102 corresponding to the contact penetrating regions.

Specifically, in an example, the shape of the test hole 107 is configured to be an annular shape, which may be a circular ring, a square ring, a polygonal ring, an irregular ring, and so on, and the insulation test portion 110 formed subsequently is also configured to be an annular structure, of course, in other examples, the test hole 107 may also be a bar-shaped structure, and further may be configured to be a plurality of bar-shaped structures, and may also be configured to be other structures for realizing isolation of the test substrate 101, according to actual settings, in this example, the shape of the test hole 107 is configured to be an annular shape, further, the contact hole 108 is configured within an area defined by the annular shape and has a distance from an inner edge of the annular test hole 107, and the annular test hole 107 is configured to facilitate the provision of two isolated portions of the test substrate 101 at a desired position, thereby facilitating the preparation of subsequent test structure portions, the lead-out of the wiring is facilitated, and at this time, the subsequently formed through contact 111 is also arranged in the annular region defined by the insulation test portion 110, and at the same time, the first interconnection contact 103 in the test device layer 102 is in contact with the test substrate 101 defined in the annular region, so as to realize the electrical connection with the test substrate 101.

Further, in an alternative example, the annular region is divided into adjacent body regions and contact via regions, for example, the body regions and the contact via regions are arranged left and right, in an example, the body regions and the contact via regions have equal areas, the test substrate 101 of the body regions is used for realizing electrical connection with the first interconnection contacts 103, the test substrate 101 of the contact via regions is used for realizing electrical leading-out of the body regions based on the through contacts 111, that is, the first interconnection contacts 103 correspond to the body regions, the second interconnection contacts 104 and the through contacts 111 correspond to the contact via regions, the contact holes 108 are arranged in the contact via regions, and in an alternative example, the number of the first interconnection contacts 103 is equal to that of the second interconnection contacts 104, of course, in other examples, the number of the first interconnection contacts 103 is at least one, and the number of the second interconnection contacts 104 is at least one, so as to achieve electrical extraction of the test substrate 101.

As an example, the semiconductor test structure includes at least two of the test units, and the through contacts 111 of different ones of the test units are connected to different test voltages to perform a semiconductor test.

Specifically, as shown in fig. 9 and 10, the top view of fig. 9 can refer to fig. 10, in this example, the test structure includes at least two test units, and fig. 9 shows two test units as an example, in this test structure, different voltage applications are performed on the through contacts 111 of the two test units, that is, two portions of the test substrate 101, which isolate the insulation test portion 110, are electrically led out through the metal layer 105 and the first interconnection contact 103 of each test unit, so that whether a problem occurs in the insulation test portion between the two portions of the substrate can be measured, and whether a problem occurs in the isolation structure can be measured. Of course, when a plurality of the test units exist, two of the test units can be used for testing similar isolation structures based on different test voltages.

As an example, the semiconductor test structure further includes a first metal comb portion 203 and a second metal comb portion 204, the first metal comb portion 203 and the second metal comb portion 204 are disposed in an interdigital shape, and the first metal comb portion and the second metal comb portion are electrically connected to the through

contact portions

201 and 202 of different test units, respectively.

Specifically, as shown in fig. 10, when there are at least two test units, the method further includes a step of forming two metal comb teeth portions, which form interdigital test electrodes, where the first metal comb tooth portion is electrically connected to the through contact portion 111 of one test unit, and the second metal comb tooth portion is electrically connected to the through contact portion 111 of another test unit, so that different test voltages can be applied to the through contact portions 111 of the two test units, respectively, to perform a VBD test, and a function of a breakdown voltage test is realized, for example, electrical leading-out is performed through the electrical leading-out

structures

201 and 202 of different test units, in one example, the structure for performing the VBD test may be an original device test structure, and by the design of the present invention, the VBD test structure (Padout 3K level VBD, e.g., VBD between TSCs) can be monitored, increasing the ability to monitor the TSI structure while preserving the original functionality.

In an alternative example, the width of the test hole 107 is less than twice the thickness of the isolation layer 109, so as to facilitate effective filling of the insulation test portion 110, avoid waste of oxidation process time and raw materials, and improve operation efficiency, and the width of the test hole 107 is between 120 nm and 200nm, and may be selected as 160 nm. The width of the contact hole 108 is between 700-750nm, and can be selected as 720nm, so as to facilitate the preparation of the semiconductor test structure.

Specifically, the present invention further provides a semiconductor device structure, wherein the semiconductor device structure may further include a memory structure formed on the test substrate 101, that is, the memory structure and the test structure are integrated on the test substrate 101, wherein the memory structure includes a core region and a step region disposed around the core region, the step region is formed by alternately stacking isolation layers and control gate layers, and a trench pillar structure penetrating through the memory structure is formed in the core region. The interconnect structure within the device fabric layer includes vertically disposed contacts and laterally disposed interconnect lines. Optionally, the vertically arranged contact includes a contact portion for electrically connecting with the semiconductor substrate, and the contact portion includes a word line contact portion arranged perpendicular to the surface direction of the semiconductor substrate and connected with the step region gate layer, a channel contact portion connected with the top of the channel pillar structure, a common source contact portion penetrating through the storage structure, and the like; the laterally arranged interconnection lines include word lines, source lines, bit lines, and the like arranged in parallel to the surface direction of the semiconductor substrate and connected to vertically arranged contacts. The contact part is matched with the interconnecting wire to lead out the structure electrically connected with the outside in the device structural layer to the bottom to be formed on the surface of the semiconductor substrate, in an example 3D NAND flash memory structure, including a memory array structure and a CMOS circuit structure located over the memory array structure, the memory array junctions and CMOS circuit structures are typically formed on two different wafers, then bonding the wafer formed with CMOS circuit and the wafer with memory array structure by bonding, then thinning the back of the wafer with the memory array structure, forming a through wafer contact part from the back of the wafer, connecting the CMOS circuit with the memory array structure, in this example, the test structure and the memory structure are integrated on the same wafer, bonded to a CMOS wafer, the test structure can realize the test of the well region isolation structure on the wafer of the memory structure.

Example three:

as shown in fig. 14, the present invention also provides a semiconductor test method, which comprises the steps of:

providing the semiconductor test structure of any of embodiments two;

a test voltage is applied to the through contact 111 to perform an electrical test of the insulation test part 110, and when at least two test units are formed, different test voltages are applied to the through contacts of different test units to perform an electrical test of the insulation test part 110.

Specifically, the present invention provides a semiconductor test method, first providing the semiconductor test structure as described in any one of the second embodiments, based on the test unit in the test structure, the insulation test portion 110 achieves insulation between the test substrates 101, and an Isolation structure in the test substrate 101 is formed, so that a test of the Isolation structure can be performed based on the insulation test portion 110, that is, different voltages are respectively applied to the test substrates 101 on both sides of the insulation test portion 110 to perform a test of the Isolation structure, for example, a test of an insulation Isolation structure (TSI, Through Si Isolation) that isolates a well region in a semiconductor device structure region can be performed based on the insulation test portion 110, wherein the present invention forms a Through contact portion 111 in the contact hole 108, which is electrically connected to the second interconnection contact portion 104, so that the Through contact portion 111 can pass Through the second interconnection contact portion 104, The electrical connection between the metal layer 105 and the first interconnection contact 103 in contact with the test substrate 101 leads out the test substrate 101, so that a voltage can be applied at one end of the through contact 111 for testing the insulation test portion in the test substrate 101, leading out one end of both sides of the insulation test portion 110 is provided, and an effective test of an isolation structure is achieved, and further, based on the above-mentioned scheme of the present invention, a test voltage is applied at one end of the through contact 111, a voltage is applied at one end of the first interconnection contact 103, and an electrical test between the first interconnection contact 103 and the second interconnection contact 104 can be performed to perform a test of two interconnection portions in a semiconductor device structure, such as a test between two ct (contact) contacts, and further, the test unit of the present invention can be prepared in a scribe line, the method can be used for testing the Isolation structure in the WAT stage, can find the Isolation structure in the early stage if the Isolation structure has problems, does not need to wait for the test in the Sort test stage, and can also effectively solve the problems caused by Well leakage test in the Well region in the Sort test stage.

When there are at least two test units, different voltages are applied to the through contacts 111 of the two test units, as shown in fig. 9 and 10, that is, the two test substrates 101 separating the insulation test part 110 are electrically led out through the respective first interconnection contacts 103 of the test units, so that it can be determined whether there is a problem in the insulation test part between the two test substrates 101, and whether there is a problem in the isolation structure. Of course, when a plurality of the test units exist, two of the test units can be used for testing similar isolation structures based on different test voltages.

Specifically, as shown in fig. 10, when the number of the test units is at least two, two test units are taken as an example in the figure, and when the test structure further includes the first metal comb portion and the second metal comb portion, which form the interdigital test electrode, the first metal comb portion is electrically connected to the through contact portion 111 of one test unit, and the second metal comb portion is electrically connected to the through contact portion 111 of the other test unit, so that different test voltages can be applied to the through contact portions 111 of the two test units respectively to perform the VBD test, and the function of the breakdown voltage test is realized, for example, the VBD is electrically led out through the electrical lead-out structure 112, in one example, the structure for performing the VBD test may be an original device test structure, and the VBD test structure (Padout 3K level d, for example, VBD between TSCs) is improved through the design of the present invention, the monitoring capability of the TSI structure is increased while the original function is kept.

Comparative example:

as shown in fig. 11-13, the present invention further provides a comparative example, in which the test structure of the comparative example includes at least one test unit, the test unit includes a test substrate 301, a test device layer 302, a second interconnect contact 303, a metal layer 304, an insulating dielectric layer 305, an isolation layer 306, a through contact 307, and an electrical lead-out structure 308, as shown in fig. 12 and 13, the comparative example also includes two examples of test units, including a first electrical lead-out structure 401, a second electrical lead-out structure 402, a first metal comb portion 403, and a second metal comb portion 404, in the comparative example, the description of the relevant structures in the comparative example can refer to the description of embodiments 1 to 3 of the present invention, the structure of the comparative example can be a VBD test structure in the existing device structure, a VBD test can be performed in the WAT test stage, that is a Padout 3K level VBD structure, the testing structure in embodiments 1 to 3 of the present invention improves the structure by adding a circle of TSI structure around the Pad of the existing PADOUT VBD structure and transforming the Pad into a Half Pad, so as to increase the monitoring capability of the TSI structure while retaining the original function, construct a structure capable of monitoring TSI on the WAT testing TSK, and monitor whether the TSI process is in a problem or not in an early stage.

In summary, the semiconductor test structure and method of the present invention isolate the test substrate based on the insulation test portion, and electrically extract the test substrate through the first interconnection contact portion, the metal layer, and the second interconnection contact portion, thereby implementing the test of the isolation structure. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Those skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims

1. A method for preparing a semiconductor test structure is characterized by comprising the following steps:

providing a test substrate, wherein the test substrate is provided with a first surface and a second surface which are opposite;

forming an isolation layer on the inner wall surface of the contact hole, forming a through contact part on at least the inner wall of the isolation layer, and forming an insulation test part penetrating through the test substrate in the test hole, wherein the insulation test part isolates the test substrate to divide the test substrate into at least two insulated parts, and the through contact part is electrically connected with the second interconnection contact part to form a test unit;

the contact hole, the test hole and the well region isolation structure of the device region are formed on the basis of the same process, so that the well region isolation structure is monitored through testing of the test unit.

2. The method of fabricating a semiconductor test structure according to claim 1, further comprising, after forming said test device layer, the steps of: and forming an insulating medium layer on the second surface of the test substrate, wherein the penetrating contact part also extends through the upper surface and the lower surface of the insulating medium layer.

3. The method as claimed in claim 2, wherein the step of forming the insulating dielectric layer, the contact hole and the test hole comprises:

forming a graphical mask layer on the insulating medium material layer;

4. The method of claim 2, further comprising the step of, after forming the through contact: and forming an electrical leading-out structure electrically connected with the through contact part on the insulating medium layer.

5. The method as claimed in claim 1, wherein the shape of the test hole comprises a ring shape, the ring-shaped test hole is sleeved on the periphery of the contact hole, and the first interconnection contact portion is in contact with the test substrate in a ring-shaped area defined by the test hole.

6. The method as claimed in claim 5, wherein the ring region is divided into adjacent body regions and contact via regions, and the number of the first interconnect contacts and the number of the second interconnect contacts are the same, wherein the first interconnect contacts are formed in the test device layer corresponding to the body regions and the second interconnect contacts are formed in the test device layer corresponding to the contact via regions.

7. The method of claim 1, comprising the step of preparing at least two test cells, wherein the through contacts of different test cells are connected to different test voltages for semiconductor testing.

8. The method of claim 7, further comprising a step of preparing a first metal comb portion and a second metal comb portion, wherein the first metal comb portion and the second metal comb portion are disposed in an interdigital manner, and the first metal comb portion and the second metal comb portion are electrically connected to the through contact portions of different test units, respectively.

9. The method for manufacturing a semiconductor test structure according to any one of claims 1 to 8, wherein the contact holes, the test holes and the well region isolation structures of the device region are formed on the basis of the same process; the insulation test part and the isolation layer are formed based on the same process.

10. The method of claim 9, wherein the insulation test portion and the isolation layer are formed by an oxidation process.

11. The method of claim 9, wherein the width of the test hole is less than twice the thickness of the isolation layer.

12. A semiconductor test structure, comprising at least one test cell, the test cell comprising:

a through contact part filled in the contact hole, the through contact part being formed at least on the inner wall of the isolation layer and electrically connected with the second interconnection contact part; and

the insulation testing part is filled in the testing hole and penetrates through the testing substrate, and the insulation testing part isolates the testing substrate so as to divide the testing substrate into at least two parts which are insulated mutually;

the contact hole, the test hole and the well region isolation structure of the device region are formed based on the same process, so that the well region isolation structure is monitored through testing the test unit.

13. The semiconductor test structure of claim 12, wherein the test unit further comprises an insulating dielectric layer formed on the second side of the test substrate, and the through contact further extends through upper and lower surfaces of the insulating dielectric layer.

14. The semiconductor test structure of claim 13, wherein an electrical lead-out structure electrically connected to the through contact is further formed on the insulating dielectric layer.

15. The semiconductor test structure of claim 12, wherein the test hole has a shape comprising a ring, the ring-shaped test hole is disposed around a periphery of the contact hole, and the first interconnect contact is in contact with the test substrate within a ring-shaped area defined by the test hole.

16. The semiconductor test structure of claim 15, wherein the annular region is divided into adjacent body regions and contact via regions, and the number of the first interconnect contacts and the number of the second interconnect contacts are the same, wherein the first interconnect contacts are formed in the test device layer corresponding to the body regions and the second interconnect contacts are formed in the test device layer corresponding to the contact via regions.

17. The semiconductor test structure of claim 12, wherein the semiconductor test structure comprises at least two of the test cells, the through contacts of different ones of the test cells being connected to different test voltages for semiconductor testing.

18. The semiconductor test structure of claim 17, further comprising a first metal comb portion and a second metal comb portion, wherein the first metal comb portion and the second metal comb portion are disposed in an interdigital manner, and the first metal comb portion and the second metal comb portion are electrically connected to the through contact portions of different test units, respectively.

19. The semiconductor test structure of any of claims 12-18, wherein the width of the test hole is less than twice the thickness of the isolation layer.

20. A semiconductor device structure, characterized in that it comprises a semiconductor test structure according to any one of claims 12-19, which is formed in a dicing street of the semiconductor device structure.

21. A semiconductor test method, characterized in that the test method comprises the steps of:

providing a semiconductor test structure according to any of claims 12-19;