CN111063282A - Test circuit of display panel and OLED display - Google Patents
Test circuit of display panel and OLED display Download PDFInfo
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- CN111063282A CN111063282A CN201911177923.3A CN201911177923A CN111063282A CN 111063282 A CN111063282 A CN 111063282A CN 201911177923 A CN201911177923 A CN 201911177923A CN 111063282 A CN111063282 A CN 111063282A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The application provides a test circuit of display panel, test circuit includes: three input data signal lines including an R data signal line, a G data signal line, and a B data signal line; the three control voltage signal lines comprise an R control voltage signal line, a G control voltage signal line and a B control voltage signal line; the testing unit comprises six gating modules, the output ends of the six gating modules are respectively connected with 6 columns of sub-pixels of the pixel structure, and the output end of each gating module is respectively connected with each sub-pixel in one column of sub-pixels; the input end of each gating module is respectively connected with one data signal line or two data signal lines corresponding to the sub-pixels of the corresponding column; and the control end of each gating module is respectively connected with one control voltage signal line or two control voltage signal lines corresponding to the sub-pixels of the corresponding row.
Description
Technical Field
The application relates to the technical field of display, in particular to a test circuit of a display panel and an OLED display.
Background
The OLED has the advantages of wide color gamut, high contrast, energy conservation, foldability and strong competitiveness in new generation displays. The AMOLED technology is one of the major development directions of flexible display. The current OLED light emitting area design is divided into: real RGB/dummy pixel design. The dummy pixel design is suitable for a display screen with high pixel density, and is usually applied to the design of a mobile phone panel. The dummy pixel design is usually applied to large-screen designs such as Pad, and the requirement on pixel density is slightly lower. The display effect of the dummy pixel design is better, however, the arrangement of the light-emitting device is compact, and the FMM (flexible printed Circuit) raster has higher requirements. Therefore, the prior art has drawbacks and needs to be improved.
Disclosure of Invention
The utility model aims at providing a display panel's test circuit and OLED display has the effect that realizes lighting test to neotype display panel, can improve the product percent of pass.
The application provides a test circuit of a display panel, the display panel comprises a plurality of pixel structures arranged in an array, each pixel structure comprises four pixel units arranged in a rectangular array, each pixel unit comprises an R sub-pixel, a G sub-pixel and a B sub-pixel, and each column of sub-pixels comprises two sub-pixels or one sub-pixel; the test circuit includes:
three input data signal lines including an R data signal line, a G data signal line, and a B data signal line;
the three control voltage signal lines comprise an R control voltage signal line, a G control voltage signal line and a B control voltage signal line;
the testing unit comprises six gating modules, the output ends of the six gating modules are respectively connected with 6 columns of sub-pixels of the pixel structure, and the output end of each gating module is respectively connected with each sub-pixel in one column of sub-pixels; the input end of each gating module is respectively connected with one data signal line or two data signal lines corresponding to the sub-pixels of the corresponding column; and the control end of each gating module is respectively connected with one control voltage signal line or two control voltage signal lines corresponding to the sub-pixels of the corresponding row.
In the test circuit of a display panel described in the present application, the six gating modules include:
the first gating module comprises a first switching tube and a second switching tube, wherein the output end of the first switching tube is connected with the output end of the second switching tube and is connected with a first column of sub-pixels in a column of pixel structures, the input end of the first switching tube is connected with the G data signal line, the input end of the second switching tube is connected with the B data signal line, the control end of the first switching tube is connected with the G control voltage signal line, and the control end of the second switching tube is connected with the B control voltage signal line;
and the second gating module comprises a third switching tube, the input end of the third switching tube is connected with the G data signal line, and the output end of the third switching tube is connected with a second column of sub-pixels in a column of pixel structures.
In the test circuit of a display panel described in the present application, the six gating modules further include:
a third gating module, including a fourth switching tube and a fifth switching tube, where an output end of the fourth switching tube is connected to an output end of the fifth switching tube and to a third row of sub-pixels in a row of pixel structures, an input end of the fourth switching tube is connected to the B data signal line, an input end of the fifth switching tube is connected to the R data signal line, a control end of the fourth switching tube is connected to the B control voltage signal line, and a control end of the fifth switching tube is connected to the R control voltage signal line;
the fourth gating module comprises a sixth switching tube and a seventh switching tube, the output end of the sixth switching tube is connected with the output end of the seventh switching tube and connected with a fourth column of sub-pixels in a column of pixel structures, the input end of the sixth switching tube is connected with the B data signal line, the input end of the seventh switching tube is connected with the R data signal line, the control end of the sixth switching tube is connected with the B control voltage signal line, and the control end of the seventh switching tube is connected with the R control voltage signal line.
In the test circuit of a display panel described in the present application, the six gating modules further include:
the input end of the eighth switching tube is connected with the G data signal line, and the output end of the eighth switching tube is connected with a fifth column of sub-pixels in a column of pixel structures;
the sixth gating module comprises a ninth switching tube and a tenth switching tube, wherein the output end of the ninth switching tube is connected with the output end of the tenth switching tube and connected with a sixth row of sub-pixels in a row of pixel structures, the input end of the ninth switching tube is connected with the B data signal line, the input end of the tenth switching tube is connected with the R data signal line, the control end of the ninth switching tube is connected with the B control voltage signal line, and the control end of the tenth switching tube is connected with the R control voltage signal line.
In the test circuit of the display panel, the voltage transmitted by the G control voltage signal line is a low level signal, so that the second gate module and the fifth gate module are in a conducting state.
In this application display panel's test circuit, with same R control voltage signal line or same the switch tube's that B control voltage signal line is connected conduction state is the same, the conduction state of the switch tube that R control voltage signal line is connected with the switch tube's that B control voltage signal line is connected conduction state is opposite.
In the test circuit of the display panel, the first switch tube, the second switch tube, the third switch tube, the fourth switch tube, the fifth switch tube, the sixth switch tube, the seventh switch tube, the eighth switch tube, the ninth switch tube and the tenth switch tube are all field effect thin film transistors.
In the test circuit of the display panel, the first switch tube, the second switch tube, the third switch tube, the fourth switch tube, the fifth switch tube, the sixth switch tube, the seventh switch tube, the eighth switch tube, the ninth switch tube and the tenth switch tube are all P-type field effect thin film transistors.
In the test circuit of the display panel, the display panel is an OLED display panel.
An OLED display, comprising the test circuit of the display panel.
This application is through adopting neotype test circuit, through setting up a plurality of gating modules to the realization is lighted the effect of test to neotype display panel, can improve the product percent of pass.
Drawings
In order to more clearly illustrate the technical solutions in the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a test circuit of a display panel in some embodiments of the present application.
FIG. 2 is a first timing diagram of a test circuit of a display panel according to some embodiments of the present disclosure.
FIG. 3 is a second timing diagram of a test circuit of a display panel according to some embodiments of the present disclosure.
Detailed Description
Specific structural and functional details disclosed herein are merely representative and are provided for purposes of describing example embodiments of the present application. This application may, however, be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present application, it is to be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in the orientation or positional relationship indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and therefore should not be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified. Furthermore, the term "comprises" and any variations thereof is intended to cover non-exclusive inclusions.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a test circuit of a display panel in some embodiments of the present application. The test circuit of the display panel is used for the lighting test of the display panel.
The display panel comprises a plurality of pixel structures 100 arranged in an array, each pixel structure 100 comprises four pixel units 101 arranged in a rectangular array, each pixel unit 101 comprises three sub-pixels 1011, namely an R sub-pixel, a G sub-pixel and a B sub-pixel, and each column of sub-pixels 1011 comprises two sub-pixels 1011 or one sub-pixel 1011.
Specifically, the test circuit 200 includes: three input data signal lines CT-R \ CT-G \ CT-B, three control voltage signal lines CT-EN-R \ CT-EN-G \ CT-EN-B and a plurality of test units 201.
The three input data signal lines include an R data signal line CT-R, G data signal line CT-G and a B data signal line CT-B. The control voltage signal lines include an R control voltage signal line CT-EN-R, G control voltage signal line CT-EN-G and a B control voltage signal line CT-EN-B.
Each of the test units 201 includes six gating modules, output ends of the six gating modules are respectively connected to 6 columns of sub-pixels 1011 of the pixel structure 100, and an output end of each of the gating modules is respectively connected to each of the sub-pixels 1011 in one column of sub-pixels 1011; the input end of each gating module is respectively connected with one data signal line or two data signal lines corresponding to the sub-pixels 1011 in the corresponding row; and the control end of each gating module is respectively connected with one control voltage signal line or two control voltage signal lines corresponding to the sub-pixels of the corresponding row.
Specifically, the six gating modules include: the first gating module, the second gating module, the third gating module, the fourth gating module, the fifth gating module and the sixth gating module.
The first gating module includes a first switch transistor T1 and a second switch transistor T2, an output terminal of the first switch transistor T1 is connected to an output terminal of the second switch transistor T2 and to a first column of sub-pixels 1011 in a column of pixel structures 100, an input terminal of the first switch transistor T1 is connected to the G data signal line CT-R, an input terminal of the second switch transistor T2 is connected to the B data signal line CT-B, a control terminal of the first switch transistor T1 is connected to the G control voltage signal line CT-G, and a control terminal of the second switch transistor T2 is connected to the B control voltage signal line.
The second gating module comprises a third switching tube T3, an input end of the third switching tube T3 is connected to the G data signal line CT-G, and an output end of the third switching tube T3 is connected to the second column of sub-pixels 1011 in the column of pixel structure.
The third gating module includes a fourth switching tube T4 and a fifth switching tube T5, an output terminal of the fourth switching tube T4 is connected to an output terminal of the fifth switching tube T5 and to a third column of subpixels 1011 in a column of pixel structures 100, an input terminal of the fourth switching tube T4 is connected to the B data signal line CT-B, an input terminal of the fifth switching tube T5 is connected to the R data signal line, a control terminal of the fourth switching tube T4 is connected to the B control voltage signal line, and a control terminal of the fifth switching tube T5 is connected to the R control voltage signal line.
The pixel structure comprises a sixth switching tube T6 and a seventh switching tube T7, wherein an output end of the sixth switching tube T6 is connected to an output end of the seventh switching tube T7 and to a fourth column of sub-pixels in a column of pixel structures, an input end of the sixth switching tube T6 is connected to the B data signal line, an input end of the seventh switching tube T7 is connected to the R data signal line, a control end of the sixth switching tube T6 is connected to the B control voltage signal line, and a control end of the seventh switching tube T7 is connected to the R control voltage signal line CT-EN-R.
The fifth gating module comprises an eighth switching tube T8, an input end of the eighth switching tube T8 is connected to the G data signal line, and an output end of the eighth switching tube is connected to a fifth column of sub-pixels in a column of pixel structures.
The sixth gating module includes a ninth switching tube T9 and a tenth switching tube T10, an output terminal of the ninth switching tube T9 is connected to an output terminal of the tenth switching tube T10 and to a sixth column of sub-pixels in a column of pixel structures, an input terminal of the ninth switching tube T9 is connected to the B data signal line, an input terminal of the tenth switching tube T10 is connected to the R data signal line, a control terminal of the ninth switching tube T9 is connected to the B control voltage signal line, and a control terminal of the tenth switching tube is connected to the R control voltage signal line CT-EN-R.
In some embodiments, the first switching tube, the second switching tube, the third switching tube, the fourth switching tube, the fifth switching tube, the sixth switching tube, the seventh switching tube, the eighth switching tube, the ninth switching tube and the tenth switching tube are all field effect thin film transistors. The first switch tube, the second switch tube, the third switch tube, the fourth switch tube, the fifth switch tube, the sixth switch tube, the seventh switch tube, the eighth switch tube, the ninth switch tube and the tenth switch tube are all P-type field effect thin film transistors.
Specifically, when the first row pixel structure is driven, the timing control of the input data signal line is as shown in fig. 2, Scan [1] controls the writing of the data signal in the first row 100, and Scan [2] controls the writing of the 2 nd row pixel structure 100. The first row of data signals drives the first row of pixel structures 100 for a time period X, and rgbggr … … data is written for the first row, successfully driving the first row of pixel structures 100.
Specifically, when the second row of pixel structures are driven, the timing control of the input data signal line is as shown in fig. 3, Scan [2] controls the writing of the 2 nd row of data signals, the second row of data signals drives the second row of pixel structures 100 for a time period of Y, and the second row of pixel structures 100 are successfully driven along with the writing of BGRRGB … … data in the first row. Driving each subsequent row: the working state of the odd-numbered row CT is consistent with the first-row pixel structure, and the working state of the even-numbered row CT is consistent with the second-row pixel structure.
During driving, the voltage transmitted by the G control voltage signal line is a low level signal, so that the second gating module and the fifth gating module are in a conducting state. The conduction state of the switch tube connected with the same R control voltage signal line or the same B control voltage signal line is the same, and the conduction state of the switch tube connected with the R control voltage signal line is opposite to that of the switch tube connected with the B control voltage signal line.
This application is through adopting neotype test circuit, through setting up a plurality of gating modules to the realization is lighted the effect of test to neotype display panel, can improve the product percent of pass.
The principles and embodiments of the present application have been described herein using specific examples, which are presented only to assist in understanding the present application. Meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A test circuit of a display panel comprises a plurality of pixel structures arranged in an array, wherein each pixel structure comprises four pixel units arranged in a rectangular array, each pixel unit comprises an R sub-pixel, a G sub-pixel and a B sub-pixel, and each column of sub-pixels comprises two sub-pixels or one sub-pixel; wherein the test circuit comprises:
three input data signal lines including an R data signal line, a G data signal line, and a B data signal line;
the three control voltage signal lines comprise an R control voltage signal line, a G control voltage signal line and a B control voltage signal line;
the testing unit comprises six gating modules, the output ends of the six gating modules are respectively connected with 6 columns of sub-pixels of the pixel structure, and the output end of each gating module is respectively connected with each sub-pixel in one column of sub-pixels; the input end of each gating module is respectively connected with one data signal line or two data signal lines corresponding to the sub-pixels of the corresponding column; and the control end of each gating module is respectively connected with one control voltage signal line or two control voltage signal lines corresponding to the sub-pixels of the corresponding row.
2. The test circuit of the display panel according to claim 1, wherein the six gating modules comprise:
the first gating module comprises a first switching tube and a second switching tube, wherein the output end of the first switching tube is connected with the output end of the second switching tube and is connected with a first column of sub-pixels in a column of pixel structures, the input end of the first switching tube is connected with the G data signal line, the input end of the second switching tube is connected with the B data signal line, the control end of the first switching tube is connected with the G control voltage signal line, and the control end of the second switching tube is connected with the B control voltage signal line;
and the second gating module comprises a third switching tube, the input end of the third switching tube is connected with the G data signal line, and the output end of the third switching tube is connected with a second column of sub-pixels in a column of pixel structures.
3. The test circuit of the display panel according to claim 2, wherein the six gating modules further comprise:
a third gating module, including a fourth switching tube and a fifth switching tube, where an output end of the fourth switching tube is connected to an output end of the fifth switching tube and to a third row of sub-pixels in a row of pixel structures, an input end of the fourth switching tube is connected to the B data signal line, an input end of the fifth switching tube is connected to the R data signal line, a control end of the fourth switching tube is connected to the B control voltage signal line, and a control end of the fifth switching tube is connected to the R control voltage signal line;
the fourth gating module comprises a sixth switching tube and a seventh switching tube, the output end of the sixth switching tube is connected with the output end of the seventh switching tube and connected with a fourth column of sub-pixels in a column of pixel structures, the input end of the sixth switching tube is connected with the B data signal line, the input end of the seventh switching tube is connected with the R data signal line, the control end of the sixth switching tube is connected with the B control voltage signal line, and the control end of the seventh switching tube is connected with the R control voltage signal line.
4. The test circuit of the display panel according to claim 3, wherein the six gating modules further comprise:
the input end of the eighth switching tube is connected with the G data signal line, and the output end of the eighth switching tube is connected with a fifth column of sub-pixels in a column of pixel structures;
the sixth gating module comprises a ninth switching tube and a tenth switching tube, wherein the output end of the ninth switching tube is connected with the output end of the tenth switching tube and connected with a sixth row of sub-pixels in a row of pixel structures, the input end of the ninth switching tube is connected with the B data signal line, the input end of the tenth switching tube is connected with the R data signal line, the control end of the ninth switching tube is connected with the B control voltage signal line, and the control end of the tenth switching tube is connected with the R control voltage signal line.
5. The test circuit for a display panel according to claim 4, wherein the voltage transmitted by the G control voltage signal line is a low level signal, so that the second gate module and the fifth gate module are in a conducting state.
6. The test circuit for a display panel according to claim 4, wherein the conduction state of the switching tube connected to the same R control voltage signal line or the same B control voltage signal line is the same, and the conduction state of the switching tube connected to the R control voltage signal line is opposite to the conduction state of the switching tube connected to the B control voltage signal line.
7. The test circuit for the display panel according to claim 4, wherein the first switch tube, the second switch tube, the third switch tube, the fourth switch tube, the fifth switch tube, the sixth switch tube, the seventh switch tube, the eighth switch tube, the ninth switch tube and the tenth switch tube are all field effect thin film transistors.
8. The test circuit for a display panel according to claim 7, wherein the first switch tube, the second switch tube, the third switch tube, the fourth switch tube, the fifth switch tube, the sixth switch tube, the seventh switch tube, the eighth switch tube, the ninth switch tube and the tenth switch tube are all P-type field effect thin film transistors.
9. The test circuit of claim 1, wherein the display panel is an OLED display panel.
10. An OLED display characterized by comprising a test circuit of the display panel claimed in any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201911177923.3A CN111063282A (en) | 2019-11-27 | 2019-11-27 | Test circuit of display panel and OLED display |
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| CN201911177923.3A CN111063282A (en) | 2019-11-27 | 2019-11-27 | Test circuit of display panel and OLED display |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112002275A (en) * | 2020-09-04 | 2020-11-27 | 昆山国显光电有限公司 | Test circuit and test method of display panel and display panel |
| CN113223433A (en) * | 2021-05-19 | 2021-08-06 | Oppo广东移动通信有限公司 | Display panel, test method and test system thereof and display equipment |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101390004A (en) * | 2006-02-24 | 2009-03-18 | 飞利浦拉米尔德斯照明设备有限责任公司 | Multi-colored led array with improved color uniformity |
| US20130141314A1 (en) * | 2011-12-01 | 2013-06-06 | Ji-Hyun Ka | Detecting method of defects of line and demultiplexer, defect detecting device, and display panel including the defect detecting device |
| US20150090961A1 (en) * | 2013-10-02 | 2015-04-02 | Samsung Display Co., Ltd. | Organic light-emitting display panel |
| US20160267826A1 (en) * | 2015-03-11 | 2016-09-15 | Samsung Display Co., Ltd. | Display panel |
| CN108615504A (en) * | 2018-05-10 | 2018-10-02 | 武汉华星光电半导体显示技术有限公司 | DEMUX display panels and OLED display |
| CN108806602A (en) * | 2013-05-31 | 2018-11-13 | 三星显示有限公司 | Organic light emitting display panel |
| US20180366052A1 (en) * | 2016-08-12 | 2018-12-20 | Boe Technology Group Co., Ltd. | Pixel structure, display panel and driving method thereof |
| CN110379346A (en) * | 2019-07-19 | 2019-10-25 | 上海天马有机发光显示技术有限公司 | Display panel and preparation method thereof, test method and display device |
-
2019
- 2019-11-27 CN CN201911177923.3A patent/CN111063282A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101390004A (en) * | 2006-02-24 | 2009-03-18 | 飞利浦拉米尔德斯照明设备有限责任公司 | Multi-colored led array with improved color uniformity |
| US20130141314A1 (en) * | 2011-12-01 | 2013-06-06 | Ji-Hyun Ka | Detecting method of defects of line and demultiplexer, defect detecting device, and display panel including the defect detecting device |
| CN108806602A (en) * | 2013-05-31 | 2018-11-13 | 三星显示有限公司 | Organic light emitting display panel |
| US20150090961A1 (en) * | 2013-10-02 | 2015-04-02 | Samsung Display Co., Ltd. | Organic light-emitting display panel |
| US20160267826A1 (en) * | 2015-03-11 | 2016-09-15 | Samsung Display Co., Ltd. | Display panel |
| US20180366052A1 (en) * | 2016-08-12 | 2018-12-20 | Boe Technology Group Co., Ltd. | Pixel structure, display panel and driving method thereof |
| CN108615504A (en) * | 2018-05-10 | 2018-10-02 | 武汉华星光电半导体显示技术有限公司 | DEMUX display panels and OLED display |
| CN110379346A (en) * | 2019-07-19 | 2019-10-25 | 上海天马有机发光显示技术有限公司 | Display panel and preparation method thereof, test method and display device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112002275A (en) * | 2020-09-04 | 2020-11-27 | 昆山国显光电有限公司 | Test circuit and test method of display panel and display panel |
| CN113223433A (en) * | 2021-05-19 | 2021-08-06 | Oppo广东移动通信有限公司 | Display panel, test method and test system thereof and display equipment |
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