CN111048435A - Defect monitoring method - Google Patents
Defect monitoring method Download PDFInfo
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- CN111048435A CN111048435A CN201911360930.7A CN201911360930A CN111048435A CN 111048435 A CN111048435 A CN 111048435A CN 201911360930 A CN201911360930 A CN 201911360930A CN 111048435 A CN111048435 A CN 111048435A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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Abstract
The invention provides a defect monitoring method, which comprises the following steps: carrying out pattern scanning on the product, and searching out the wafer which does not satisfy the rows of the three chips; dividing all chips on a wafer into two areas, wherein the first area comprises the chips at the periphery of the wafer, and the second area comprises the chips inside; comparing each chip of the first area with the adjacent chip in the front one by one in sequence; and comparing the chip in the second area with the front chip and the rear chip respectively to obtain comparison data of the chips in the two areas. In the defect monitoring method provided by the invention, any defect monitoring method can be used for detecting the chips with the number less than three in a row, namely scanning and detecting all the chips on the wafer, so that the yield of the finished wafer product is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a defect monitoring method.
Background
In the face of the semiconductor industry, increasing the yield of products is becoming a major key element of core competitiveness. How to catch the defect effectively in real time through the defect scanning board in each step of yield detection of production line operation to the not enough that appears in the management and control technology process prevents bigger profit loss, becomes vital importance.
In the existing defect scanning machine, the defect is captured by comparing a chip (Die) with a left chip and a right chip of the chip, so that scanning can be normally performed only by scanning at least three chips in each row, but the scanning is not performed by using the prior art because the scanning is lower than that of the two chips, thereby increasing the risk of Yield reduction (Wafer Low Yield) of finished wafers.
Disclosure of Invention
The invention aims to provide a defect monitoring method which can detect the defects of all chips on a wafer. The yield of the wafer product is improved.
In order to achieve the above object, the present invention provides a defect monitoring method, including:
carrying out pattern scanning on the product, and searching out the wafer which does not satisfy the rows of the three chips;
counting the total number of chips on the wafer, and numbering each chip;
each chip is compared with the previous chip;
data for final comparison was obtained.
Optionally, in the defect monitoring method, the wafer is divided into a plurality of chips, the chips exist in a form of multiple rows and multiple columns, and are arranged on the wafer in an array form.
Optionally, in the defect monitoring method, the numbering method is as follows: the chips in each row are numbered sequentially, starting with the first chip in the first row, and numbering clockwise.
The invention also provides a defect monitoring method, which comprises the following steps:
carrying out pattern scanning on the product, and searching out the wafer which does not satisfy the rows of the three chips;
dividing all chips on a wafer into two areas, wherein the first area comprises the chips at the periphery of the wafer, and the second area comprises the chips inside;
comparing each chip of the first area with the adjacent chip in the front one by one in sequence;
and comparing the chip in the second area with the front chip and the rear chip respectively to obtain comparison data of the chips in the two areas.
Optionally, in the defect monitoring method, a dividing method of the first area and the second area is as follows: and any chip in any row or any column is the outermost chip, the row or the column is classified as the first area, and the rest chips are classified as the second area.
Optionally, in the defect monitoring method, the method for comparing each chip in the first area with an adjacent chip in the front one by one sequentially includes: the chips in the first area are named line by line starting from the first line, and each chip is compared with the adjacent chip before the chip in turn.
The invention also provides a defect monitoring method, which comprises the following steps:
carrying out pattern scanning on the product, and searching out the wafer which does not satisfy the rows of the three chips;
dividing the wafer crystal into a plurality of grid areas, and comparing the chip in each grid with the chip in front of the chip in the same grid to obtain comparison data of the grids.
Optionally, in the defect monitoring method, the grid dividing method divides the entire wafer into a plurality of grid areas with reference to a pattern mask.
Optionally, in the defect monitoring method, each cell includes one or more chips.
In the defect monitoring method provided by the invention, any defect monitoring method can be used for detecting the chips with the number less than three in a row, namely scanning and detecting all the chips on the wafer, so that the yield of the finished wafer product is improved.
Drawings
Fig. 1 is a schematic diagram of chip division according to a first embodiment and a second embodiment of the present invention;
FIG. 2 is a flowchart of a defect monitoring method according to a first embodiment of the present invention;
FIG. 3 is a flowchart of a defect monitoring method according to a second embodiment of the present invention;
FIG. 4 is a flowchart of a defect monitoring method according to a third embodiment of the present invention;
FIG. 5 is a diagram illustrating chip partitioning according to a third embodiment of the present invention;
in the figure: 1-first lattice, 2-second lattice, 101-first chip, 102-second chip, 103-third chip, 104-fourth chip, 107-seventh chip, 108-eighth chip, 109-ninth chip, 110-tenth chip, 150-fifty-fifth chip, 156-fifty-sixth chip, 157-fifty-fifth chip, 161-sixteenth chip, 162-sixty-second chip, 163-sixty-third chip.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. Advantages and features of the present invention will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the following, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method.
The inventor finds that the scanning area can be increased and the Yield Loss (Yield Loss) can be prevented by extracting regular graph information, carrying out different calculation modes on graphs with different chip sizes and adopting different operation modes to solve the problem of comparison between chips of different products. Referring to fig. 1, a plurality of lattices are chips on a wafer, and it can be seen that the condition that at least three chips are located in the same row is not satisfied by the first chip 101 in one row, so that it is necessary to have sixty-second chips 162 and sixty-third chips 163 in the last row, and therefore, if the first row and the last row cannot be scanned and detected using the prior art, a new defect scanning method needs to be provided, and the present invention provides three scanning methods.
Example one
Referring to fig. 2, an embodiment of the present invention provides a defect monitoring method, including:
s11: carrying out pattern scanning on the product, and searching out the wafer which does not satisfy the rows of the three chips;
s12: counting the total number of chips on the wafer, and numbering each chip;
s13: each chip is compared with the previous chip;
s14: data for final comparison was obtained.
Specifically, the number of chips is counted according to a photomask graph used by the wafer, and the distribution of the chips is known in real time. For example, in FIG. 1, the chip has a row of less than three chips, and therefore, the chip is screened out. The number of chips is then scanned out by prior art techniques.
In this embodiment, the wafer is divided into a plurality of chips, the chips exist in a plurality of rows and columns, and are arranged on the wafer in an array. The wafer is generally circular, a plurality of chips in a square grid shape are distributed on the wafer, and the plurality of chips exist in an array form, so that all the chips cannot be uniformly divided, that is, the number of the chips in each row may be different, and a column at the edge may have a few chips, for example, a row less than three chips. In the invention, the chips on the wafer are detected by adopting three methods, and all the chips can be detected, thereby improving the yield of products.
In this embodiment, the numbering method includes: the chips in each row are numbered sequentially, starting with the first chip in the first row, and numbering clockwise. One direction is selected, the most marginal row is taken as the first row, for example, the row where the first chip 101 is located in fig. 1, the row is named clockwise, after the chips in the whole row are named, the next row is continued, and all the chips are named sequentially. Up to the last row, for example the row where the second chip 102 of fig. 1 is located. And then each chip is compared with the previous chip to obtain comparison data and judge whether the defects occur. For example, in fig. 1, the second chip 102 is compared with the first chip 101 to obtain comparison data, and the third chip 103 is compared with the second chip 102 to obtain comparison data.
Example two
Referring to fig. 3, a second embodiment of the present invention provides a defect monitoring method, including:
s21: carrying out pattern scanning on the product, and searching out the wafer which does not satisfy the rows of the three chips;
s22: dividing all chips on a wafer into two areas, wherein the first area comprises the chips at the periphery of the wafer, and the second area comprises the chips inside;
s23: comparing each chip of the first area with the adjacent chip in the front one by one in sequence;
s24: and comparing the chip in the second area with the front chip and the rear chip respectively to obtain comparison data of the chips in the two areas.
In this embodiment, the method for dividing the first area and the second area includes: and any chip in any row or any column is the outermost chip, the row or the column is classified as the first area, and the rest chips are classified as the second area. The wafer is circular, the shape formed by a plurality of chips similar to the lattice shape is not a regular square shape, and the row or the column at the edge may not have three chips, so that the chips can be divided into two areas for data comparison respectively. For example, the row of the first chip 101, the row of the second chip 102, the row of the seventh chip 107, the row of the fifty-sixth chip 156, the row of the fifty-seventh chip 157 and the row of the sixty-second chip 162 in fig. 1 all belong to the peripheral chips of the wafer, and are divided into the first area, and the chips in other rows and other columns are divided into the second area.
In this embodiment, the method for comparing each chip in the first area with an adjacent chip in the front in sequence includes: the chips in the first area are named line by line starting from the first line, each chip is compared with the adjacent chip before the chip in sequence, and each chip can be named line by line anticlockwise. In other embodiments of the invention, each chip may also be named clockwise row by row. For example, in fig. 1, the second chip 102 is compared with the first chip 101, the fifty-sixth chip 156 is compared with the fifty-sixth chip 150, and the sixty-second chip 162 is compared with the sixty-sixth chip 161, so as to obtain the comparison data of all the chips except the first chip 101 in the first region respectively. The comparison data of the second area is compared by the prior art comparison method, i.e. each chip is compared with the adjacent chips in front of and behind the chip. Finally, the comparison data of all chips except the first chip 101 is obtained.
EXAMPLE III
Referring to fig. 4, a third embodiment of the present invention provides a defect monitoring method, which is characterized by including:
s31: carrying out image scanning on the product, and searching out chips which do not meet the line of three chips;
s32: dividing the wafer into a plurality of grid areas, and comparing the chip in each grid with the chip in front of the chip in the same grid to obtain comparison data of the grids.
In this embodiment, the grid dividing method divides the entire wafer into a plurality of grid regions with reference to the pattern mask. Since the wafer is a prototype and the lattice area is square, the number of chips contained in one lattice in the edge area of the wafer is inconsistent with the number of chips in the middle lattice after division.
In this embodiment, each cell contains one or more chips. The grid division can be realized by directly adopting a mask plate to divide the wafer into a plurality of grids, the size of the grids is not fixed, for example, fig. 5 only lists two grids, theoretically, the whole wafer is divided into grids, and only two grids are illustrated in the embodiment of the invention. The first lattice 1 incorporates therein the second chip 102, the seventh chip 107, and the eighth chip 108; the second lattice 2 incorporates therein the first chip 101, the third chip 103, the fourth chip 104, the ninth chip 109, and the tenth chip 110. The chips in the first grid 1 are respectively compared with the front adjacent chip in the first grid 1 to obtain the contrast data of a plurality of chips, and the chips in the second grid 2 are respectively compared with the front adjacent chip in the second grid 2 to obtain the contrast data of a plurality of chips, namely, each grid is independent, so that the contrast data of all the chips is finally obtained. Finally, the comparative data are analyzed to find defects, and the methods for analyzing the comparative data and finding defects used in the first embodiment, the second embodiment and the third embodiment are all the prior art and are not stated again.
Preferably, which method is used is selected according to the advantages of the respective methods. In terms of actual operability, the third method is to obtain the partition of the grid region immediately, and the partition can be directly used without background re-identification and combination, so that the time consumption is shortest; the first method has the longest time consumption because the first method is separated from the existing computing unit and needs full-image computing, but the last displayed information is the most complete from the aspect of map scanning; the second method is more biased to classify, the chips causing two condition differences in the process are classified when the defects are scanned, the defects are identified more specifically, and the method is quicker than the first method in time because the method can be simultaneously operated in a background by two systems.
In summary, in the defect monitoring method provided in the embodiment of the present invention, by using any one of the defect monitoring methods of the present invention, all chips on the wafer can be scanned and detected by detecting chips with a row number smaller than three, so that the yield of finished wafers is improved.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (9)
1. A method of defect monitoring, comprising:
carrying out pattern scanning on the product, and searching out the wafer which does not satisfy the rows of the three chips;
counting the total number of chips on the wafer, and numbering each chip;
each chip is compared with the previous chip;
data for final comparison was obtained.
2. The method of claim 1, wherein the wafer is divided into a plurality of chips, the chips are arranged in a plurality of rows and columns and are arranged on the wafer in an array.
3. The defect monitoring method of claim 2, wherein the numbering is by: the chips in each row are numbered sequentially, starting with the first chip in the first row, and numbering clockwise.
4. A method of defect monitoring, comprising:
carrying out pattern scanning on the product, and searching out the wafer which does not satisfy the rows of the three chips;
dividing all chips on a wafer into two areas, wherein the first area comprises the chips at the periphery of the wafer, and the second area comprises the chips inside;
comparing each chip of the first area with the adjacent chip in the front one by one in sequence;
and comparing the chip in the second area with the front chip and the rear chip respectively to obtain comparison data of the chips in the two areas.
5. The defect monitoring method of claim 4, wherein the first area and the second area are divided by: and any chip in any row or any column is the outermost chip, the row or the column is classified as the first area, and the rest chips are classified as the second area.
6. The defect monitoring method of claim 4, wherein comparing each chip of the first area with a previously adjacent chip in turn comprises: the chips in the first area are named line by line starting from the first line, and each chip is compared with the adjacent chip before the chip in turn.
7. A method of defect monitoring, comprising:
carrying out pattern scanning on the product, and searching out the wafer which does not satisfy the rows of the three chips;
dividing the wafer into a plurality of grid areas, and comparing the chip in each grid with the chip in front of the chip in the same grid to obtain comparison data of the grids.
8. The method of claim 7, wherein the grid dividing method divides the entire wafer into a plurality of grid areas with reference to a pattern mask.
9. A method of defect monitoring as claimed in claim 7 wherein each cell contains one or more chips.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112557884A (en) * | 2020-11-18 | 2021-03-26 | 上海华力集成电路制造有限公司 | Method for detecting weak point defect |
| CN113096113A (en) * | 2021-04-27 | 2021-07-09 | 上海华虹宏力半导体制造有限公司 | Chip marking method, system, electronic device and computer readable storage medium |
| CN114113142A (en) * | 2022-01-24 | 2022-03-01 | 广州粤芯半导体技术有限公司 | Defect detection method and device for semiconductor device and electronic equipment |
| CN115346901A (en) * | 2022-10-17 | 2022-11-15 | 江西兆驰半导体有限公司 | LED wafer sorting method |
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