CN110992906A

CN110992906A - Drive method of Demux circuit

Info

Publication number: CN110992906A
Application number: CN201911128056.4A
Authority: CN
Inventors: 熊克; 谢建峰
Original assignee: Fujian Huajiacai Co Ltd
Current assignee: Fujian Huajiacai Co Ltd
Priority date: 2019-11-18
Filing date: 2019-11-18
Publication date: 2020-04-10

Abstract

A drive method of a Demux circuit includes at least two falling edges in an enable time domain of a Demux sub-pixel drive signal. Specifically, the enable time domain including the Demux pixel driving signal belongs to the enable time domain of the Gate driving line of the current stage. Specifically, the sub-pixels in the Demux sub-pixel driving signal comprise an R sub-pixel, a B sub-pixel and a G sub-pixel. Optionally, the preset falling amplitudes of the falling edges are equal. Preferably, the start time interval between the falling edges may be set to 1 ± 0.2 μ s, which is different from the prior art, and the above scheme can reduce the normal display at the display position of the chromaticity shift boundary by adjusting the fluctuation of the VCOM circuit by the Demux driving circuit.

Description

Drive method of Demux circuit

Technical Field

The invention relates to a pixel circuit display optimization technology, in particular to a Demux circuit driving method capable of better de-interleaving.

Background

In the liquid crystal display screen, the deinterlacing (Demux signal) of the sub-pixel color of the corresponding liquid crystal display is adjusted mainly by supplying power to the liquid crystal display pixel through the positive, negative and amplitude of the electricity. The existing liquid crystal display screen has the problem that voltage deviation is caused by coupling of a Demux circuit to an on-chip VCOM, and finally abnormal display is caused on partial horizontal straight lines.

Disclosure of Invention

Therefore, a new drive method of the Demux circuit needs to be provided to solve the problem of abnormal display of the liquid crystal display screen in the prior art.

To achieve the above object, the inventors provide a Demux circuit driving method including at least two falling edges in an enable time domain of Demux subpixel driving signals.

Specifically, the enable time domain including the Demux pixel driving signal belongs to the enable time domain of the Gate driving line of the current stage.

Specifically, the sub-pixels in the Demux sub-pixel driving signal comprise an R sub-pixel, a B sub-pixel and a G sub-pixel.

Optionally, the preset falling amplitudes of the falling edges are equal.

Preferably, the start time interval between falling edges may be set to 1 ± 0.2 μ s.

Different from the prior art, the scheme can adjust the fluctuation of the VCOM circuit through the Demux driving circuit, and reduce the normal display at the display position of the chromaticity transformation boundary.

Drawings

FIG. 1 is a schematic diagram of a display pattern according to an embodiment;

FIG. 2 is a schematic diagram of a defect display according to an embodiment;

FIG. 3 is a schematic diagram of a Demux LCD panel and parasitic capacitance according to an embodiment;

FIG. 4 is a schematic diagram of a front 1/3127 gray level VCOM according to an embodiment;

FIG. 5 is a timing diagram illustrating the principle of generating dark lines according to one embodiment;

FIG. 6 is a timing diagram illustrating the bright line generation principle according to an embodiment;

FIG. 7 is a diagram illustrating a normal gray level after timing adjustment according to an embodiment;

FIG. 8 is an exemplary diagram illustrating dark line elimination after timing adjustment according to an embodiment;

fig. 9 is an exemplary diagram of eliminating bright lines after timing adjustment according to an embodiment of the present invention.

Note 1: VCOM has not yet recovered to the original level when Gate is off, and the display is brighter than 127 gray scale.

Note 2: when Gate is off, VCOM returns to the original level, displaying 127 gray levels, since the front 1/3 screen is brighter, in contrast, a black line is formed.

Note 3: VCOM does not yet return to the original level when Gate is off, and is more negative, thus showing more brightness than 127 gray levels, in contrast to the formation of white lines.

Note 4: after the falling edge is adjusted, the amount of Demux coupling is reduced, and 127 gray levels can be correctly written.

Note 5: after the falling edge is adjusted, the amount of Demux coupling is reduced, and 127 gray levels can be correctly written.

Note 6: after the falling edge is adjusted, the amount of Demux coupling is reduced, and 127 gray levels can be correctly written.

Detailed Description

To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.

In the liquid crystal display screen, the deinterlacing (Demux signal) of the sub-pixel color of the corresponding liquid crystal display is adjusted mainly by supplying power to the liquid crystal display pixel through the positive, negative and amplitude of the electricity. In a specific example, please refer to fig. 1, which is a specific pattern for displaying a liquid crystal display, in a general display, a display result may be as shown in fig. 2, and a bright line or a dark line appearing at a bright-dark boundary is a display defect. Fig. 3, parasitic capacitance present in Demux lcd displays. Demux can represent three cases of Demux R (red sub-pixel de-interleaving circuit)/Demux G (green sub-pixel de-interleaving circuit)/Demux B (blue sub-pixel de-interleaving circuit), respectively, in which one parasitic capacitance C2 exists between Data Line and VCOM and one parasitic capacitance C1 exists between Demux and Data Line in panel.

In the embodiment shown in FIG. 4, a diagram of 127 gray levels VCOM for the front 1/3 display is shown. The VCOM above and above the dark line in FIG. 2 is coupled by Demux R/Demux G/Demux B according to the following coupling principle: when the Gate is turned on, the Demux falling edge pulls down the voltage on the Data Line through the parasitic capacitor C1 existing between Demux and Data Line, and after the voltage on the Data Line falls, the voltage on VCOM is pulled down through the parasitic capacitor existing between the Data Line and VCOM, so that the VCOM voltage deviates from Best VCOM, and Real VCOM cannot be restored to Best VCOM before the Gate is turned off, thereby lowering the VCOM voltage of the front 1/3127 gray scale (the portion of the display screen above the black Line in fig. 2). This causes the voltage difference between the Pixel electrode and the VCOM electrode to be increased, and the luminance of the front 1/3127 gray level display is higher than the normal 127 gray level display.

Fig. 5, principle timing of dark line generation. In the image of fig. 1, when the 127 gray scale is transited to the 255 gray scale (indicated by 127 ≈ 255 ×) the voltage on the Data Line corresponding to Demux R increases, the Data Line voltage increases due to the parasitic capacitance between the Data Line and the VCOM electrode, and the VCOM voltage is also coupled to increase; when the falling edge of Demux R is encountered, the falling edge of Demux R pulls down the voltage on the Data Line through a parasitic capacitor C1 existing between Demux R and the Data Line; the voltage on the Data Line corresponding to the Demux G is increased, and due to the parasitic capacitance between the Data Line and the VCOM electrode, the voltage of the Data Line is increased, and the VCOM voltage is also coupled to be increased; when the falling edge of Demux G is encountered, the falling edge of Demux G pulls down the voltage on the Data Line through a parasitic capacitor C1 existing between Demux G and the Data Line; the voltage on the Data Line corresponding to the Demux B is increased, and due to the parasitic capacitance between the Data Line and the VCOM electrode, the voltage of the Data Line is increased, and the VCOM voltage is also coupled to be increased; when the falling edge of Demux G is encountered, the falling edge of Demux B will pull down the voltage on the Data Line through the parasitic capacitance C1 existing between Demux B and Data Line; however, VCOM can be restored to Best VCOM before Gate is turned off, so the brightness displayed here is normal 127 gray level brightness. However, since the gray scale of 1/3127 at the front shows a higher luminance than the normal 127 gray scale, it appears as a dark line at this location in contrast.

Fig. 6 shows a timing chart of bright line generation principle. The voltage of the Data Line is decreased, namely 255 gray levels are transited to 127 gray levels, and the voltage of VCOM is pulled down through a parasitic capacitor C2 existing between the Data Line and the VCOM, so that the VCOM voltage is deviated from Best VCOM more; when the Demux falls, the Demux falls will pull down the voltage on the Data Line through the parasitic capacitor C1 existing between the Demux and the Data Line, and after the voltage of the Data Line falls, the voltage of VCOM is pulled down through the parasitic capacitor C2 existing between the Data Line and VCOM, so that the VCOM voltage deviates more from Best VCOM, and the Real VCOM cannot recover to Best VCOM before the Gate is turned off, so that when the 255 gray scale is transited to the 127 gray scale, the VCOM is more lower, and the voltage difference between the Pixel electrode and VCOM is larger, thereby displaying the bright Line.

FIG. 7 is a schematic diagram showing the gray level after timing adjustment. The specific adjustment manner is as shown in fig. 7, by adjusting the falling edge of the Demux waveform, the coupling effect of the Demux falling edge on the Data Line, that is, the coupling effect of the Data Line on the VCOM electrode, is reduced. The falling edge of Demux is first dropped to a voltage level such that at least two falling edges are included in the enable time domain of the Demux subpixel drive signal. Such as dropping to 0V (directly to-10 or more negative before no modulation), where VCOM is also coupled down, but is coupled small, the VCOM electrode is again replenished with charge anytime and anywhere, thus returning to the Best VCOM level quickly; and reducing Demux from 0V to-10V (which may be another negative voltage in one example), so that VCOM is coupled to a small level and VCOM electrode can return to Best VCOM level in time because Demux voltage is reduced in stages. The gray scale portion of the front 1/3 shows no anomalies.

In yet other embodiments, some embodiments may be implemented, and the falling edge of Demux may include more than two falling edges, and the multiple falling edges may make the change of Demux smaller, so as to further reduce the coupling degree of VCOM. VCOM can return to the ideal level in more time. Finally, the technical effect of better improving the display of the liquid crystal screen can be achieved.

Further, preset reduction amplitude values of the plurality of reduction edges can be set to be equal, and when the number of the reduction edges is two, the preset reduction amplitude value at each time is half of the total Demux pressure difference. The coupling value of VCOM can be more balanced every time when the preset falling amplitudes are equal, so that the fluctuation of VCOM can be better recovered in a short time, in a specific embodiment, the starting time interval between a plurality of falling edges can be set to 1 ± 0.2 μ s, and the effect of better improving the liquid crystal display can also be achieved.

The example of fig. 8 shows a timing adjusted dark line elimination diagram. When the picture encounters a 127 gray level to a 255 gray level, the Data Line has a stronger coupling effect on the VCOM electrode, the Data Line changes from 127 to 255, the voltage of the VCOM electrode is coupled upwards, the VCOM is as close as possible to Best VCOM because the VCOM electrode is constantly supplementing charges, but the Best VCOM cannot be restored in time because the coupling is too severe. When the Demux falling edge is encountered, the voltage of the VCOM electrode coupled by the Data Line is reduced upwards by adjusting the waveform falling edge of the Demux so as to reduce the coupling influence of the Demux falling edge on the Data Line. The falling edge of Demux is first dropped to a voltage level, such as 0V (directly to-10 or more negative before no modulation), at which time VCOM is also coupled down, but coupled small, the VCOM electrode is again recharged anytime and anywhere, thus returning quickly to the Best VCOM level; and reducing Demux from 0V to-10V (in this case, it can be another negative voltage), so that VCOM is coupled to be small, and VCOM electrode can return to Best VCOM level in time, and dark line abnormality is eliminated.

Fig. 9 shows a timing adjusted bright line elimination diagram. When the picture encounters 255 gray levels and transits to 127 gray levels, the Data Line has a strong coupling effect on the VCOM electrode, the Data Line changes from 255 to 127, the voltage of the VCOM electrode is coupled downwards, the VCOM is as close as possible to Best VCOM because the VCOM electrode is constantly supplementing charges, but the coupling is too severe to restore to Best VCOM in time. When a Demux falling edge is encountered, the voltage of a Data Line coupling VCOM electrode is reduced upwards by adjusting the waveform falling edge of Demux so as to reduce the coupling influence of the Demux falling edge on the Data Line. The falling edge of Demux is first dropped to a voltage level, such as 0V (directly to-10 or more negative before no modulation), at which time VCOM is also coupled down, but coupled small, the VCOM electrode is again recharged anytime and anywhere, thus returning quickly to Best VCOM level; and reducing Demux from 0V to-10V (in this case, it can be another negative voltage), so that VCOM is coupled to be small, so that VCOM electrode can return to Best VCOM level in time, and dark line abnormality is eliminated.

It should be noted that, although the above embodiments have been described herein, the invention is not limited thereto. Therefore, based on the innovative concepts of the present invention, the technical solutions of the present invention can be directly or indirectly applied to other related technical fields by making changes and modifications to the embodiments described herein, or by using equivalent structures or equivalent processes performed by the contents of the present specification and the attached drawings, which are included in the scope of the present invention.

Claims

1. A drive method of a Demux circuit is characterized by comprising at least two falling edges in an enabling time domain of a Demux sub-pixel drive signal.

2. The Demux circuit driving method according to claim 1, including an enable time domain of Demux pixel driving signals belonging to an enable time domain of a Gate driving line of a current stage.

3. The Demux circuit driving method according to claim 1, wherein the sub-pixels in the Demux sub-pixel driving signal include an R sub-pixel, a B sub-pixel, and a G sub-pixel.

4. The Demux circuit driving method according to claim 1, wherein the predetermined falling amplitudes of the falling edges are equal.

5. The Demux circuit driving method according to claim 1, wherein a start time interval between falling edges can be set to 1 ± 0.2 μ s.