CN110991635B - Circuit and implementation method of multi-mode synaptic time-dependent plasticity algorithm - Google Patents

Abstract

Embodiments of the present invention provide a circuit and implementation method of a multimodal synaptic time-dependent plasticity algorithm, including a time window generation circuit, a switch switching circuit, an OTA synapse circuit, a symmetrical circuit of the time window generating circuit, and a symmetrical circuit of the switch switching circuit Circuit; wherein, the time window generation circuit is used to output the time window sampling voltage under the action of the first control signal and the applied voltage; the switch switching circuit is used to switch the input of the OTA synapse circuit connected to the time window sampling voltage and the external reference voltage port; the OTA synaptic circuit is used to calculate the variation of the synaptic weight value under the action of the time window sampling voltage and the external reference voltage when the first external pulse signal and the second external pulse signal arrive, and convert the variation into the charge The form is stored on a storage capacitor connected to the output port of the OTA synaptic circuit. The embodiment of the present invention implements multiple synaptic time-dependent plasticity algorithms, which are simple to implement and flexible to adjust.

Description

Circuit and implementation method of multimodal synaptic time-dependent plasticity algorithm

technical field

The invention belongs to the technical field of artificial neural networks, and in particular relates to a circuit and an implementation method of a multimodal synaptic time-dependent plasticity algorithm.

Background technique

As a bionic artificial neural network, the spiking neural network adopts more biologically meaningful neurons, synapses and algorithm models. By imitating the characteristics, structure and operating mechanism of the biological impulse neural network, it is expected to obtain a higher level of artificial intelligence. At the same time, the spiking neural network adopts the integrated storage and calculation architecture of the biological nervous system, which can fundamentally solve the calculation bottleneck problem caused by the separation of storage and calculation in the traditional Von Neumann architecture.

Neuromorphic engineering is to provide a reasonable and effective hardware foundation for the realization of large-scale spiking neural networks. One of its important areas is the realization of various synapses, neurons and algorithmic circuits with biological characteristics by using VLSI (Very Large Scale Integration, very large scale integration) circuits. A class of algorithms that widely exist in biological impulse neural networks is called synaptic time-dependent plasticity algorithm. Its most basic feature is to adjust the synaptic weights according to certain rules according to the time difference and sequence of the membrane impulses before and after the synapse. , and then realize the learning and memory functions.

Studies have found that in different nervous system regions and under different conditions, there are many different synaptic time-dependent plasticity algorithm mechanisms. Currently, neuromorphic engineering of most synaptic algorithms often only implements one or two algorithms. Circuits that can implement multiple algorithms often use complex biological ion models, which are not friendly to hardware implementations. At the same time, precise adjustment of various parameter voltages is required to display different algorithms, which is not suitable for large-scale pulsed neural networks.

Contents of the invention

In order to overcome the above-mentioned existing synaptic algorithm circuit implementation of few types of algorithms, complex hardware and algorithm implementation, and low reconfigurability problems or at least partly solve the above problems, the embodiment of the present invention provides a multi-modal synaptic Circuit and implementation of time-dependent plasticity algorithm.

According to the first aspect of the embodiments of the present invention, a circuit of a multimodal synaptic time-dependent plasticity algorithm is provided, including:

including a time window generating circuit, a switch switching circuit, an OTA synapse circuit, a symmetrical circuit of the time window generating circuit, and a symmetrical circuit of the switching circuit;

Wherein, the time window generation circuit is used to output the time window sampling voltage under the action of the first control signal and the applied voltage;

The switch switching circuit is used to switch the input port of the OTA synapse circuit connected to the time window sampling voltage and the external reference voltage;

The OTA synaptic circuit is used to calculate the variation of the synaptic weight value under the action of the time window sampling voltage and the external reference voltage when the first external pulse signal and the second external pulse signal arrive, and calculate the The amount of change is stored in the form of charge on the storage capacitor connected to the output port of the OTA synaptic circuit.

According to the second aspect of an embodiment of the present invention, a method for implementing a multimodal synaptic time-dependent plasticity algorithm based on the circuit of the above-mentioned multimodal synaptic time-dependent plasticity algorithm is provided, including:

The time-window generation circuit generates multiple time-window sampling voltages under the action of the first control signal and the applied voltage;

The switch-based switching circuit is used to switch the input port of the OTA synaptic circuit connected to the time window sampling voltage and the external reference voltage;

When the first external pulse signal and the second external pulse signal arrive based on the OTA synaptic circuit calculation, the amount of change of the synapse weight under the action of the time window sampling voltage and the external reference voltage, and the amount of change Stored in the form of charge on the storage capacitor connected to the output port of the OTA synapse circuit.

The embodiment of the present invention provides a multi-modal synaptic time-dependent plasticity algorithm circuit and implementation method. The circuit adjusts the control signal, controls the time window generation circuit to generate various time window sampling voltages, and switches and time window sampling The input port of the OTA synapse circuit connected to the voltage and the external reference voltage enables the OTA synapse circuit to determine the change of the synaptic weight value according to the voltage difference of the input port under different switching conditions, thereby realizing a variety of synaptic time-dependent plasticity algorithms ; and the time scale and gain range of the algorithm can be adjusted by adjusting the applied voltage, which is suitable for large-scale spiking neural networks, with simple implementation and flexible adjustment.

Description of drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are For some embodiments of the present invention, those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic diagram of the overall circuit structure of the multimodal synaptic time-dependent plasticity algorithm provided by the embodiment of the present invention;

2 is a schematic structural diagram of a time window generation circuit in a circuit of a multimodal synaptic time-dependent plasticity algorithm provided by an embodiment of the present invention;

3 is a schematic structural diagram of a switch switching circuit in a circuit of a multimodal synaptic time-dependent plasticity algorithm provided by an embodiment of the present invention;

4 is a schematic structural diagram of the OTA synapse circuit in the circuit of the multimodal synaptic time-dependent plasticity algorithm provided by the embodiment of the present invention;

FIG. 5 is a schematic flowchart of a method for implementing a multimodal synaptic time-dependent plasticity algorithm provided by an embodiment of the present invention;

6 is a schematic diagram of the curve of the first algorithm implemented in the implementation method of the multimodal synaptic time-dependent plasticity algorithm provided by the embodiment of the present invention;

FIG. 7 is a schematic diagram of the curve of the second algorithm implemented in the implementation method of the multimodal synaptic time-dependent plasticity algorithm provided by the embodiment of the present invention;

Fig. 8 is a schematic diagram of the curve of the third algorithm implemented in the implementation method of the multimodal synaptic time-dependent plasticity algorithm provided by the embodiment of the present invention;

FIG. 9 is a schematic diagram of the curve of the fourth algorithm implemented in the implementation method of the multimodal synaptic time-dependent plasticity algorithm provided by the embodiment of the present invention;

Fig. 10 is a schematic diagram of the curve of the fifth algorithm implemented in the implementation method of the multimodal synaptic time-dependent plasticity algorithm provided by the embodiment of the present invention;

FIG. 11 is a schematic diagram of the sixth algorithm implemented in the implementation method of the multimodal synaptic time-dependent plasticity algorithm provided by the embodiment of the present invention;

Fig. 12 is a schematic diagram of the curve of the seventh algorithm implemented in the implementation method of the multimodal synaptic time-dependent plasticity algorithm provided by the embodiment of the present invention;

FIG. 13 is a schematic diagram of an eighth algorithm implemented in the implementation method of the multimodal synaptic time-dependent plasticity algorithm provided by the embodiment of the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

In one embodiment of the present invention, a circuit of a multimodal synaptic time-dependent plasticity algorithm is provided. FIG. 1 is a schematic diagram of the overall circuit structure of a multimodal synaptic time-dependent plasticity algorithm provided by an embodiment of the present invention. The circuit includes Time window generating circuit 10, switch switching circuit 20, OTA (Operational Transconductance Amplifier, transconductance amplifier) synaptic circuit 30, time window generating circuit 10 Symmetric circuit 10B and switch switching circuit 20 Symmetric circuit 20B;

Wherein, the OTA synaptic circuit 30 is an OTA-based synaptic circuit.

The time window generating circuit 10 is used to output the time window sampling voltage under the action of the first control signal V _CTR1 and the applied voltage;

The time window generating circuit 10 can generate various time window sampling voltages under the action of the first control signal V _CTR1 and the applied voltage, and outputs the time window sampling voltages in the preset mode each time. The preset mode is a preset mode, corresponding to the type of the time window sampling voltage one by one.

The switch switching circuit 20 is used to switch the input port of the OTA synaptic circuit connected to the time window sampling voltage and the external reference voltage;

The switch switching circuit 20 is used to determine the connection mode between the sampling voltage of the time window and the external reference voltage and different input ports of the OTA synapse circuit 30, so as to realize the corresponding multi-modal synapse time-dependent plasticity algorithm.

The OTA synapse circuit 30 is used to calculate the amount of change in the synaptic weight value under the action of the time window sampling voltage and the external reference voltage when the first external pulse signal and the second external pulse signal arrive, and convert the amount of change in the form of charge stored in the storage capacitor connected to the output port of the OTA synaptic circuit 30 .

In this embodiment, after the time window generation circuit 10 is started, the generated time window sampling voltage will be sent to the input port of the OTA synapse circuit 30 through the switch selection circuit 20 . The OTA synapse circuit 30 will calculate the size of the output current according to the different voltage differences of its input ports, and store it in the form of charge on the storage capacitor connected to its output port, and then change the voltage on the storage capacitor, that is, the synapse weight value size.

In this embodiment, by adjusting the control signal, the time window generation circuit is controlled to generate multiple time window sampling voltages, and by switching the input port of the OTA synapse circuit connected to the time window sampling voltage and the external reference voltage, the OTA synapse circuit is In different switching situations, the change of synaptic weight is determined according to the voltage difference of the input port, thereby realizing a variety of synaptic time-dependent plasticity algorithms; and the time scale and gain range of the algorithm can be adjusted by adjusting the applied voltage, which is suitable for large Scale spiking neural network, simple to implement and flexible to adjust.

On the basis of the above embodiments, as shown in FIG. 2, the time window generation circuit 10 in this embodiment includes first to tenth N-type transistors, namely NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8, NM9 and NM10, the first to third P-type transistors, namely PM1, PM2 and PM3, and the first capacitor C ₁ , the second capacitor C ₂ and the comparator Compare;

Wherein, the source of the first P-type transistor PM1 is connected to the external fourth common reference voltage port VCM4, the gate of the first P-type transistor PM1 is connected to the first bias voltage V _bin for controlling the charging current, and the first P-type transistor PM1 The drain of PM1 is connected to the source of the second P-type transistor PM2;

The gate of the second P-type transistor PM2 is connected to the gate of the second N-type transistor NM2 and the return signal port _Vback , and the drain of the second P-type transistor PM2 is connected to the drain of the second N-type transistor PM2, the first N The source of the N-type transistor NM1, the drain of the sixth N-type transistor NM6 are connected to the first pole of the first capacitor _C1 ;

The source of the third P-type transistor PM3 is connected to the external power supply voltage VDD, the gate of the third P-type transistor PM3 is connected to the gate of the tenth N-type transistor NM10, the return signal port V _back and the first control signal V _CTR1 ;

Wherein, the drain of the first N-type transistor NM1 is connected to the external power supply voltage VDD, and the gate of the first N-type transistor NM1 is connected to the first external pulse signal V _pre ;

The source of the second N-type transistor NM2 is connected to the drain of the third N-type transistor NM3;

The gate of the third N-type transistor NM3 is connected to the second bias voltage V _blk that controls the leakage current, and the source of the third N-type transistor NM3 is connected to the second pole of the first capacitor _C1 and the second common reference voltage VCM2 ;

The drain of the fourth N-type transistor NM4 is connected to the external power supply voltage VDD, the gate of the fourth N-type transistor NM4 is connected to the first external pulse signal _Vpre , and the source of the fourth N-type transistor NM4 is connected to the fifth N-type transistor. The drain of NM5, the first pole of the second capacitor _C2 , and the source of the seventh N-type transistor NM7 are connected;

The gate of the fifth N-type transistor NM5 is connected to the third bias voltage V _blk2 that controls the leakage current, and the source of the fifth N-type transistor NM5 is connected to the second pole of the second capacitor _C2 and the first common reference voltage VCM1 ;

The gate of the sixth N-type transistor NM6 is connected to the second external pulse signal V _post , and the source of the sixth N-type transistor NM6 is connected to the source of the ninth N-type transistor NM9 and the output port V _edcp of the time window sampling voltage;

The gate of the seventh N-type transistor NM7 is connected to the first control signal V _CTR1 , and the drain of the seventh N-type transistor NM7 is connected to the drain of the eighth N-type transistor NM8 and the anode of the comparator Compare;

The gate of the eighth N-type transistor NM8 is connected to the inversion signal V _CTR1~ of the first control signal V _CTR1 , and the source of the eighth N-type transistor NM8 is connected to the external ground signal GND;

The drain of the ninth N-type transistor NM9 is connected to the port V _REF of the external reference voltage, and the gate of the ninth N-type transistor NM9 is connected to the inverted signal V _post of the second external pulse signal V _post ;

The drain of the tenth N-type transistor NM10 is connected to the output end of the comparator Compare;

The negative input port of the comparator Compare is connected to the external reference voltage V _C of the comparator;

Wherein, the applied voltage includes the first bias voltage V _bin , the second bias voltage V _blk and the third bias voltage V _blk2 ; the return signal port V _back is used to return the second capacitor C ₂ at the third bias voltage V _blk2 , a signal generated under the action of the first control signal V _CTR1 and the complementary signal V _{CTR1 ˜} of the first control signal.

On the basis of the above-mentioned embodiment, as shown in FIG. NM15;

Wherein, the drain of the fourth P-type transistor PM4 is connected to the source of the fifteenth N-type transistor NM15 and the port of the external reference voltage V _REF , and the gate of the fourth P-type transistor PM4 is connected to the port of the fifteenth N-type transistor NM15. The gate is connected to the third control signal V _CTR3 , and the source of the fourth P-type transistor PM4 is connected to the fourth common reference voltage VCM4;

The gate of the eleventh N-type transistor NM11 is connected to the gate of the twelfth N-type transistor NM12 and the second control signal V _CTR2 , the drain of the eleventh N-type transistor NM11 is connected to the drain of the fourteenth N-type transistor NM14 pole and the output port V _edcp of the time window sampling voltage in the time window generating circuit 10, the source of the eleventh N-type transistor NM11 is connected with the source of the thirteenth N-type transistor NM13 and the first positive electrode of the OTA synapse circuit 30 input port OTAP connection;

The drain of the twelfth N-type transistor NM12 is connected to the drain of the thirteenth N-type transistor NM13 and the port V _REF of the external reference voltage, and the source of the twelfth N-type transistor NM12 is connected to the port V REF of the fourteenth N-type transistor NM14. The source is connected to the first negative input port OTAN of the OTA synapse circuit 30;

The gate of the thirteenth N-type transistor NM13 is connected to the gate of the fourteenth N-type transistor NM14 and the inverted signal V _CTR2 of the second control signal;

The drain of the fifteenth N-type transistor NM15 is connected to the third common reference voltage VCM3.

On the basis of the above-mentioned embodiments, as shown in FIG. 4, the OTA synaptic circuit in this embodiment includes fifth to eighth P-type transistors, namely PM5, PM6, PM7 and PM8, sixteenth to twenty-fifth N Type transistors, namely NM16, NM17, NM18, NM19, NM20, NM21, NM22, NM23, NM24 and NM25, and the first transmission tube TG1, the second transmission tube TG2 and the storage capacitor C _W ;

Wherein, the sources of the fifth to eighth P-type transistors are all connected to the external power supply voltage VDD;

The gate of the fifth P-type transistor PM5 is connected to the gate of the sixth P-type transistor PM6, the drain of the sixteenth N-type transistor NM16, and the drain of the eighteenth N-type transistor NM18, and the fifth P-type transistor PM5 The drain is connected to the drain and gate of the twenty-second N-type transistor NM22, and the gate of the twenty-fifth N-type transistor NM25;

The gate of the seventh P-type transistor PM7 is connected to the gate of the eighth P-type transistor PM8, the drain of the seventeenth P-type transistor NM17, and the drain of the nineteenth N-type transistor NM19;

The drain of the eighth P-type transistor PM8 is connected to the drain of the twenty-fifth N-type transistor NM25, the input end of the first transfer transistor TG1, and the input end of the second transfer transistor TG2;

The source of the sixteenth N-type transistor NM16 is connected to the source of the seventeenth N-type transistor NM17 and the drain of the twentieth N-type transistor NM20;

The source of the eighteenth N-type transistor NM18 is connected to the source of the nineteenth N-type transistor NM19 and the drain of the twenty-first N-type transistor NM21;

The gate of the twentieth N-type transistor NM20 is connected to the second external pulse signal V _pre , and the source NM20 of the twentieth N-type transistor is connected to the drain of the twenty-third N-type transistor NM23;

The gate of the twenty-first N-type transistor NM21 is connected to the first external pulse signal V _post , and the source of the twenty-first N-type transistor NM21 is connected to the drain of the twenty-fourth N-type transistor NM24;

The gate of the twenty-third N-type transistor NM23 is connected to the gate of the twenty-fourth N-type transistor NM24 and the fourth bias voltage V _tail that controls the size of the OTA tail current;

The sources of the twenty-second to twenty-fifth N-type transistors are connected to the external ground signal GND;

The anode of the first transmission tube TG1 is connected to the second external pulse signal V _post , the negative pole of the first transmission tube TG1 is connected to the inversion signal V _post~ of the second external pulse signal, and the output of the first transmission tube TG1 is connected to the second transmission The output of the tube TG2 is connected to the first pole of the storage capacitor C _W ;

The anode of the second transmission tube TG2 is connected to the first external pulse signal _Vpre , and the negative pole of the second transmission tube TG2 is connected to the inversion signal Vpre _~ of the first external pulse signal;

The second pole of the storage capacitor C _w is connected to the external ground signal GND.

In another embodiment of the present invention, a method for implementing a multimodal synaptic time-dependent plasticity algorithm based on any of the circuit embodiments of the above-mentioned multimodal synaptic time-dependent plasticity algorithm is provided. The method is based on the foregoing embodiments The circuit implementation in. Therefore, the descriptions and definitions in the various embodiments of the circuit of the aforementioned multimodal synaptic time-dependent plasticity algorithm can be used to understand the various execution steps in the embodiments of the present invention. Fig. 5 is a schematic flow chart of the implementation method of the multimodal synapse time-dependent plasticity algorithm provided by the embodiment of the present invention. Window sampling voltage;

Wherein, the OTA synaptic circuit is an OTA-based synaptic circuit. The time window generation circuit can generate various time window sampling voltages under the action of the first control signal V _CTR1 and the applied voltage, and outputs the time window sampling voltages in the preset mode each time. The preset mode is a preset mode, corresponding to the type of the time window sampling voltage one by one.

S502, based on the switch switching circuit, is used to switch the input port of the OTA synaptic circuit connected to the time window sampling voltage and the external reference voltage;

The switch switching circuit is used to determine the connection mode between the time window sampling voltage and the external reference voltage and different input ports of the OTA synapse circuit, so as to realize the corresponding multimodal synaptic time-dependent plasticity algorithm.

S503, based on the OTA synapse circuit, when the first external pulse signal and the second external pulse signal arrive, the change amount of the synapse weight value under the action of the time window sampling voltage and the external reference voltage is calculated, and the change amount is expressed in the form of charge Stored on the storage capacitor connected to the output port of the OTA synapse circuit.

In this embodiment, after the time window generation circuit is started, the generated time window sampling voltage will be sent to the input port of the OTA synapse circuit through the switch selection circuit. The OTA synaptic circuit will calculate the magnitude of the output current according to the different voltage differences of its input port, and store it in the form of charge on the storage capacitor connected to its output port, and then change the voltage on the storage capacitor, that is, the size of the synaptic weight .

In this embodiment, by adjusting the control signal, the time window generation circuit is controlled to generate multiple time window sampling voltages, and by switching the input port of the OTA synapse circuit connected to the time window sampling voltage and the external reference voltage, the OTA synapse circuit is In different switching situations, the change of synaptic weight is determined according to the voltage difference of the input port, thereby realizing a variety of synaptic time-dependent plasticity algorithms; and the time scale and gain range of the algorithm can be adjusted by adjusting the applied voltage, which is suitable for large Scale spiking neural network, simple to implement and flexible to adjust.

On the basis of the above-mentioned embodiments, the step of generating multiple time-window sampling voltages under the action of the first control signal and the applied voltage based on the time-window generation circuit in this embodiment includes: at the moment when the first external pulse signal V _pre arrives , so that the first capacitor C ₁ and the second capacitor C ₂ are charged to the peak value; the second capacitor C ₂ generates a return signal under the action of the third bias voltage V _blk2 , the first control signal V _CTR1 and its complementary signal V _CTR1B The signal of port V _back ;

Make the first capacitor C ₁ generate a preset window waveform under the action of the first bias voltage V _bin , the second bias voltage V _blk and the return signal port V _back , and generate a preset window waveform under the action of the second external pulse signal V _post and its Under the action of the reverse signal V _post˜ , the time window sampling voltage is output, such as the time window sampling voltage of 50 ns, and then output to the input terminal of the switch switching circuit 20 .

On the basis of the above-mentioned embodiments, in this embodiment, the step of generating multiple time-window sampling voltages under the action of the first control signal and the applied voltage based on the time-window generating circuit includes: when the first control signal V _CTR1 is at a low level , when returning to the high level of the signal of the signal port _Vback , the second P-type transistor PM2 in the time window generation circuit 10 is turned off, and the second N-type transistor NM2 in the time window generation circuit 10 is turned on, so that the first capacitor _C1 Under the control of the second bias voltage V _blk , the voltage on the voltage gradually decreases until it is equal to the second common reference voltage VCM2;

When the first control signal V _CTR1 is at a high level, the voltage on the second capacitor _C2 is connected to the positive input port of the comparator Compare in the time window generation circuit 10, and the second capacitor _C2 is at the third bias voltage V _blk2 Gradually decrease under the control of until it is equal to the first common reference voltage VCM1;

When the voltage on the second capacitor _C2 is higher than the external reference voltage V _C of the negative input port of the comparator Compare, the comparator outputs a high level, and the signal returned to the signal port V _back is also a high level, and it is turned off at this time The second P-type transistor PM2 turns on the second N-type transistor NM2, so that the voltage of _C1 on the first capacitor gradually decreases under the control of the second bias voltage V _blk until the voltage on the first capacitor _C1 is less than V _C , at this time the comparator Compare outputs a low level, returns to the signal port, the signal of V _back becomes low level, turns on the second P-type transistor PM2, and turns off the second N-type transistor NM2, so that the first capacitor _C1 The voltage gradually rises under the control of the first bias voltage V _bin until it is equal to the fourth common reference voltage VCM4 .

On the basis of the above-mentioned embodiments, the step of switching the input port of the OTA synapse circuit 30 connected to the time window sampling voltage and the external reference voltage based on the switch switching circuit 20 in this embodiment includes: making the fourth switch in the switch switching circuit 20 The P-type transistor PM4 and the fifteenth N-type transistor NM15 select different external reference voltages connected to the port V _REF of the external reference voltage under the control of the third control signal V _CTR3 ; make the eleventh to fourteenth N-type transistors The time window sampling voltage and the external reference voltage connected to each input port of the OTA synapse circuit 30 are selected under the control of the second control signal V _CTR2 and its complementary signal V _{CTR2 ˜} .

On the basis of the above-mentioned embodiments, the step of switching the input port of the OTA synapse circuit 30 connected to the time window sampling voltage and the external reference voltage based on the switch switching circuit 20 in this embodiment includes: when the third control signal V _CTR3 is low level, the fourth P-type transistor PM4 is turned on, the fifteenth N-type transistor NM15 is turned off, and the port V _REF of the external reference voltage is connected to the fourth common reference voltage VCM4;

When the third control signal V _CTR3 is at a high level, the fourth P-type transistor PM4 is turned off, the fifteenth N-type transistor NM15 is turned on, and the port V _REF of the external reference voltage is connected to the third common reference voltage VCM3;

When the second control signal V _CTR2 is at low level and the complementary signal V _CTR2~ of the second control signal is at high level, the thirteenth to fourteenth N-type transistors are turned on, and the eleventh to twelfth N-type transistors are turned off. type transistor, the port V _REF of the external reference voltage is connected to the positive input port OTAP of the OTA synapse circuit 30, and the output port V _edcp of the time window sampling voltage is connected to the negative input port OTAN of the OTA synapse circuit 30;

When the second control signal V _CTR2 is at a high level and the complementary signal V _CTR2~ of the second control signal is at a low level, the thirteenth to fourteenth N-type transistors are turned off, and the eleventh to twelfth N-type transistors are turned on. type transistor, the port V _REF of the external reference voltage is connected to the negative input port OTAN of the OTA synapse circuit 30, and the output port V _edcp of the time window sampling voltage is connected to the positive input port OTAP of the OTA synapse circuit 30;

Wherein, the external reference voltage includes a third common reference voltage and a fourth common reference voltage.

On the basis of the above-mentioned embodiments, in this embodiment, when the first external pulse signal V _pre and the second external pulse signal V _post arrive based on the OTA synaptic circuit 30, under the action of the time window sampling voltage and the external reference voltage The step of changing the amount of synapse weight includes: when the first external pulse signal V _pre arrives earlier than the second external pulse signal V _post , according to the sixteenth N-type transistor NM16 and the seventeenth N-type transistor NM16 in the OTA synapse circuit 30 The positive and negative and the size of the voltage difference on the gate of the type transistor NM17 determine the positive and negative and the size of the current output by the OTA synapse circuit 30, and determine the variation of the synaptic weight according to the positive and negative of the current and the size;

When the first external pulse signal V _pre arrives later than the second external pulse signal V _post , according to the positive voltage difference between the gates of the eighteenth N-type transistor NM18 and the nineteenth N-type transistor NM19 in the OTA synapse circuit 30 Negative and magnitude, determine the positive and negative sum of the current output by the OTA synapse circuit 30, and determine the change amount of the synaptic weight according to the positive and negative sum of the current.

On the basis of the above-mentioned embodiments, in this embodiment, the OTA synapse is determined according to the positive and negative sum of the voltage difference between the gates of the sixteenth N-type transistor NM16 and the seventeenth N-type transistor NM17 in the OTA synapse circuit 30. The steps of the positive, negative and magnitude of the current output by the circuit 30 include: when the first external pulse signal V _pre arrives earlier than the second external pulse signal V _post , when the voltage on the gate of the seventeenth N-type transistor NM17 When it is greater than the voltage on the gate of the sixteenth N-type transistor NM16, at the moment when the second external pulse signal V _pos arrives, the OTA synapse circuit 30 outputs a positive current to the storage capacitor C _W through the first transmission transistor TG1, The synapse weight increases; when the voltage on the gate of the seventeenth N-type transistor NM17 is less than the voltage on the gate of the sixteenth N-type transistor NM16, at the moment when the second external pulse signal V _post arrives, the OTA burst The touch circuit 30 outputs a negative current to the storage capacitor C _W through the first transmission tube TG1, and the synapse weight decreases;

According to the positive and negative sum of the voltage difference between the gates of the eighteenth N-type transistor and the nineteenth N-type transistor in the OTA synapse circuit 30, the step of determining the positive and negative sum of the current output by the OTA synapse circuit includes: When the first external pulse signal _Vpre arrives later than the second external pulse signal _Vpost , when the voltage on the gate of the nineteenth N-type transistor NM19 is greater than the voltage on the gate of the eighteenth N-type transistor NM18, At the moment when the first external pulse signal V _pre arrives, the OTA synaptic circuit 30 outputs a positive current to the storage capacitor C _W through the second transmission tube TG2, and the synaptic weight increases; when the gate of the nineteenth N-type transistor NM19 When the voltage on the gate of the eighteenth N-type transistor NM18 is less than the voltage on the gate of the eighteenth N-type transistor NM18, at the moment when the first external pulse signal V _pre arrives, the OTA synapse circuit 30 outputs a negative direction to the storage capacitor C _W through the second transmission transistor TG2 current, the synaptic weight decreases.

In this embodiment, the first control signal V _CTR1 is respectively applied to the gates of the seventh N-type transistor NM7, the tenth N-type transistor NM10, and the third P-type transistor PM3 in the time window generating circuit 10; The complementary signal V _{CTR1 ˜} is applied to the gate of the eighth N-type transistor NM8 in the time window generation circuit 10 . The second control signal V _CTR2 is respectively applied to the gates of the eleventh N-type transistor NM11 and the twelfth N-type transistor NM2 in the switch switching circuit 20; the complementary signal V _CTR2~ of the second control signal is applied to the switch switch Gates of the thirteenth N-type transistor NM13 and the fourteenth N-type transistor NM14 in the circuit 20 . The third control signal V _CTR3 is respectively applied to the gates of the fourth P-type transistor PM4 and the fifteenth N-type transistor NM15 in the switching circuit 20 . Symmetrical signals V _CTR1B , V _CTR2B , V _CTR3B and their complementary signals of the first to third control signals are respectively applied to corresponding positions of the Δt<0 circuit part symmetrical to the Δt>0 circuit part in FIG. 1 .

In this embodiment, each control signal has its specific meaning. The first control signal V _CTR1 determines the window type output by the time window generating circuit 10 . The second control signal V _CTR2 and the third control signal V _CTR3 determine the direction of weight updating and the reference voltage of the input port of the OTA synapse circuit 30 . Specifically, when the first control signal V _CTR1 is at a low level, the time window generating circuit 10 outputs a window voltage of an exponentially falling waveform; when the first control signal V _CTR1 is at a high level, the time window generating circuit 10 outputs a waveform with a return characteristic window voltage. When the second control voltage V _CTR2 is at a high level, if the time window voltage is sampled and the voltage output on the output port V _edcp is greater than the reference voltage determined by V _CTR3 , the weight update direction is positive; if the time window voltage is sampled at If the voltage output on the output port V _edcp is lower than the reference voltage determined by V _CTR3 , the weight updating direction is negative. When the second control voltage V _CTR2 is at a low level, if the time window voltage is sampled and the voltage output on the output port V _edcp is greater than the reference voltage determined by V _CTR3 , the weight update direction is negative; if the time window voltage is sampled at If the voltage output from the output port V _edcp is lower than the reference voltage determined by V _CTR3 , the weight update direction is positive. When the third control signal V _CTR3 is at a high level, the voltage at the input port of the OTA synapse circuit is the third common reference voltage VCM3, which is always smaller than the voltage output on the output port V _edcp by sampling the time window voltage, and the synapse is updated as Single direction, the specific direction is determined according to the above description. When the third control signal V _CTR3 is at a low level, the voltage at the input port of the OTA synaptic circuit is the fourth common reference voltage VCM4, which is within the range of the voltage value output on the output port V _edcp after the time window voltage is sampled, and the synaptic Updates can be both positive and negative, and the specific direction is determined by the above description. The functions of the symmetrical signals V _CTR1B , V _CTR2B , and V _CTR3B of the first to third control signals are the same as those of the first to third control signals described above. Table 1 shows eight combinations of the first to third control signals and their symmetry signals, which can realize eight types of synaptic plasticity algorithms.

Table 1 Eight combinations of the first to third control signals and their symmetrical signals

serial number <![CDATA[V_CTR1]]> <![CDATA[V_CTR2]]> <![CDATA[V_CTR3]]> <![CDATA[V_CTR1B]]> <![CDATA[V_CTR2B]]> <![CDATA[V_CTR3B]]> 1 0 1 1 0 0 1 2 1 1 0 1 1 0 3 0 1 0 0 1 0 4 0 0 1 0 0 1 5 0 0 1 0 1 1 6 0 1 0 0 1 1

7 1 1 0 0 0 1 8 0 1 1 0 1 1

Let the first control signal V _CTR1 and the symmetrical signal V _CTR1B of the first control signal be low level, the second control signal V _CTR2 be high level, the symmetrical signal V _CTR2B of the second control signal be low level, and the third control signal The signal V _CTR3 and the symmetrical signal of the third control signal are at high level to realize the learning algorithm shown in FIG. 6 . The abscissa is Δt, and the ordinate is the variation of synaptic weights.

In this embodiment, when the first control signal V _CTR1 and its symmetry signal V _CTR1B are at low level, the time window generating circuit 10 and its symmetry circuit both output a window voltage of an exponentially decreasing waveform. The second control signal V _CTR2 is high level, the symmetrical signal V _CTR2B of the second control signal is low level, and the voltage output port V _edcp and its symmetrical port V _edcpB after the time window voltage is sampled are respectively connected to the OTA synapse circuit 30's first positive input port OTAP and second negative input port OTANB. The port V _REF of the external reference voltage and its symmetrical port V _REFB are respectively connected to the first negative input port OTAN and the second positive input port OTAPB of the OTA synapse circuit 30 . Both the third control signal V _CTR3 and its symmetrical signal V _CTR3B are at high level, and the port V _REF of the external reference voltage and its symmetrical port V _REFB are both connected to the third common reference voltage VCM3 . At this time, when the first pulse signal V _pre arrives before the second pulse signal V _post , that is, Δt>0, the synaptic weight update direction is positive, and the smaller the time difference Δt between the two, the synaptic weight update The larger the amplitude is; when the first pulse signal V _pre arrives after the second pulse signal V _post , that is, in the case of Δt<0, the synaptic weight update direction is negative, and the smaller the time difference t between the two, the greater the weight update range. large, as shown in Figure 6.

Make the first control signal V _CTR1 and the symmetry signal V _CTR1B of the first control signal high, the second control signal V _CTR2 and the symmetry signal V _CTR2B of the second control signal are low, and the third control signal V _CTR3 and The symmetrical signal V _CTR3B of the third control signal is at a low level to implement the learning algorithm shown in FIG. 7 .

In this embodiment, the first control signal V _CTR1 and its symmetry signal V _CTR1B are at high level, then the time window generating circuit 10 and its symmetry circuit both output a window voltage with a return characteristic waveform. The second control signal V _CTR2 and its symmetrical signal V _CTR2B are at high level, and the voltage output port V _edcp and its symmetrical port V _edcpB after the time window voltage is sampled are respectively connected to the first positive input port OTAP of the OTA synapse circuit 30 , the second positive input port OTAPB. The port V _REF of the external reference voltage and its symmetrical port V _REFB are respectively connected to the first negative input port OTAN and the second negative input port OTANB. Both the third control signal V _CTR3 and its symmetrical signal V _CTR3B are at low level, and the port V _REF of the external reference voltage and its symmetrical port V _REFB are both connected to the fourth common reference voltage VCM4 . At this time, when the first pulse signal V _pre arrives before the second pulse signal V _post , that is, Δt>0, if the voltage on the first positive input port OTAP of the OTA synapse circuit 30 is greater than that of the OTA synapse circuit 30 The voltage on the first negative input port OTAN of , the synaptic weight update direction is positive, otherwise it is negative, and the greater the difference between the two, the greater the weight update range. When the first pulse signal V _pre arrives after the second pulse signal V _post , that is, in the case of Δt<0, if the voltage on the second positive input port OTAPB is greater than the voltage on the second negative input port OTANB, the synaptic weight The update direction is positive, otherwise it is negative, and the greater the difference between the two, the greater the weight update range, as shown in Figure 7.

Make the first control signal V _CTR1 and the symmetry signal V _CTR1B of the first control signal low, the second control signal V _CTR2 and the symmetry signal V _CTR2B of the second control signal are high, and the third control signal V _CTR3 and The symmetrical signal V _CTR3B of the third control signal is at a low level to implement the learning algorithm shown in FIG. 8 .

In this embodiment, when the first control signal V _CTR1 and its symmetry signal V _CTR1B are at low level, the time window generating circuit 10 and its symmetry circuit both output a window voltage of an exponentially decreasing waveform. The second control signal V _CTR2 and its symmetrical signal V _CTR2B are at high level, and the voltage output port V _edcp and its symmetrical port V _edcpB after the time window voltage is sampled are respectively connected to the first positive input port OTAP of the OTA synapse circuit 30 , the second positive input port OTAPB, the external reference voltage port V _REF and its symmetrical port V _CREFB are respectively connected to the first negative input port OTAN and the second negative input port OTANB of the OTA synapse circuit 30 . Both the third control signal V _CTR3 and its symmetrical signal V _CTR3B are at low level, and the port V _REF of the external reference voltage and its symmetrical port V _REFB are both connected to the fourth common reference voltage VCM4 . At this time, when the first pulse signal V _pre arrives before the second pulse signal V _post , that is, Δt>0, if the voltage on the first positive input port OTAP is greater than the voltage on the first negative input port OTAN, the burst The update direction of the weight value is positive, otherwise it is negative, and the greater the difference between the two, the greater the update range of the weight value. When the first pulse signal V _pre arrives after the second pulse signal V _post , that is, in the case of Δt<0, if the voltage on the second positive input port OTAP is greater than the voltage on the second negative input port OTAN, the synaptic weight The update direction is positive, otherwise it is negative, and the greater the difference between the two, the greater the weight update range, as shown in Figure 8.

Make the first control signal V _CTR1 and the symmetry signal V _CTR1B of the first control signal low, the second control signal V _CTR2 and the symmetry signal V _CTR2B of the second control signal are low, and the third control signal V _CTR3 and The symmetrical signal V _CTR3B of the third control signal is at a high level to implement the learning algorithm shown in FIG. 9 .

In this embodiment, when the first control signal V _CTR1 and its symmetry signal V _CTR1B are at low level, the time window generating circuit 10 and its symmetry circuit both output a window voltage of an exponentially decreasing waveform. The second control signal V _CTR2 and its symmetrical signal V _CTR2B are at low level, and the voltage output port V _edcp and its symmetrical port V _edcpB after the time window voltage is sampled are respectively connected to the first negative input port OTAN of the OTA synaptic circuit 30 , The second negative input short even OTANB. The port V _REF of the external reference voltage and its symmetrical port V _REFB are respectively connected to the first positive input port OTAP and the second positive input port OTAPB of the OTA synapse circuit 30 . Both the third control signal V _CTR3 and its symmetrical signal V _CTR3B are at high level, and the port V _REF of the external reference voltage and its symmetrical port V _REFB are both connected to the third common reference voltage VCM3 . At this time, when the first pulse signal V _pre arrives before the second pulse signal V _post , that is, Δt>0 or comes after the first pulse signal V _pre , that is, when the second pulse signal V _post arrives, that is, Δt<0, The update direction of synaptic weights is negative, and the larger the time difference Δt, the larger the update range of the weights, as shown in Figure 9.

Let the first control signal V _CTR1 and the symmetrical signal V _CTR1B of the first control signal be at low level, the second control signal V _CTR2 be at low level, the symmetrical signal V CTR2B of the second control signal be at high level, and the third control signal V _CTR2B be at high level. The signal V _CTR3 and the symmetry signal V _CTR3B of the third control signal are at high level to implement the learning algorithm shown in FIG. 10 .

In this embodiment, when the first control signal V _CTR1 and its symmetry signal V _CTR1B are at low level, the time window generating circuit 10 and its symmetry circuit both output a window voltage of an exponentially decreasing waveform. The second control signal V _CTR2 is low level, the symmetrical signal V _CTR2B of the second control signal is high level, and the voltage output port V _edcp and its symmetrical port V _edcpB after the time window voltage is sampled are respectively connected to the OTA synapse circuit 30 of the first negative input port OTAN, the second positive input port OTAPB. The port V _REF of the external reference voltage and the symmetrical port V _REFB are respectively connected to the first positive input port OTAP and the second negative input port OTANB of the OTA synapse circuit 30 . Both the third control signal V _CTR3 and its symmetrical signal V _CTR3B are at high level, and the port V _REF of the external reference voltage and its symmetrical port V _REFB are both connected to the third common reference voltage VCM3 . At this time, when the first pulse signal V _pre arrives before the second pulse signal V _post , that is, Δt>0, the update direction of synaptic weights is negative, and the smaller the time difference Δt between the two, the larger the weight update range ; When the second pulse signal V _post arrives after the first pulse signal V _pre , that is, in the case of Δt<0, the synaptic weight update direction is positive, and the smaller the time difference Δt between the two, the larger the weight update range, as shown in Figure 10 shows.

Make the first control signal V _CTR1 and the symmetry signal V _CTR1B of the first control signal low, the second control signal V _CTR2 and the symmetry signal V _CTR2B of the second control signal are high, and the third control signal V _CTR3 is low level, and the symmetrical signal V _CTR3B of the third control signal is high level, realizing the learning algorithm shown in FIG. 11 .

In this embodiment, when the first control signal V _CTR1 and its symmetry signal V _CTR1B are at low level, the time window generating circuit 10 and its symmetry circuit both output a window voltage of an exponentially decreasing waveform. The second control signal V _CTR2 and its symmetrical signal V _CTR2B are at high level, and the voltage output port V _edcp and its symmetrical port V _edcpB after the time window voltage is sampled are respectively connected to the first positive input port OTAP of the OTA synapse circuit 30 , the second positive input port OTAPB. The port V _REF of the external reference voltage and its symmetrical port V _REFB are respectively connected to the first negative input port OTAP and the second negative input port OTAPB of the OTA synapse circuit 30 . The third control signal V _CTR3 is low level, the symmetrical signal V _CTR3B of the third control signal is high level, the port V _REF of the external reference voltage and its symmetrical port V _REFB are connected with the fourth common reference voltage VCM4 and the third common reference voltage VCM4 respectively. Reference voltage VCM3 connection. At this time, when the first pulse signal V _pre arrives before the second pulse signal V _post , that is, Δt>0, if the voltage on the first positive input port OTAP is greater than the voltage on the first negative input port OTAN, then The update direction of the synaptic weight is positive, otherwise it is negative, and the smaller the time difference Δt between the two is, the larger the update range of the weight is. When the first pulse signal V _pre comes after the second pulse signal V _post , that is, in the case of Δt<0, the synaptic weight update direction is positive, and the smaller the time difference Δt between the two, the larger the weight update range, as shown in the figure 11.

Let the first control signal V _CTR1 be high level, the symmetrical signal V _CTR1B of the first control signal be low level, the second control signal V _CTR2 be high level, and the symmetrical signal V _CTR2B of the second control signal be low level , the third control signal V _CTR3 is at low level, and the symmetrical signal V _CTR3B of the third control signal is at high level, so as to realize the learning algorithm shown in FIG. 12 .

In this embodiment, the first control signal V _CTR1 is at a high level, and the symmetrical signal V _CTR1B of the first control signal is at a low level, then the time window generating circuit 10 and its symmetrical circuit respectively output window voltages with return characteristic waveforms and the window voltage of the exponentially falling waveform. The second control signal V _CTR2 is high level, the symmetrical signal V _CTR2B of the second control signal is low level, and the voltage output port V _edcp and its symmetrical port V _edcpB after the time window voltage is sampled are respectively connected to the OTA synapse circuit 30 positive input port OTAP, negative input port OTANB. The port V _REF of the external reference voltage and its symmetrical port V _REFB are respectively connected to the first negative input port OTAN and the second positive input port OTAPB of the OTA synapse circuit 30 . The third control signal V _CTR3 is low level, the symmetrical signal V _CTR3B of the third control signal is high level, the port V _REF of the external reference voltage and its symmetrical port V _REFB are connected with the fourth common reference voltage VCM4 and the third common reference voltage VCM4 respectively. Reference voltage VCM3 connection. At this time, when the first pulse signal V _pre arrives before the second pulse signal V _post , that is, Δt>0, if the voltage on the first positive input port OTAP is greater than the voltage on the first negative input port OTAN, then The update direction of the synaptic weight is positive, otherwise it is negative, and the smaller the time difference Δt between the two is, the larger the update range of the weight is. When the first pulse signal V _pre arrives after the second pulse signal V _post , that is, in the case of Δt<0, the update direction of the synaptic weight is negative, and the smaller the time difference Δt between the two, the larger the weight update range, as shown in the figure 12 shown.

Make the first control signal V _CTR1 and the symmetry signal V _CTR1B of the first control signal low, the second control signal V _CTR2 and the symmetry signal V _CTR2B of the second control signal are high, and the third control signal V _CTR3 and The symmetry signal V _CTR3B of the third control signal is at a high level to implement the learning algorithm shown in FIG. 13 .

In this embodiment, when the first control signal V _CTR1 and its symmetry signal V _CTR1B are at low level, the time window generating circuit 10 and its symmetry circuit both output a window voltage of an exponentially decreasing waveform. The second control signal V _CTR2 and its symmetrical signal V _CTR2B are at high level, and the voltage output port V _edcp and its symmetrical port V _edcpB after the time window voltage is sampled are respectively connected to the positive input port OTAP, the positive input port of the OTA synapse circuit 30 Input port OTAPB. The port V _REF of the external reference voltage and its symmetrical port V _REFB are respectively connected to the first negative input port OTAN and the second negative input port OTANB of the OTA synapse circuit 30 . The third control signal V _CTR3 and its symmetrical signal V _CTR3B are at high level, and the port V _REF of the external reference voltage and its symmetrical port V _REFB are connected to the third common reference voltage VCM3 . At this time, when the first pulse signal V _pre arrives before the second pulse signal V _post , that is, Δt>0 or comes after the first pulse signal V _pre , that is, when the second pulse signal V _post arrives, that is, Δt<0, The direction of synaptic weight update is positive, and the smaller the time difference Δt between the two is, the larger the weight update range is, as shown in Figure 13.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims (9)

1. A circuit of a multi-modal synaptic time-dependent plasticity algorithm, comprising a time window generating circuit, a switching circuit, an OTA synaptic circuit, a symmetrical circuit of the time window generating circuit and a symmetrical circuit of the switching circuit;

the time window generating circuit is used for outputting time window sampling voltage under the action of the first control signal and the external voltage;

the switch switching circuit is used for switching an input port of the OTA synaptic circuit connected with the time window sampling voltage and an external reference voltage;

the OTA synaptic circuit is used for calculating the variation of synaptic weight under the action of the sampling voltage of the time window and the external reference voltage when the first external pulse signal and the second external pulse signal arrive, and storing the variation in the form of charge on a storage capacitor connected with an output port of the OTA synaptic circuit;

The OTA protruding circuit comprises fifth to eighth P-type transistors, sixteenth to twenty-fifth N-type transistors, a first transmission tube, a second transmission tube and a storage capacitor;

the sources of the fifth to eighth P-type transistors are connected with an external power supply voltage;

the grid electrode of the fifth P type transistor is connected with the grid electrode of the sixth P type transistor, the drain electrode of the sixteenth N type transistor and the drain electrode of the eighteenth N type transistor, and the drain electrode of the fifth P type transistor is connected with the drain electrode and the grid electrode of the twenty second N type transistor and the grid electrode of the twenty fifth N type transistor;

the grid electrode of the seventh P type transistor is connected with the grid electrode of the eighth P type transistor, the drain electrode of the seventeenth P type transistor and the drain electrode of the nineteenth N type transistor;

the drain electrode of the eighth P-type transistor is connected with the drain electrode of the twenty-fifth N-type transistor, the input end of the first transmission tube and the input end of the second transmission tube;

a source of the sixteenth N-type transistor is connected to a source of the seventeenth N-type transistor and a drain of the twentieth N-type transistor;

the source electrode of the eighteenth N-type transistor is connected with the source electrode of the nineteenth N-type transistor and the drain electrode of the twenty first N-type transistor;

the grid electrode of the twenty-N type transistor is connected with a second external pulse signal, and the source electrode of the twenty-N type transistor is connected with the drain electrode of the twenty-third N type transistor;

The grid electrode of the twenty-first N-type transistor is connected with a first external pulse signal, and the source electrode of the twenty-first N-type transistor is connected with the drain electrode of the twenty-fourth N-type transistor;

the grid electrode of the twenty-third N-type transistor is connected with the grid electrode of the twenty-fourth N-type transistor and a fourth bias voltage;

the source electrode of the twenty-second to twenty-fifth N-type transistor is connected with an external ground signal;

the positive electrode of the first transmission tube is connected with the second external pulse signal, the negative electrode of the first transmission tube is connected with the inverting signal of the second external pulse signal, and the output of the first transmission tube is connected with the output of the second transmission tube and the first electrode of the storage capacitor;

the positive electrode of the second transmission tube is connected with the first external pulse signal, and the negative electrode of the second transmission tube is connected with the inverting signal of the first external pulse signal;

the second pole of the storage capacitor is in signal connection with the external ground.

2. The circuit of the multi-modal synaptic time-dependent plasticity algorithm as claimed in claim 1, wherein the time window generating circuit comprises first to tenth N-type transistors, first to third P-type transistors, first capacitor, second capacitor and comparator;

The source electrode of the first P-type transistor is connected with a port of a fourth common reference voltage, the grid electrode of the first P-type transistor is connected with a first bias voltage for controlling charging current, and the drain electrode of the first P-type transistor is connected with the source electrode of the second P-type transistor;

the grid electrode of the second P-type transistor is connected with the grid electrode of the second N-type transistor and the return signal port, and the drain electrode of the second P-type transistor is connected with the drain electrode of the second N-type transistor, the source electrode of the first N-type transistor, the drain electrode of the sixth N-type transistor and the first electrode of the first capacitor;

the source electrode of the third P-type transistor is connected with an external power supply voltage, and the grid electrode of the third P-type transistor is connected with the grid electrode of the tenth N-type transistor, the return signal port and the first control signal;

the drain electrode of the first N-type transistor is connected with the external power supply voltage, and the grid electrode of the first N-type transistor is connected with the first external pulse signal;

the source electrode of the second N-type transistor is connected with the drain electrode of the third N-type transistor;

the grid electrode of the third N-type transistor is connected with a second bias voltage for controlling leakage current, and the source electrode of the third N-type transistor is connected with a second pole of the first capacitor and a second common reference voltage;

The drain electrode of the fourth N-type transistor is connected with the external power supply voltage, the grid electrode of the fourth N-type transistor is connected with the first external pulse signal, and the source electrode of the fourth N-type transistor is connected with the drain electrode of the fifth N-type transistor, the first electrode of the second capacitor and the source electrode of the seventh N-type transistor;

the grid electrode of the fifth N-type transistor is connected with a third bias voltage for controlling leakage current, and the source electrode of the fifth N-type transistor is connected with a second electrode of the second capacitor and a first common reference voltage;

the grid electrode of the sixth N-type transistor is connected with the second external pulse signal, and the source electrode of the sixth N-type transistor is connected with the source electrode of the ninth N-type transistor and the output port of the time window sampling voltage;

the grid electrode of the seventh N-type transistor is connected with the first control signal voltage, and the drain electrode of the seventh N-type transistor is connected with the drain electrode of the eighth N-type transistor and the positive electrode of the comparator;

the grid electrode of the eighth N-type transistor is connected with the inverting signal of the first control signal, and the source electrode of the eighth N-type transistor is connected with an external ground signal;

the drain electrode of the ninth N-type transistor is connected with the port of the external reference voltage, and the grid electrode of the ninth N-type transistor is connected with the inverting signal of the second external pulse signal;

The drain electrode of the tenth N-type transistor is connected with the output end of the comparator;

the negative electrode input port of the comparator is connected with an external reference voltage of the comparator;

the external voltage comprises a first bias voltage, a second bias voltage and a third bias voltage;

the return signal port is used for returning signals generated by the second capacitor under the action of the third bias voltage, the first control signal and complementary signals of the first control signal.

3. The circuit of the multi-modal synaptic time-dependent plasticity algorithm as claimed in claim 1, wherein the switching circuit comprises a fourth P-type transistor and eleventh to fifteenth N-type transistors;

the drain electrode of the fourth P-type transistor is connected with the source electrode of the fifteenth N-type transistor and a port of external reference voltage, the grid electrode of the fourth P-type transistor is connected with the grid electrode of the fifteenth N-type transistor and a third control signal, and the source electrode of the fourth P-type transistor is connected with a fourth common reference voltage;

the grid electrode of the eleventh N-type transistor is connected with the grid electrode of the twelfth N-type transistor and the second control signal, the drain electrode of the eleventh N-type transistor is connected with the drain electrode of the fourteenth N-type transistor and the output port of the time window sampling voltage in the time window generating circuit, and the source electrode of the eleventh N-type transistor is connected with the source electrode of the thirteenth N-type transistor and the first positive input port of the OTA synaptic circuit;

A drain of a twelfth N-type transistor is connected to the drain of the thirteenth N-type transistor and to a port of an external reference voltage, a source of the twelfth N-type transistor is connected to a source of the fourteenth N-type transistor and to a first negative input port of the OTA synaptic circuit;

the grid electrode of the thirteenth N-type transistor is connected with the grid electrode of the fourteenth N-type transistor and the inverting signal of the second control signal;

the drain electrode of the fifteenth N-type transistor is connected with a third common reference voltage.

4. A method of implementing a multi-modal synaptic time-dependent plasticity algorithm based on the circuitry of any one of claims 1-3, comprising:

the time window based generation circuit generates various time window sampling voltages under the action of the first control signal and the external voltage;

the OTA synaptic circuit is used for switching an input port of the OTA synaptic circuit connected with the time window sampling voltage and an external reference voltage based on a switch switching circuit;

when the first external pulse signal and the second external pulse signal arrive, the change quantity of the synaptic weight under the action of the sampling voltage of the time window and the external reference voltage is calculated based on an OTA synaptic circuit, and the change quantity is stored in a storage capacitor connected with an output port of the OTA synaptic circuit in a form of electric charge.

5. The method of claim 4, wherein the step of generating a plurality of time window sampling voltages based on the time window generating circuit under the action of the first control signal and the applied voltage comprises:

charging the first capacitor and the second capacitor to peak values at the instant when the first external pulse signal arrives;

the second capacitor generates a signal of a return signal port under the action of a third bias voltage, a first control signal and a complementary signal of the first control signal;

the first capacitor generates window waveforms under the action of a first bias voltage, a second bias voltage and a return signal port, and outputs time window sampling voltages under the action of the second external pulse signals and the inverted signals of the second external pulse signals.

6. The method of claim 5, wherein the step of generating a plurality of time window sampling voltages based on the time window generating circuit under the action of the first control signal and the applied voltage comprises:

when the first control signal is in a low level and the signal of the return signal port is in a high level, turning off a second P-type transistor in the time window generating circuit, and turning on a second N-type transistor in the time window generating circuit, so that the voltage on the first capacitor gradually drops under the control of the second bias voltage until the voltage is equal to a second common reference voltage;

When the first control signal is at a high level, the voltage on the second capacitor is connected with the positive electrode input port of the comparator in the time window generating circuit, and the second capacitor gradually drops under the control of the third bias voltage until the second capacitor is equal to the first common reference voltage;

when the voltage on the second capacitor is higher than the external reference voltage of the negative input port of the comparator, the comparator outputs a high level, the signal of the return signal port is also high level, the second P-type transistor is turned off, the second N-type transistor is turned on, the voltage on the first capacitor gradually drops under the control of the second bias voltage until the voltage on the first capacitor is smaller than the external reference voltage of the negative input port of the comparator, the comparator outputs a low level, the signal of the return signal port becomes low level, the second P-type transistor is turned on, the second N-type transistor is turned off, and the voltage on the first capacitor gradually rises under the control of the first bias voltage until the voltage is equal to a fourth common reference voltage.

7. The method of claim 4, wherein switching the input port of the OTA synaptic circuit connected to the time window sampling voltage and an external reference voltage based on a switch switching circuit comprises:

The fourth P-type transistor and the fifteenth N-type transistor in the switch switching circuit select an external reference voltage connected with a port of the external reference voltage under the control of a third control signal;

the eleventh through fourteenth N-type transistors are caused to select a time window sampling voltage and an external reference voltage connected to respective input ports of the OTA synaptic circuit under control of a second control signal and a complement of the second control signal.

8. The method of claim 7, wherein switching the input port of the OTA synaptic circuit connected to the time window sampling voltage and an external reference voltage based on a switch switching circuit comprises:

when the third control signal is at a low level, the fourth P-type transistor is turned on, the fifteenth N-type transistor is turned off, and a port of the external reference voltage is connected with a fourth common reference voltage;

when the third control signal is at a high level, the fourth P-type transistor is turned off, the fifteenth N-type transistor is turned on, and a port of the external reference voltage is connected with a third common reference voltage;

When the second control signal is at a low level and the complementary signal of the second control signal is at a high level, switching on thirteenth to fourteenth N-type transistors, switching off eleventh to twelfth N-type transistors, wherein a port of the external reference voltage is connected with a positive input port of the OTA synaptic circuit, and an output port of the time window sampling voltage is connected with a negative input port of the OTA synaptic circuit;

when the second control signal is in a high level and the complementary signal of the second control signal is in a low level, turning off thirteenth to fourteenth N-type transistors, turning on eleventh to twelfth N-type transistors, wherein a port of the external reference voltage is connected with a negative input port of the OTA synaptic circuit, and an output port of the time window sampling voltage is connected with a positive input port of the OTA synaptic circuit;

wherein the external reference voltages include the third common reference voltage and a fourth common reference voltage.

9. The method according to claim 4, wherein the step of calculating the amount of change in synaptic weights under the action of the time window sampling voltage and the external reference voltage when the first external pulse signal and the second external pulse signal arrive based on the OTA synaptic circuit comprises:

When the first external pulse signal arrives earlier than the second external pulse signal, determining the positive and negative sum of currents output by the OTA synaptic circuit according to the positive and negative sum of voltage differences on gates of a sixteenth N-type transistor and a seventeenth N-type transistor in the OTA synaptic circuit, and determining the variation of the synaptic weight according to the positive and negative sum of currents;

when the first external pulse signal arrives later than the second external pulse signal, determining the positive and negative sum of currents output by the OTA synaptic circuit according to the positive and negative sum of voltage differences on the grid electrodes of an eighteenth N-type transistor and a nineteenth N-type transistor in the OTA synaptic circuit, and determining the variation of the synaptic weight according to the positive and negative sum of currents;

the step of determining the positive and negative sum of the current output by the OTA synaptic circuit according to the positive and negative sum of the voltage difference on the grid electrodes of the sixteenth N-type transistor and the seventeenth N-type transistor in the OTA synaptic circuit, and determining the variation of the synaptic weight according to the positive and negative sum of the current comprises the following steps:

when the voltage on the grid electrode of the seventeenth N-type transistor is larger than the voltage on the grid electrode of the sixteenth N-type transistor, the OTA synaptic transmission circuit outputs forward current to the storage capacitor through the first transmission tube at the moment when the second external pulse signal arrives, and the synaptic weight is increased;

When the voltage on the grid electrode of the seventeenth N-type transistor is smaller than the voltage on the grid electrode of the sixteenth N-type transistor, the OTA synaptic transmission circuit outputs negative current to the storage capacitor through the first transmission tube at the moment when the second external pulse signal arrives, and the synaptic weight is reduced;

the step of determining the positive and negative sum of the current output by the OTA synaptic circuit according to the positive and negative sum of the voltage difference on the grid electrodes of the eighteenth N-type transistor and the nineteenth N-type transistor in the OTA synaptic circuit, and determining the variation of the synaptic weight according to the positive and negative sum of the current comprises the following steps:

when the voltage on the grid electrode of the nineteenth N-type transistor is larger than the voltage on the grid electrode of the eighteenth N-type transistor, the OTA synaptic transmission circuit outputs forward current to the storage capacitor through a second transmission tube at the moment that the first external pulse signal arrives, and the synaptic weight is increased;

when the voltage on the grid electrode of the nineteenth N-type transistor is smaller than the voltage on the grid electrode of the eighteenth N-type transistor, the OTA synaptic transmission circuit outputs negative current to the storage capacitor through a second transmission tube at the moment when the first external pulse signal arrives, and the synaptic weight is reduced.

Images