CN110995405A - Chaos-based initial vector generation algorithm and IP core thereof - Google Patents

Abstract

The invention provides a chaos-based initial vector generation algorithm and an IP core thereof, wherein the generation algorithm is based on an initial value x of 32 bits input in a sequence generator of Logistic chaos₀Dividing 128-bit initial KEY KEY of ZUC encryption algorithm into 16 32-bit KEYs [ i](ii) a Will key 0]Assigned to 32 bits x₀And calculate x₁＝4x₀(1‑x₀) (ii) a Will key [ i]Assign a key [ i-1 ]]Then x is added₁Assign value to key [15]For all x generated in sequence₁The sequence truncates the last 128-bit sequence every 1024 bits as an initial vector. An IP core to generate an algorithm, comprising: the method comprises an initial vector generation module, a ZUC encryption algorithm module, a key stream FIFO module, an operation module, a UART communication module and a controller module. The invention greatly improves the unpredictability of the initial vector by utilizing the good randomness of the chaotic pseudo-random sequence.

Description

Chaos-based initial vector generation algorithm and IP core thereof

The technical field is as follows:

the invention relates to the field of data encryption, in particular to a chaos initial vector generation algorithm and an IP core thereof.

Background art:

ZUC is a synchronous sequence cipher algorithm, the input of which contains two parts, namely an Initial Key (Key) with 128 bits of bit width and an Initial Vector (IV) with 128 bits of bit width. The ZUC sequence cipher algorithm encrypts digital information using an input 128-bit KEY and a 128-bit initial vector generation KEY stream.

The ZUC sequence cipher algorithm is the third set of international encryption algorithms recommended by the international organization for standardization 3GPP (3rd Generation partnership project). According to the ZUC sequence cipher algorithm promulgated by 3GPP, the initial vector is generated in a fixed manner and structure by using the relevant control information in the wireless communication process, and is expressed as: let signal COUNT [0] | COUNT [1] | COUNT [3], COUNT represents a frame counter in a communication process, whose bit width is 32 bits, where COUNT [ i ] (0 ≦ i ≦ 3) is a byte 8 bits long, and an initial vector of 128-bit width is expressed as IV [0] | IV [1] | | IV [2] | |.

IV[0]＝COUNT[0],IV[1]＝COUNT[1],

IV[2]＝COUNT[2],IV[3]＝COUNT[3],

IV[4]＝BEARER||DIRECTION||002,

IV[5]＝IV[6]＝IV[7]＝000000002,

IV[8]＝IV[0],IV[9]＝IV[1],

IV[10]＝IV[2],IV[11]＝IV[3],

IV[12]＝IV[4],IV[13]＝IV[5],

IV[14]＝IV[6],IV[15]＝IV[7].

The symbol "|" is a bit connection symbol, the bit width of the signal BEARER is 5 bits, the function is a BEARER layer identifier, the bit width of the signal DIRECTION is 1 bit, and the function is a transmission DIRECTION identifier. Since the initial vector is insecure in the communication and can be transmitted in plaintext, and the signal COUNT is set to 0 after each time the KEY is updated and is changed in an incremental manner, and the signal DIRECTION has only two states, i.e., up and down, only 5 bits of the signal BEARER are completely unpredictable in the whole initial vector. Ideally, the number of bits in the unpredictable part of the IV and the number of bits of the KEY should be the same to improve the resistance to TMDTTO (Time-Memory-Data Trade-Off) attacks. This problem is noted in some literature and it is also noted that a shorter number of unpredictable bits in the initial vector reduces the complexity of the alternative type of TMTO attack, while increasing the number of unpredictable bits in the initial vector is beneficial in ameliorating this problem.

The initial vector plays a very important role in the ssc algorithm. In many cases, the KEY cannot be changed frequently in the specific encryption process, and the updating and using of different initial vectors avoids the situation that the same ciphertext is generated under the same plaintext and the same KEY, and also avoids the situation that the same KEY stream is used for encryption for multiple times. Meanwhile, in wireless communication, information in a channel is easily lost, and an encryption communication system is difficult to apply when the encryption communication system can correctly decrypt only under the condition that the information is completely received.

Disclosure of Invention

Based on the defects, the invention provides the chaos initial vector generation algorithm and the IP core thereof, which greatly improves the unpredictability of the initial vector so as to improve the capability of coping with TMTO attacks.

The technology adopted by the invention is as follows: a chaos-based initial vector generation algorithm comprises the following steps:

firstly, inputting an initial value x of 32 bits into a sequence generator based on Logistic chaos₀Dividing 128-bit initial KEY KEY of ZUC encryption algorithm into 16 32-bit KEYs [ i](i is not less than 0 and not more than 15), key [ i ≦ 15 ≦ key](i is more than or equal to 0 and less than or equal to 15) are respectively used as the input of Logistic chaotic iterative mapping,

the Logistic chaotic iterative mapping expression is as follows:

x_n+1＝4x_n(1-x_n) (1)

wherein x₀Is an initial value, n is the number of iterations, and x_nThe device is composed of a 32-bit register;

step two, key [0]]Assigned to 32 bits x₀And calculate x₁＝4x₀(1-x₀)；

Step three, key [ i ]]Assign a key [ i-1 ]]Then x is added₁Assign value to key [15]For all x generated in sequence₁The sequence intercepts the last 128-bit sequence as an initial vector at 1024-bit intervals, and returns to step two.

The invention also has the following features: an IP core based on a chaos initial vector generation algorithm comprises the following steps: the initial vector generating module, the ZUC encryption algorithm module, the key stream FIFO module, the operation module, the UART communication module and the controller module which are generated by the method,

the initial vector generation module is responsible for generating an initial vector required by the ZUC encryption algorithm module;

the ZUC encryption algorithm module is responsible for generating a KEY sequence for encryption and decryption according to a KEY KEY and an initial vector;

the key stream FIFO module is used for caching the key stream output by the ZUC encryption algorithm module;

the UART communication module realizes the modulation and demodulation work of the communication process of the IP core and the upper computer;

the arithmetic module carries out XOR operation on data taken out from a receiver FIFO unit and a key stream FIFO module of the UART communication module to finish encryption and decryption of the data, and delivers the processed data to a transmitter FIFO unit of the UART communication module;

the controller module is a main control unit of the whole IP core, all modules work under the scheduling of the controller module, and the controller module controls the flow direction of data and the operation received by the data.

The invention has the following advantages and beneficial effects: the invention utilizes the good randomness of the chaotic pseudo-random sequence to greatly improve the unpredictability of the initial vector so as to improve the capability of coping TMTO attack, and combines the initial vector with the ZUC sequence cryptographic algorithm to form an important component of the IP core of the ZUC encryption algorithm. In addition, the sequence cipher algorithm adds the initial vector and designs the frame structure for data communication, so that even if partial data is damaged or lost, the system can continue to complete the decryption of the correctly received data frame. The initial vector may also be used as the number of information frames in case the transmitted information is sequential.

Drawings

FIG. 1 is a schematic diagram of an FPGA-based ZUC encryption algorithm IP core;

FIG. 2 is a top level design diagram of initial vector generation algorithm module hardware implementation based on Logistic chaos;

FIG. 3 is a flow diagram of an initial vector generation module;

FIG. 4 is a diagram of the FPGA top level architecture.

Detailed Description

The invention is further illustrated by way of example in the accompanying drawings of the specification:

example 1

A chaos-based initial vector generation algorithm comprises the following steps:

firstly, inputting an initial value x of 32 bits into a sequence generator based on Logistic chaos₀Dividing 128-bit initial KEY KEY of ZUC encryption algorithm into 16 32-bit KEYs [ i](i is not less than 0 and not more than 15), key [ i ≦ 15 ≦ key](i is more than or equal to 0 and less than or equal to 15) are respectively used as the input of Logistic chaotic iterative mapping,

the Logistic chaotic iterative mapping expression is as follows:

x_n+1＝4x_n(1-x_n) (1)

wherein x₀Is an initial value, n is the number of iterations, and x_nThe device is composed of a 32-bit register;

step two, key [0]]Assigned to 32 bits x₀And calculate x₁＝4x₀(1-x₀)；

Step three, key [ i ]]Assign a key [ i-1 ]]Then x is added₁Assign value to key [15]For all x generated in sequence₁Sequence space 1024The last 128-bit sequence is truncated as an initial vector and transferred back to step two.

The IP core based on the chaos initial vector generation algorithm comprises the following steps: the device comprises an initial vector generation module, a ZUC encryption algorithm module, a key stream FIFO module, an operation module, a UART communication module and a controller module, wherein the initial vector generation module is responsible for generating an initial vector required by the work of the ZUC encryption algorithm module;

the ZUC encryption algorithm module is responsible for generating a KEY sequence for encryption and decryption according to a KEY KEY and an initial vector;

the key stream FIFO module is used for caching the key stream output by the ZUC encryption algorithm module;

the UART communication module realizes the modulation and demodulation work of the communication process of the IP core and the upper computer;

the arithmetic module carries out XOR operation on data taken out from a receiver FIFO unit and a key stream FIFO module of the UART communication module to finish encryption and decryption of the data, and delivers the processed data to a transmitter FIFO unit of the UART communication module;

the controller module is a main control unit of the whole IP core, all modules work under the scheduling of the controller module, and the controller module controls the flow direction of data and the operation received by the data.

Example 2

IP core FPGA based on chaos initial vector generation algorithm

As shown in fig. 2, the initial vector generation module has 6 input-output signals, the definitions of which are listed in table 1.

TABLE 1 Top level Module Signal List

The initial vector generation module has a control signal "start" in addition to the clock signal and the reset signal, and the main workflow of the initial vector generation module is described here: when the initial vector generation module is powered on, firstly, reset operation is carried out, then the initial vector generation module enters a standby state, when a start signal is valid for the first time, the initial vector generation module downloads a secret key and runs for 1024 clock cycles, then an initial vector is output, meanwhile, an initial vector valid flag signal IV is output to be valid, the signal on the output signal IV is shown to be valid at the moment, then the module enters the standby state, if the signal start is valid again, the module runs for 1024 clock cycles again in the immediately previous state and generates a new initial vector, and so on, and an algorithm flow chart is used for expressing a main working flow, as shown in FIG. 3.

FIG. 4 is a top level architecture design in which a module with multi-beat latency has its latency (latency) labeled in the figure. The global calculation precision of the initial vector generation module is 32 bits, and the system variable x can be known by the formula (1)_nE (0,1), all operations of IVMKAKER are 32-bit unsigned pure decimals, e.g., a 32-bit binary number in the system is represented as M_b＝m₃₁m₃₀m₂₉…m₁m₀Wherein m is_iE {0,1} and i ═ 0,1,2, …,31, the decimal number it represents can be represented by equation (2):

the control module is a control unit that performs the function of generating the initial value in equation (1) and controls the functions of enabling each sub-module and selecting signals of the selector module. The delay module delays the input by two clock cycles to output; the functional expression of the position negation module is as follows:

bn[31:0]＝～sel[31:0](3)

the adder module performs the addition 1 calculation on the input value, and the expression is as follows:

add[31:0]＝bn[31:0]+1 (4)

bit-wise negation module and additionThe cascade connection of the device modules jointly completes (1-x) in the formula (1)_n) Part of the calculation, whose principle is similar to complement, is illustrated here as: for example, there are unsigned binary numbers a 10000 and B1010, and it is clear that the value of a-B can be obtained by B + 1. This is done because all numbers in the system are 32 unsigned decimal numbers, and 33 bit wide is needed to represent decimal 1, and the method in the design avoids adding one bit wide separately for representing decimal 1 and using subtraction in the digital circuit, and furthermore, the negation operation is very simple to implement for the digital circuit; the multiplier module completes x_n(1-x_n) When two data with a bit width of 32 bits are multiplied, a product with a bit width of 64 bits is generated inside the multiplier.

The resource and speed conditions occupied by the realized initial vector generation module are counted, and compared with a circuit which uses a conventional Logistic chaotic sequence generation algorithm to realize the same function, the result is shown in table 2, and the highest operation frequency of the circuit is increased by 2.4 times under the condition that the logic resource Slice consumption of the realized initial vector generation module on an FPGA chip is increased by 16.3%, and good resource consumption and speed level are obtained on the basis that the generated initial vector obtains better unpredictability.

TABLE 2 resource vs. speed

Claims (2)

1. A chaos-based initial vector generation algorithm is characterized in that an initial vector generation method comprises the following steps:

firstly, inputting an initial value x of 32 bits into a sequence generator based on Logistic chaos₀Dividing 128-bit initial KEY KEY of ZUC encryption algorithm into 16 32-bit KEYs [ i](i is not less than 0 and not more than 15), key [ i ≦ 15 ≦ key](i is more than or equal to 0 and less than or equal to 15) are respectively used as Logistic chaotic iterative mappingThe input of (a) is performed,

the Logistic chaotic iterative mapping expression is as follows:

x_n+1＝4x_n(1-x_n) (1)

wherein x₀Is an initial value, n is the number of iterations, and x_nThe device is composed of a 32-bit register;

step two, key [0]]Assigned to 32 bits x₀And calculate x₁＝4x₀(1-x₀)；

Step three, key [ i ]]Assign a key [ i-1 ]]Then x is added₁Assign value to key [15]For all x generated in sequence₁The sequence intercepts the last 128-bit sequence as an initial vector at 1024-bit intervals, and returns to step two.

2. An IP core based on a chaos initial vector generation algorithm is characterized by comprising the following steps: the method of claim 1, wherein the initial vector generation module, the ZUC encryption algorithm module, the keystream FIFO module, the arithmetic module, the UART communication module and the controller module are generated by the method,

the initial vector generation module is responsible for generating an initial vector required by the ZUC encryption algorithm module;

the ZUC encryption algorithm module is responsible for generating a KEY sequence for encryption and decryption according to a KEY KEY and an initial vector;

the key stream FIFO module is used for caching the key stream output by the ZUC encryption algorithm module;

the UART communication module realizes the modulation and demodulation work of the communication process of the IP core and the upper computer;

the arithmetic module carries out XOR operation on the data taken out from the receiver FIFO unit and the key stream FIFO module of the UART communication module to finish the encryption and decryption of the data, and the processed data is delivered to the transmitter FIFO unit of the UART communication module;

the controller module is a main control unit of the whole IP core, all modules work under the scheduling of the controller module, and the controller module controls the flow direction of data and the operation received by the data.

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