CN110970346A - Semiconductor structure and preparation method - Google Patents
Semiconductor structure and preparation method Download PDFInfo
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- CN110970346A CN110970346A CN201811147684.2A CN201811147684A CN110970346A CN 110970346 A CN110970346 A CN 110970346A CN 201811147684 A CN201811147684 A CN 201811147684A CN 110970346 A CN110970346 A CN 110970346A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 105
- 238000002360 preparation method Methods 0.000 title abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 152
- 238000005468 ion implantation Methods 0.000 claims abstract description 21
- 238000011049 filling Methods 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 39
- 230000004888 barrier function Effects 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 17
- -1 oxygen ions Chemical class 0.000 claims description 15
- 150000002500 ions Chemical class 0.000 claims description 12
- 229910052796 boron Inorganic materials 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 238000002955 isolation Methods 0.000 abstract description 46
- 230000000694 effects Effects 0.000 abstract description 11
- 230000007547 defect Effects 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 261
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 29
- 229910052581 Si3N4 Inorganic materials 0.000 description 27
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 26
- 229920002120 photoresistant polymer Polymers 0.000 description 17
- 230000008569 process Effects 0.000 description 14
- 239000000377 silicon dioxide Substances 0.000 description 14
- 235000012239 silicon dioxide Nutrition 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 238000002513 implantation Methods 0.000 description 9
- 239000006117 anti-reflective coating Substances 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000001657 homoepitaxy Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
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- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention provides a semiconductor structure and a preparation method thereof, wherein the preparation method comprises the following steps: 1) providing a semiconductor substrate, and forming a groove in the semiconductor substrate; 2) performing ion implantation on the bottom and the side wall of the groove to form a doped dielectric layer; 3) forming a first dielectric layer in the groove, wherein the upper surface of the first dielectric layer is lower than the upper surface of the semiconductor substrate; 4) growing a substrate extension layer positioned above the first dielectric layer on the side wall of the groove which is not covered by the first dielectric layer, and exposing partial surface of the first dielectric layer; 5) and forming a second dielectric layer at least filling the groove on the surfaces of the first dielectric layer and the substrate extension layer. According to the shallow trench isolation structure, the substrate extension layer is formed to cover and protect the side wall of the dielectric layer at the edge of the trench, so that the defect of an edge gap is avoided, the area of an active area is increased, and the narrow channel effect is reduced; the shallow trench isolation structure with the wider trench bottom is obtained by adopting ion implantation, the isolation effect is improved, and the product yield is improved.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly, to a semiconductor structure and a method for fabricating the same.
Background
At present, Shallow Trench Isolation (STI) is widely used in the isolation process of the semiconductor technology node of 0.25um and below. The defects or parameters that affect the performance of the shallow trench isolation structure mainly include a divot (divot) and the bottom width of the shallow trench isolation structure. In the prior art, the edge of a shallow trench isolation structure is often corroded in subsequent wet etching to form an edge gap defect, so that a device fails; in addition, as the device size decreases, the bottom width of the shallow trench isolation structure and the channel width of the transistor also decrease, which also seriously affects the electrical performance of the device.
Therefore, it is desirable to provide a new semiconductor structure and a method for fabricating the same, which solve the above-mentioned problems.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a semiconductor structure and a manufacturing method thereof, which are used to solve the problem of poor isolation effect of the shallow trench isolation structure in the prior art.
To achieve the above and other related objects, the present invention provides a method for fabricating a semiconductor structure, comprising the steps of:
1) providing a semiconductor substrate, and forming a groove in the semiconductor substrate;
2) performing ion implantation on the bottom and the side wall of the groove to form a doped dielectric layer on the bottom and the side wall of the groove;
3) forming a first dielectric layer in the groove, wherein the upper surface of the first dielectric layer is lower than the upper surface of the semiconductor substrate;
4) growing a substrate extension layer on the side wall of the groove which is not covered by the first dielectric layer, wherein the substrate extension layer is positioned above the first dielectric layer and exposes part of the surface of the first dielectric layer; and
5) and forming a second dielectric layer on the surfaces of the first dielectric layer and the substrate extension layer, wherein the second dielectric layer at least fills the groove.
As a preferable aspect of the present invention, in the step 1), the step of forming the trench in the substrate includes:
1-1) depositing an etching barrier layer on the surface of the semiconductor substrate, and carrying out graphical processing on the etching barrier layer; and
1-2) etching the semiconductor substrate by taking the etching barrier layer as an etching mask, and forming the groove in the semiconductor substrate.
As a preferable aspect of the present invention, in step 2), the implanted ions include oxygen ions.
As a preferable mode of the present invention, in the step 2), the implanted ions further include at least one of boron ions or chloride ions.
As a preferable scheme of the present invention, in step 2), after the doped dielectric layer is formed at the bottom and the sidewall of the trench, a step of performing a rapid thermal processing process on the doped dielectric layer is further included.
As a preferable aspect of the present invention, in the step 3), the forming a first dielectric layer in the trench includes:
3-1) filling the first dielectric layer in the groove, wherein the groove is at least filled with the first dielectric layer; and
3-2) back-etching the first dielectric layer to enable the upper surface of the first dielectric layer to be lower than the upper surface of the semiconductor substrate.
As a preferable aspect of the present invention, the upper surface of the substrate extension layer formed in step 4) is flush with the upper surface of the semiconductor substrate.
As a preferable aspect of the present invention, in step 4), the material of the substrate extension layer grown is the same as the material of the semiconductor substrate.
The present invention also provides a semiconductor structure comprising:
a semiconductor substrate;
a trench formed in the semiconductor substrate;
the doped dielectric layer is formed at the bottom and the side wall of the groove;
the first dielectric layer is formed in the groove, and the upper surface of the first dielectric layer is lower than the upper surface of the semiconductor substrate;
the substrate extension layer is formed on the side wall of the groove which is not covered by the first dielectric layer and extends to cover part of the surface of the first dielectric layer; and
and the second dielectric layer is formed on the surfaces of the first dielectric layer and the substrate extension layer and at least fills the groove.
As a preferred embodiment of the present invention, the doped dielectric layer is formed by performing ion implantation on the bottom and the sidewall of the trench and performing rapid thermal processing.
As a preferred embodiment of the present invention, the ions implanted in the doped dielectric layer include oxygen ions.
As a preferable aspect of the present invention, the ions implanted in the doped dielectric layer further include at least one of boron ions or chloride ions.
As a preferable aspect of the present invention, an upper surface of the substrate extension layer is flush with an upper surface of the semiconductor substrate.
In a preferred embodiment of the present invention, the material of the substrate extension layer is the same as the material of the semiconductor substrate.
As described above, the present invention provides a semiconductor structure and a manufacturing method thereof, which have the following advantages:
according to the invention, a novel shallow trench isolation structure is introduced, and a substrate extension layer is formed to cover and protect the side wall of the dielectric layer at the edge of the trench, so that the formation of edge gap defects is avoided, the active area and the channel width among the shallow trench isolation structures are increased, and the narrow channel effect is reduced; by adopting the ion implantation method, the shallow trench isolation structure with wider trench bottom is obtained, the isolation effect of the shallow trench isolation structure is improved, and the product yield is improved.
Drawings
Fig. 1 is a schematic cross-sectional view of a shallow trench isolation structure obtained in the prior art.
Fig. 2 is a schematic top view of a prior art transistor formed in an active area between shallow trench isolation structures.
Fig. 3 is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present invention.
Fig. 4 to fig. 20 are schematic cross-sectional views illustrating steps of a method for fabricating a semiconductor structure according to an embodiment of the invention.
Fig. 21 is a schematic top view illustrating a transistor formed in an active region between semiconductor structures according to a first embodiment of the present invention.
Description of the element reference numerals
101 silicon substrate
102 silicon dioxide dielectric layer
102a edge notch
103 active region
104 shallow trench isolation structure
105 semiconductor substrate
106 grid
201 semiconductor substrate
201a groove
201b substrate extension layer
201c word line trench
202 doped dielectric layer
203 first dielectric layer
204 second dielectric layer
205 liner oxide layer
206 silicon nitride barrier layer
207 photoresist layer
207a anti-reflective coating
208 silicon nitride spacer layer
209 hard mask layer
210 word line photoresist layer
210a word line photoresist anti-reflective coating
211 isolation oxide layer
212 first conductive layer
213 second conductive layer
214 silicon nitride fill layer
303 active region
303a substrate active region
304 shallow trench isolation structure
305 semiconductor substrate
306 grid electrode
W1 channel width
W2 expanded channel width
S1-S5 Steps 1) -5 of the method for fabricating a semiconductor structure provided in the first embodiment of the present invention
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 21. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Example one
Fig. 1 is a schematic cross-sectional view of a shallow trench isolation structure obtained by the prior art. The silicon dioxide dielectric layer 102 is filled in the trench formed on the silicon substrate 101 to form the shallow trench isolation structure, and in the subsequent process, a wet etching is generally used to remove the dielectric layer on the surface of the silicon substrate 101, which simultaneously etches the silicon dioxide dielectric layer 102 in the trench and forms an edge gap 102a at the edge of the trench. The edge gap 102a may form an additional leakage current channel in a subsequent process, which may affect the isolation effect and even cause device failure. In addition, the bottom width a1 of the shallow trench isolation structure also has a large influence on the leakage performance of the shallow trench isolation structure, and the narrow bottom width a1 may cause substrate leakage current to occur, which affects the electrical performance of the device.
Fig. 2 is a schematic top view of a prior art transistor formed in an active region between shallow trench isolation structures. An active region 103 is isolated from a semiconductor substrate 105 by a shallow trench isolation structure 104, and a gate 106 is formed on the active region 103. With the continuous development of the integration level of the device, the channel width W1 of the transistor is continuously reduced, so that a narrow channel effect is easily caused, the threshold voltage of the transistor is increased, the driving current is reduced, and the electrical performance of the device is affected.
Referring to fig. 3 to 21, the present invention provides a method for fabricating a semiconductor structure, including the following steps:
1) providing a semiconductor substrate 201, and forming a groove 201a in the semiconductor substrate 201;
2) performing ion implantation on the bottom and the side wall of the trench 201a to form a doped dielectric layer 202 on the bottom and the side wall of the trench 201 a;
3) forming a first dielectric layer 203 in the trench 201a, wherein the upper surface of the first dielectric layer 203 is lower than the upper surface of the semiconductor substrate 201;
4) growing a substrate extension layer 201b on the sidewall of the trench 201a not covered by the first dielectric layer 203, wherein the substrate extension layer 201b is located above the first dielectric layer 203 and exposes a part of the surface of the first dielectric layer 203; and
5) and forming a second dielectric layer 204 on the surfaces of the first dielectric layer 203 and the substrate extension layer 201b, wherein the second dielectric layer 204 at least fills the trench 201 a.
In step 1), referring to step S1 of fig. 3 and fig. 4 to 6, a semiconductor substrate 201 is provided, and a trench 201a is formed in the semiconductor substrate 201. Optionally, the step of forming the trench in the substrate comprises the steps of: 1-1) depositing an etching barrier layer on the surface of the semiconductor substrate 201, and carrying out graphical processing on the etching barrier layer; 1-2) etching the semiconductor substrate 201 by using the etching barrier layer as an etching mask, and forming the trench in the semiconductor substrate 201. In this embodiment, the semiconductor substrate 201 includes a silicon substrate, a pad oxide layer 205 is grown on a surface of the semiconductor substrate 201, and a silicon nitride barrier layer 206 is grown on a surface of the pad oxide layer 205. The method of growing the liner oxide layer 205 comprises a thermal oxidation process and the method of growing the silicon nitride barrier layer 206 comprises chemical vapor deposition. Optionally, the silicon nitride barrier layer 206 is patterned by photolithography and etching. A photoresist layer 207 is coated on the surface of the silicon nitride barrier layer 206, and optionally, an anti-reflective coating layer 207a may be coated before the photoresist layer 207 is coated. The patterned photoresist layer 207 is obtained by exposure and development, as shown in fig. 4. The patterned photoresist layer 207 is used as an etching mask to etch the anti-reflective coating layer 207a, the silicon nitride barrier layer 206 and the pad oxide layer 205, and the photoresist layer 207 and the anti-reflective coating layer 207a are removed by ashing to remove photoresist, as shown in fig. 5. With the silicon nitride barrier layer 206 as an etching barrier layer, the exposed semiconductor substrate 201 is dry etched, and the trench 201a is formed, as shown in fig. 6. It should be noted that, when the semiconductor substrate 201 is etched by the dry etching, a high selection ratio needs to be maintained for the silicon nitride barrier layer 206 to ensure that the silicon nitride barrier layer 206 still has a certain thickness, for example, 40 to 100nm, after being etched, so that the silicon nitride barrier layer can shield and protect an active region located below the silicon nitride barrier layer in a subsequent ion implantation process.
In step 2), referring to step S2 of fig. 3 and fig. 7 to 8, ion implantation is performed on the bottom and the sidewall of the trench 201a to form a doped dielectric layer 202 on the bottom and the sidewall of the trench 201 a. Alternatively, when ion implantation is performed on the implantation region 202a at the bottom and the sidewall of the trench 201a, the implanted ions are mainly oxygen ions, and a small amount of impurity ions, such as boron ions or chloride ions, may be doped therein to increase the oxidation rate and reduce defects, as shown in fig. 7. The implantation dosage of the ion implantation is 1012To 1015ions/cm2The implantation energy is 5KeV to 35 KeV. After the ion implantation is completed, performing Rapid Thermal Processing (RTP) on the implantation region 202a to eliminate damage caused by the ion implantation, wherein the temperature rise and temperature fall rates of the rapid thermal processing are both 10-200 ℃/s. After the ion implantation and the rapid thermal processing, the doped dielectric layer 202 composed of silicon dioxide is formed in the implanted region 202a, as shown in fig. 8. The doped dielectric layer202, the width of the shallow trench isolation structure is no longer limited to the width of the trench 201a, the bottom width of the shallow trench isolation structure is greatly widened, the substrate leakage current is reduced, and the electrical performance of the device is improved. In addition, the doped dielectric layer 202 may also serve as a silicon dioxide liner layer in the trench, so that a step of growing a silicon dioxide liner layer in the trench is omitted when a dielectric layer is filled in the trench in the following step.
In step 3), referring to step S3 of fig. 3 and fig. 9 to 10, a first dielectric layer 203 is formed in the trench 201a, and the upper surface of the first dielectric layer 203 is lower than the upper surface of the semiconductor substrate 201. Optionally, a high-density plasma chemical vapor deposition (HDPCVD) is used to form the first dielectric layer 203 in the trench 201a, where the first dielectric layer 203 includes a silicon dioxide layer, and the trench 201a is at least filled with the first dielectric layer 203. In this embodiment, the first dielectric layer 203 also covers the surface of the silicon nitride barrier layer 206, as shown in fig. 9. And etching the first dielectric layer 203 by using a back etching process, so that the upper surface of the first dielectric layer 203 is lower than the upper surface of the semiconductor substrate 201, as shown in fig. 10. The etch-back process includes dry etching, which requires a high selectivity ratio for silicon and silicon nitride, and the upper surface of the first dielectric layer 203 after etch-back is kept flat. Optionally, the difference between the upper surface of the first dielectric layer 203 and the upper surface of the semiconductor substrate 201 is 5 to 25 nm. This allows the step height portion region on the sidewall of the trench 201a to be exposed so as to form the substrate extension layer 201b in the exposed region in the subsequent step, and the step height is an important parameter for the epitaxial growth of the substrate extension layer 201b, so that the epitaxial growth rate and the epitaxial layer thickness can be effectively controlled.
In step 4), referring to step S4 of fig. 3 and fig. 11, a substrate extension layer 201b is grown on the sidewall of the trench 201a not covered by the first dielectric layer 203, wherein the substrate extension layer 201b is located above the first dielectric layer 203 and exposes a portion of the surface of the first dielectric layer 203. Optionally, the substrate extension layer 201b is epitaxially grown on the sidewall of the trench 201a not covered by the first dielectric layer 203 by chemical vapor deposition. The substrate extension layer 201b is formed of the same material as the semiconductor substrate 201, and in this embodiment, is a silicon material, and the epitaxial growth includes homoepitaxy, i.e., the epitaxial layer and the substrate have the same chemical properties and crystal structure. The process temperature range of the epitaxial growth is 800-1200 ℃, and the process time range is 0.1-15 min. After the epitaxial growth is finished, the substrate extension layer 201b is formed to be located above the first dielectric layer 203 and expose a part of the surface of the first dielectric layer 203, and the upper surface of the substrate extension layer 201b is flush with the upper surface of the semiconductor substrate 201, as shown in fig. 11. It should be noted that in other embodiments of the present invention, the material of the substrate extension layer 201b may also be different from the material of the semiconductor substrate 201; the material of the substrate extension layer 201b further includes silicon germanium or doped silicon material; the method for forming the substrate extension layer 201b is not limited to performing epitaxial growth on the sidewall covered by the first dielectric layer 203, and the substrate extension layer 201b may be formed by a method of depositing a substrate extension material and then performing photolithography and etching.
In step 5), referring to step S5 of fig. 3 and fig. 12 to 14, a second dielectric layer 204 is formed on the surfaces of the first dielectric layer 203 and the substrate extension layer 201b, and the second dielectric layer 204 at least fills the trench 201 a. Optionally, a second dielectric layer 204 is formed on the surfaces of the first dielectric layer 203 and the substrate extension layer 201b by high-density plasma chemical vapor deposition (HDPCVD), the second dielectric layer 204 includes a silicon dioxide layer, and the second dielectric layer 204 at least fills the trench 201 a. In this embodiment, the second dielectric layer 204 also covers the surface of the silicon nitride barrier layer 206, as shown in fig. 12. The silicon nitride barrier layer 206 is used as a stop barrier layer for chemical mechanical polishing to perform chemical mechanical polishing on the second dielectric layer 204, and after the chemical mechanical polishing, the upper surface of the second dielectric layer 204 is flush with the upper surface of the silicon nitride barrier layer 206, as shown in fig. 13. The silicon nitride barrier layer 206 is removed by using a hot phosphoric acid wet etching or a dry etching with a higher selectivity to silicon oxide, so as to obtain the shallow trench isolation structure provided by the embodiment, as shown in fig. 14.
As an example, referring to fig. 15 to 20, after step 5), a process step of forming a buried word line structure in the semiconductor substrate 201 isolated by the shallow trench isolation structure is further included. After removing the silicon nitride barrier layer 206 in step 5), a silicon nitride isolation layer 208 and a hard mask layer 209 are sequentially formed above the pad oxide layer 205 and the second dielectric layer 204. The hard mask layer 209 has a composite layer structure including carbon and silicon oxynitride, and in this embodiment, the film layer structure of the hard mask layer 209 is carbon-silicon oxynitride-carbon-silicon oxynitride from bottom to top. A word line photoresist layer 210 is coated on the surface of the hard mask layer 209, and optionally, a word line photoresist antireflection layer 210a is coated on the surface of the hard mask layer 209 before the word line photoresist layer 210 is coated. By exposure and development, the word line photoresist layer 210 is patterned, as shown in fig. 15. Alternatively, depending on the size of the actual exposure dimension, a pitch doubling technique (pitch doubling) may be optionally used. With the word line photoresist layer 210 as an etching mask, the word line photoresist antireflection coating 210a and the hard mask layer 209 exposed at the lower layer are etched by dry etching, and the word line photoresist layer 210 and the word line photoresist antireflection coating 210a are removed by ashing to form the patterned hard mask layer 209, as shown in fig. 16. With the hard mask layer 209 as an etching mask, the underlying silicon nitride isolation layer 208, the pad oxide layer 205, and the semiconductor substrate 201 are etched to form a word line trench 201c, as shown in fig. 17. The hard mask layer 209 remaining after the etching is removed, and an isolation oxide layer 211, a first conductive layer 212, and a second conductive layer 213 are sequentially grown in the word line trench 201c, as shown in fig. 18, in this embodiment, the first conductive layer 212 and the second conductive layer 213 also cover the surface of the silicon nitride isolation layer 208. Optionally, the isolation oxide layer 211 comprises a silicon dioxide layer, the first conductive layer 212 comprises a titanium nitride layer, and the second conductive layer 213 comprises a metal tungsten layer. The first conductive layer 212 and the second conductive layer 213 are etched to make the upper surface lower than the upper surface of the semiconductor substrate 201, so as to form a conductive portion of the buried word line structure, as shown in fig. 19. A silicon nitride filling layer 214 is filled on the upper surfaces of the first conductive layer 212 and the second conductive layer 213, the word line trench 201c is at least filled with the silicon nitride filling layer 214, and in this embodiment, the silicon nitride filling layer 214 also covers the upper surface of the silicon nitride isolation layer 208, as shown in fig. 20. As can also be seen from fig. 20, the active regions on both sides of the buried word line structure as a gate are expanded by the substrate extension layer 201b, thereby effectively increasing the area of the active region. For the semiconductor memory device, the subsequent process further includes the step of preparing the bit line structure and the capacitor connecting line, which is not described in detail in this embodiment.
As an example, in order to further explain the extension of the active area by forming the substrate extension layer 201b in the present embodiment, please refer to fig. 21. Fig. 21 is a schematic top view of a transistor formed in the active region between the resulting shallow trench isolation structures in this embodiment. An active region 303 is isolated from a semiconductor substrate 305 by a shallow trench isolation structure 304, and a gate 306 is formed on the active region 303. Here, the substrate active region 303a represents an active region area formed on the semiconductor substrate 305, and the area thereof is the same as the size of the active region 103 in fig. 2 when the substrate extension layer 201b is not grown. In this embodiment, the area of the active region 303 is expanded by growing the substrate extension layer 201b, so that the expanded channel width W2 of the transistor is greater than the channel width W1 of the transistor in the prior art in fig. 2, thereby reducing the narrow channel effect, reducing the threshold voltage of the transistor, improving the driving current, and optimizing the device performance.
Example two
Referring to fig. 14, the present invention further provides a semiconductor structure, comprising:
a semiconductor substrate 201;
a trench 201a formed in the semiconductor substrate 201;
a doped dielectric layer 202 formed on the bottom and the sidewall of the trench 201 a;
a first dielectric layer 203 formed in the trench 201a, wherein an upper surface of the first dielectric layer 203 is lower than an upper surface of the semiconductor substrate 201;
the substrate extension layer 201b is formed on the sidewall of the trench 201a which is not covered by the first dielectric layer 203, and extends to cover a part of the surface of the first dielectric layer 203; and
and a second dielectric layer 204 formed on the surfaces of the first dielectric layer 203 and the substrate extension layer 201b and at least filling the trench 201 a.
As shown in fig. 14, a trench 201a is formed in a semiconductor substrate 201, and optionally, the semiconductor substrate 201 includes a silicon substrate. A doped dielectric layer 202 is formed at the bottom and the sidewall of the trench 201a, optionally, the doped dielectric layer 202 includes a silicon dioxide layer, and the bottom width of the shallow trench isolation structure is widened by introducing the doped dielectric layer 202. Filling the trench 201a with a first dielectric layer 203, wherein an upper surface of the first dielectric layer 203 is lower than an upper surface of the semiconductor substrate 201, and optionally, the first dielectric layer 203 includes a silicon dioxide layer. A substrate extension layer 201b is formed on the sidewall of the trench 201a not covered by the first dielectric layer 203, the substrate extension layer 201b extends to cover a part of the surface of the first dielectric layer 203, and the substrate extension layer 201b can be used as an extension region of an active region, which increases the area of the active region. A second dielectric layer 204 is formed on the surfaces of the first dielectric layer 203 and the substrate extension layer 201b, and the second dielectric layer 204 may be a silicon dioxide layer and at least fills the trench 201 a.
As an example, the doped dielectric layer 202 is formed by performing ion implantation on the bottom and the sidewall of the trench 201a and performing rapid thermal processing. Optionally, the ion implantation has an implantation dose of 1012To 1015ions/cm2The implantation energy is 5KeV to 35 KeV. After the ion implantation is completed, the implantation region 202a is subjected to a Rapid Thermal Processing (RTP) to remove damage caused by the ion implantation, a temperature rise of the RTP, andthe temperature reduction rate ranges from 10 to 200 ℃/s.
As an example, the ions implanted in the doped dielectric layer 202 include oxygen ions. The oxygen ions may combine with silicon atoms in the silicon substrate after implantation and form a silicon dioxide layer.
As an example, the ions implanted in the doped dielectric layer 202 further include at least one of boron ions or chloride ions. The implantation of boron ions or chlorine ions can increase the oxidation rate of the silicon substrate during rapid thermal processing and reduce defects in the silicon dioxide layer.
As an example, the upper surface of the substrate extension layer 201b is flush with the upper surface of the semiconductor substrate 201. As an extension portion of the active region, the upper surface of the substrate extension layer 201b is flush with the upper surface of the semiconductor substrate 201, which is beneficial to performing the subsequent process and maintaining the planarization of the surface of the semiconductor substrate 201.
As an example, the material of the substrate extension layer 201b is the same as the material of the semiconductor substrate 201. Optionally, the material of the substrate extension layer 201b and the material of the semiconductor substrate 201 are both silicon materials, and the substrate extension layer 201b is formed by homoepitaxial growth. The process temperature range of the epitaxial growth is 800-1200 ℃, and the process time range is 0.1-15 min.
In summary, the present invention provides a semiconductor structure and a method for manufacturing the same, the method comprising: 1) providing a semiconductor substrate, and forming a groove in the semiconductor substrate; 2) performing ion implantation on the bottom and the side wall of the groove to form a doped dielectric layer on the bottom and the side wall of the groove; 3) forming a first dielectric layer in the groove, wherein the upper surface of the first dielectric layer is lower than the upper surface of the semiconductor substrate; 4) growing a substrate extension layer on the side wall of the groove which is not covered by the first dielectric layer, wherein the substrate extension layer is positioned above the first dielectric layer and exposes part of the surface of the first dielectric layer; 5) and forming a second dielectric layer on the surfaces of the first dielectric layer and the substrate extension layer, wherein the second dielectric layer at least fills the groove. The present invention also provides a semiconductor structure comprising: a semiconductor substrate; a trench formed in the semiconductor substrate; the doped dielectric layer is formed at the bottom and the side wall of the groove; the first dielectric layer is formed in the groove, and the upper surface of the first dielectric layer is lower than the upper surface of the semiconductor substrate; the substrate extension layer is formed on the side wall of the groove which is not covered by the first dielectric layer and extends to cover part of the surface of the first dielectric layer; and the second dielectric layer is formed on the surfaces of the first dielectric layer and the substrate extension layer and at least fills the groove. According to the shallow trench isolation structure, the substrate extension layer is formed to cover and protect the side wall of the dielectric layer at the edge of the trench, so that the defect of edge gaps is avoided, the area of an active area between the shallow trench isolation structures is increased, the width of a channel of a transistor is expanded, and the narrow channel effect is reduced; by adopting the ion implantation method, the shallow trench isolation structure with wider trench bottom is obtained, the isolation effect of the shallow trench isolation structure is improved, and the product yield is improved.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (14)
1. A method for manufacturing a semiconductor structure is characterized by comprising the following steps:
1) providing a semiconductor substrate, and forming a groove in the semiconductor substrate;
2) performing ion implantation on the bottom and the side wall of the groove to form a doped dielectric layer on the bottom and the side wall of the groove;
3) forming a first dielectric layer in the groove, wherein the upper surface of the first dielectric layer is lower than the upper surface of the semiconductor substrate;
4) growing a substrate extension layer on the side wall of the groove which is not covered by the first dielectric layer, wherein the substrate extension layer is positioned above the first dielectric layer and exposes part of the surface of the first dielectric layer; and
5) and forming a second dielectric layer on the surfaces of the first dielectric layer and the substrate extension layer, wherein the second dielectric layer at least fills the groove.
2. The method of claim 1, wherein in step 1), the step of forming the trench in the substrate comprises:
1-1) depositing an etching barrier layer on the surface of the semiconductor substrate, and carrying out graphical processing on the etching barrier layer; and
1-2) etching the semiconductor substrate by taking the etching barrier layer as an etching mask, and forming the groove in the semiconductor substrate.
3. The method of claim 1, wherein in step 2), the implanted ions comprise oxygen ions.
4. The method of claim 3, wherein in step 2), the implanted ions further comprise at least one of boron ions or chloride ions.
5. The method for fabricating a semiconductor structure according to claim 1, further comprising performing a rapid thermal processing on the doped dielectric layer after the doped dielectric layer is formed on the bottom and the sidewall of the trench in step 2).
6. The method of claim 1, wherein in step 3), the step of forming a first dielectric layer in the trench comprises the steps of:
3-1) filling the first dielectric layer in the groove, wherein the groove is at least filled with the first dielectric layer; and
3-2) back-etching the first dielectric layer to enable the upper surface of the first dielectric layer to be lower than the upper surface of the semiconductor substrate.
7. The method for fabricating a semiconductor structure according to claim 1, wherein the upper surface of the substrate extension layer formed in step 4) is flush with the upper surface of the semiconductor substrate.
8. The method for fabricating a semiconductor structure according to claim 1, wherein in step 4), the material of the substrate extension layer is the same as the material of the semiconductor substrate.
9. A semiconductor structure, comprising:
a semiconductor substrate;
a trench formed in the semiconductor substrate;
the doped dielectric layer is formed at the bottom and the side wall of the groove;
the first dielectric layer is formed in the groove, and the upper surface of the first dielectric layer is lower than the upper surface of the semiconductor substrate;
the substrate extension layer is formed on the side wall of the groove which is not covered by the first dielectric layer and extends to cover part of the surface of the first dielectric layer; and
and the second dielectric layer is formed on the surfaces of the first dielectric layer and the substrate extension layer and at least fills the groove.
10. The semiconductor structure of claim 9, wherein the doped dielectric layer is formed by ion implantation and rapid thermal processing at the bottom and sidewalls of the trench.
11. The semiconductor structure of claim 10, wherein the ions implanted in the doped dielectric layer comprise oxygen ions.
12. The semiconductor structure of claim 11, wherein the ions implanted in the doped dielectric layer further comprise at least one of boron ions or chloride ions.
13. The semiconductor structure of claim 9, wherein an upper surface of said substrate extension layer is flush with an upper surface of said semiconductor substrate.
14. The semiconductor structure of claim 9, wherein the material of the substrate extension layer is the same as the material of the semiconductor substrate.
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