CN110957265A - Semiconductor interconnection structure and preparation method thereof - Google Patents
Semiconductor interconnection structure and preparation method thereof Download PDFInfo
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- CN110957265A CN110957265A CN201811132389.XA CN201811132389A CN110957265A CN 110957265 A CN110957265 A CN 110957265A CN 201811132389 A CN201811132389 A CN 201811132389A CN 110957265 A CN110957265 A CN 110957265A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000002360 preparation method Methods 0.000 title claims abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 123
- 239000002184 metal Substances 0.000 claims abstract description 123
- 238000000137 annealing Methods 0.000 claims abstract description 32
- 238000009713 electroplating Methods 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000011049 filling Methods 0.000 claims abstract description 17
- 238000007747 plating Methods 0.000 claims description 66
- 238000000034 method Methods 0.000 claims description 56
- 230000004888 barrier function Effects 0.000 claims description 43
- 230000008569 process Effects 0.000 claims description 31
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 19
- 229910052802 copper Inorganic materials 0.000 claims description 19
- 239000010949 copper Substances 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 19
- 229910052715 tantalum Inorganic materials 0.000 claims description 12
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 12
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 10
- MIMUSZHMZBJBPO-UHFFFAOYSA-N 6-methoxy-8-nitroquinoline Chemical compound N1=CC=CC2=CC(OC)=CC([N+]([O-])=O)=C21 MIMUSZHMZBJBPO-UHFFFAOYSA-N 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000000231 atomic layer deposition Methods 0.000 claims description 8
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 claims description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 5
- 239000001257 hydrogen Substances 0.000 claims description 5
- 229910052739 hydrogen Inorganic materials 0.000 claims description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 4
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 348
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 9
- 229910052721 tungsten Inorganic materials 0.000 description 9
- 239000010937 tungsten Substances 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229910002601 GaN Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a semiconductor interconnection structure and a preparation method thereof, comprising the following steps: 1) providing a substrate, forming a dielectric layer on the upper surface of the substrate, and forming a contact hole in the dielectric layer; 2) carrying out shape adjustment on the top opening of the contact hole to enable the side wall of the contact hole to comprise a vertical side wall and an inclined side wall; 3) forming a seed layer on the bottom, the vertical side wall, the inclined side wall and the upper surface of the dielectric layer of the contact hole; 4) forming a metal layer on the seed layer in the contact hole in an electroplating manner at least including multi-stage current density increasing; 5) and 4) annealing the structure obtained in the step 4) to enable the metal layer to fill the contact hole in a non-hole filling mode. The invention firstly adjusts the top appearance of the contact hole before filling the metal layer, thereby effectively avoiding the generation of overhang; and annealing treatment is carried out, so that the contact hole can be filled with the metal layer in a hole-free mode, the resistance value of the filled metal layer is reduced, and the reliability of the device is improved.
Description
Technical Field
The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a semiconductor interconnection structure and a preparation method thereof.
Background
In existing semiconductor processes, tungsten film deposition using a chemical vapor deposition process (CVD) is a common process in many semiconductor manufacturing. In the prior art, as shown in fig. 1, a dielectric layer 10, which is located on a substrate 10' and has a contact hole 11 formed therein, is generally heated to a process temperature in a vacuum chamber, and then an adhesion barrier layer 12 and a seed layer 13 are sequentially formed in the contact hole 11, and then a tungsten metal layer 14 is deposited in the contact hole 11.
However, as the miniaturization of the device is advanced, the size of the semiconductor interconnection structure is smaller and smaller, when the existing chemical vapor deposition process is used to fill the contact hole 11 with a high aspect ratio to form the tungsten metal layer 14 in one step, a hole 15 is easily formed in the tungsten metal layer 14 in the contact hole 11, the existence of the hole 15 may cause an electromigration problem in a subsequent copper process, and may cause a resistance value of the filled metal layer in the contact hole to be larger, thereby causing a decrease in reliability of the semiconductor device. In addition, when the tungsten metal layer 14 is filled in the contact hole 11, a metal wiring layer must be formed to be connected to the tungsten metal layer 14 to reduce the driving resistance of the device, and the formation of the metal wiring layer inevitably occupies the effective area in the dielectric layer 10, so that the effective area in the dielectric layer 10 becomes smaller.
Since copper has a lower resistivity than tungsten, filling copper in the contact hole 11 can reduce the driving resistance of the device without forming an additional metal wiring layer, however, for the contact hole 11 as shown in fig. 1, since the top of the contact hole 11 is right-angled (i.e., the sidewall of the contact hole 11 is vertically connected to the upper surface of the dielectric layer 10), before copper electroplating, overhang may be generated at the contact hole 11 when forming a barrier layer and a seed layer, so that a hole may be generated inside the filled copper when electroplating the filled copper, and the thickness of the filled copper in the edge region of the contact hole 11 is smaller, thereby causing electrical failure (EM/SM) of the device.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a semiconductor interconnect structure and a method for fabricating the same, which solve the above-mentioned problems in the prior art.
To achieve the above and other related objects, the present invention provides a method for fabricating a semiconductor interconnect structure, the method comprising the steps of:
1) providing a substrate, forming a dielectric layer on the upper surface of the substrate, and forming a contact hole in the dielectric layer;
2) carrying out shape adjustment on a top opening of the contact hole to enable the side wall of the contact hole to comprise a vertical side wall positioned at the lower part and an inclined side wall positioned at the upper part, wherein the vertical side wall is connected with the upper surface of the dielectric layer through the inclined side wall, the vertical side wall and the upper surface of the dielectric layer are obliquely crossed, and the transverse opening size of the upper part of the contact hole is larger than the transverse size of the lower part of the contact hole;
3) forming a seed layer on the bottom of the contact hole, the vertical side wall, the inclined side wall and the upper surface of the dielectric layer;
4) forming a metal layer on the seed layer in the contact hole in an electroplating manner at least comprising multi-stage current density increasing; and
5) and (4) annealing the structure obtained in the step (4) to enable the metal layer to reflow, and filling the contact hole with the metal layer in a non-porous filling manner.
As a preferred embodiment of the present invention, the aspect ratio of the contact hole formed in step 1) is greater than 5.
As a preferable aspect of the present invention, the sidewall of the contact hole formed in step 1) is perpendicular to the upper surface of the dielectric layer.
As a preferable embodiment of the present invention, in step 2), wet etching is performed on the top of the contact hole by using a mixture of ammonium bifluoride and ammonium fluoride with water or hydrogen peroxide to form the inclined sidewall.
As a preferred embodiment of the present invention, in step 2), the top of the contact hole is etched using argon gas to form the sloped sidewall.
As a preferable scheme of the invention, the method also comprises the following steps after the step 2) and before the step 3):
and forming a barrier layer on the upper surface of the dielectric layer, the bottom and the side wall of the contact hole.
As a preferred scheme of the invention, an atomic layer deposition process is adopted to deposit tantalum on the upper surface of the dielectric layer, the bottom and the side wall of the contact hole to serve as the barrier layer, and the thickness of the barrier layer is between 40 angstroms and 60 angstroms; the material of the seed layer is the same as that of the metal layer, and the thickness of the seed layer is between 100 angstroms and 200 angstroms.
As a preferred scheme of the invention, in the step 4), an electroplating process is adopted to gradually deposit metal copper from the bottom of the contact hole to the top to serve as the metal layer; the current density in the electroplating process is between 1.5 and 60 amperes, and the thickness of the metal layer formed by electroplating is between 9000 and 11000 amperes.
As a preferable aspect of the present invention, the step 4) includes the steps of:
4-1) forming a first electroplated layer in the contact hole under the condition of first current density;
4-2) forming a second electroplated layer on the upper surface of the first electroplated layer under the condition of second current density; and
4-3) forming a third electroplated layer on the upper surface of the second electroplated layer and the dielectric layer under a third current density condition; wherein,
the second current density is greater than the first current density and less than the third current density.
In a preferred embodiment of the present invention, the first current density is 1.5 to 3A, and the thickness of the first plating layer is 900 to 1100A; the second current density is between 5 and 15 amperes, and the thickness of the second electroplated layer is between 2500 and 3500 amperes; the third current density is 35-45A, and the thickness of the third electroplated layer is 5500-6500A.
As a preferable aspect of the present invention, in step 4), the metal layer is formed in the contact hole and on the dielectric layer.
As a preferable mode of the present invention, a hole is formed in the metal layer formed in the contact hole in step 4).
In a preferable embodiment of the present invention, in step 5), the structure obtained in step 4) is placed in a hydrogen atmosphere to perform an annealing treatment, wherein the annealing treatment temperature is between 300 ℃ and 500 ℃, and the annealing treatment time is between 15 minutes and 35 minutes.
As a preferable scheme of the present invention, after the step 5), the method further comprises the following steps: and removing the metal layer on the dielectric layer.
As a preferable mode of the present invention, in the step 2), the inclined sidewall is inclined at an angle of 20 to 25 degrees with respect to the vertical sidewall.
The present invention also provides a semiconductor interconnect structure comprising:
a substrate;
the dielectric layer is positioned on the upper surface of the substrate, a contact hole is formed in the dielectric layer, the side wall of the contact hole comprises a vertical side wall positioned at the lower part and an inclined side wall positioned at the upper part, the vertical side wall is connected with the upper surface of the dielectric layer through the inclined side wall, and the inclined side wall is obliquely crossed with the vertical side wall and the upper surface of the dielectric layer; the transverse opening size of the upper part of the contact hole is larger than that of the lower part of the contact hole;
a seed layer formed on the bottom of the contact hole, the vertical sidewall, the inclined sidewall and the upper surface of the dielectric layer; and
and the metal layer is formed in the contact hole in an electroplating mode at least comprising multi-stage current density increasing, and the metal layer is annealed on the seed layer, reflows and fills the contact hole in a non-hole filling mode.
In a preferred embodiment of the present invention, the material of the metal layer includes copper.
In a preferred embodiment of the present invention, the aspect ratio of the contact hole is greater than 5.
As a preferable aspect of the present invention, the present invention further includes:
and the barrier layer is positioned on the bottom and the side wall of the contact hole and positioned between the dielectric layer and the metal layer.
In a preferred embodiment of the present invention, the material of the barrier layer includes tantalum, and the material of the seed layer is the same as the material of the metal layer.
As a preferable scheme of the invention, the thickness of the barrier layer is between 40 and 60 angstroms; the thickness of the seed layer is between 100 angstroms and 200 angstroms.
As a preferable aspect of the present invention, the metal layer includes:
the first electroplated layer is positioned in the contact hole;
the second electroplated layer is positioned in the contact hole and positioned on the upper surface of the first electroplated layer; and
a third electroplated layer located on the upper surface of the second electroplated layer and the dielectric layer.
In a preferred embodiment of the present invention, the first plating layer is formed by plating under a first current density condition of 1.5 to 3 amperes, and the thickness of the first plating layer is 900 to 1100 amperes; the second electroplated layer is formed by electroplating under the condition of second current density between 5 and 15 amperes, and the thickness of the second electroplated layer is between 2500 angstroms and 3500 angstroms; the third electroplated layer is formed by electroplating under the condition of third current density between 35A and 45A, and the thickness of the third electroplated layer is between 5500A and 6500A.
As described above, the semiconductor interconnect structure and the method for manufacturing the same of the present invention have the following advantages:
according to the invention, the top appearance of the contact hole is adjusted before the metal layer is filled, so that the transverse size of the upper part of the contact hole obtained after adjustment is larger than that of the lower part of the contact hole, and the generation of overhang can be effectively avoided; after the metal layer is filled, annealing treatment is carried out, holes in the metal layer can be discharged, so that the contact holes are filled with the metal layer in a hole-free mode, the resistance value of the filled metal layer is reduced, and the reliability of the device is improved;
forming a barrier layer by adopting an atomic layer deposition process, so that the step coverage of the barrier layer is optimal; meanwhile, the thickness of the seed layer is minimized, so that the top obstacle of the contact hole can be effectively relieved;
the metal layer is formed by multi-step electroplating, the current density corresponding to the formation of the metal layer at the bottom is low, and the minimization of holes in the metal layer can be ensured in the process of forming the metal layer by electroplating.
Drawings
Fig. 1 is a schematic cross-sectional structure diagram of a structure obtained after filling a tungsten metal layer in a contact hole by using a chemical vapor deposition process in the prior art.
Fig. 2 is a flowchart illustrating a method for fabricating a semiconductor interconnect structure according to a first embodiment of the present invention.
Fig. 3 to 11 are schematic cross-sectional views illustrating steps of a method for fabricating a semiconductor interconnect structure according to a first embodiment of the present invention; fig. 11 is a schematic cross-sectional view of a semiconductor interconnect structure according to a second embodiment of the present invention.
Description of the element reference numerals
10' substrate
10 dielectric layer
11 contact hole
12 adhesion barrier layer
13 seed layer
14 tungsten metal layer
15 holes
2 base
20 dielectric layer
21 contact hole
221 vertical side wall
222 inclined side wall
23 Metal layer
231 first plating layer
232 second plating layer
233 third plating layer
24 holes
25 barrier layer
26 seed layer
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 2 to 11. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Example one
As shown in fig. 2, the present invention provides a method for manufacturing a semiconductor interconnect structure, which includes the following steps:
1) providing a substrate, forming a dielectric layer on the upper surface of the substrate, and forming a contact hole in the dielectric layer;
2) carrying out shape adjustment on a top opening of the contact hole to enable the side wall of the contact hole to comprise a vertical side wall positioned at the lower part and an inclined side wall positioned at the upper part, wherein the vertical side wall is connected with the upper surface of the dielectric layer through the inclined side wall, the vertical side wall and the upper surface of the dielectric layer are obliquely crossed, and the transverse opening size of the upper part of the contact hole is larger than the transverse size of the lower part of the contact hole;
3) forming a seed layer on the bottom of the contact hole, the vertical side wall, the inclined side wall and the upper surface of the dielectric layer;
4) forming a metal layer on the seed layer in the contact hole in an electroplating manner at least comprising multi-stage current density increasing; and
5) and (4) annealing the structure obtained in the step (4) to enable the metal layer to reflow, and filling the contact hole with the metal layer in a non-porous filling manner.
In step 1), referring to step S1 of fig. 2 and fig. 3, a substrate 2 is provided, a dielectric layer 20 is formed on the upper surface of the substrate 2, and a contact hole 21 is formed in the dielectric layer 20.
By way of example, the substrate 2 may be any one of the existing substrates, and the material of the substrate 2 may include, but is not limited to, silicon dioxide, gallium nitride, sapphire, or the like.
By way of example, the dielectric layer 20 may be any semiconductor interconnect structure known in the art that can form the contact hole 21 and the contact hole 21 needs to be filled, such as an interlayer dielectric layer of a semiconductor device, the contact hole 21 may be formed, and after the contact hole 21 is adjusted and filled, an electrical connection structure (e.g., a conductive plug) is formed to serve as an interconnect structure of an upper device layer and a lower device layer. The material of the dielectric layer 20 may include, but is not limited to, silicon oxide or silicon nitride, etc.
As an example, the number of the contact holes 21 formed in the dielectric layer 20 may be plural, and the plural contact holes 21 are arranged at intervals in the dielectric layer 20. The plurality of contact holes 21 may be arranged at equal intervals or at unequal intervals in the dielectric layer 20. Fig. 3 only illustrates that one contact hole 21 is formed in the dielectric layer 20, and the actual number of the contact holes 21 is not limited thereto.
As an example, the cross-sectional shape of the contact hole 21 may be set according to actual needs, and in this embodiment, the cross-sectional shape of the contact hole 21 may include any shape that can achieve filling, such as a rectangle or a U shape.
As an example, the contact hole 21 is preferably a contact hole with a high aspect ratio, and preferably, in this embodiment, the aspect ratio of the contact hole 21 may be greater than 5.
As an example, the contact hole 21 may be formed using a dry etching process or a wet etching process.
As an example, the sidewalls of the contact hole 21 are perpendicular to the upper surface of the dielectric layer 20.
In step 2), referring to step S2 in fig. 2 and fig. 4, a top opening of the contact hole 21 is profile-adjusted such that a sidewall of the contact hole 21 includes a vertical sidewall 221 located at a lower portion and an inclined sidewall 222 located at an upper portion, the vertical sidewall 221 is connected to an upper surface of the dielectric layer 20 through the inclined sidewall 222, the inclined sidewall 222 is oblique to both the vertical sidewall 222 and the upper surface of the dielectric layer 20, and a lateral opening size at the upper portion of the contact hole 21 is larger than a lateral size at the lower portion of the contact hole 21.
In one example, the top of the contact hole 21 may be wet etched using LAL (ammonium bifluoride and a mixture of ammonium fluoride and water or hydrogen peroxide) chemistry to form the sloped sidewall 222; for example, ammonium bifluoride (NH) can be used4HF2) Ammonium fluoride (NH)4F) And hydrogen peroxide (H)2O2) The mixed liquid carries out wet etching on the top of the contact hole 21, and in the mixed liquid, the mass percentages of ammonium bifluoride, ammonium fluoride and hydrogen peroxide are respectively as follows: 0.26%, 6.8% and 92.94%; ammonium bifluoride, ammonium fluoride and water (H) may also be used2O) is used for carrying out wet etching on the top of the contact hole 21, and in the mixed solution, the mass percentages of ammonium bifluoride, ammonium fluoride and water are respectively as follows: 11.4%, 12.6% and 76%. The lateral dimension of the slanted sidewall 222 (e.g., the diameter of the slanted sidewall 222) obtained after wet etching the contact hole 21 using the LAL chemistry is larger than the lateral dimension of the vertical sidewall 221, so that the contact hole 21 has a Profile (Positive Profile) as shown in fig. 4.
In another example, the top of the contact hole 21 may be dry etched using a dry etching process to form the sloped sidewall 222; for example, the top of the contact hole 21 may be etched using argon as an etching gas. The bias voltage and power used when the contact hole 21 having the inclined sidewall 222 is formed by dry etching the contact hole 21 are both greater than the bias voltage and power used when the contact hole 21 is formed by etching in step 1). Similarly, the lateral dimension of the upper portion of the contact hole 21 (e.g., the diameter of the lateral opening of the upper portion of the contact hole 21) obtained by dry etching the contact hole 21 by using a dry etching process is larger than the lateral dimension of the lower portion of the contact hole 21, i.e., the lateral dimension of the inclined sidewall 222 is larger than the lateral dimension of the vertical sidewall 221; the contact hole 21 obtained in this step has a morphology (Positive Profile) as shown in fig. 4.
By adjusting the top of the contact hole 21 to obtain the inclined sidewall 222, the generation of overhang can be effectively avoided, so that no hole is generated in the filled metal layer when the metal layer is filled in the contact hole 21 with the inclined sidewall 222 in the following process.
As an example, the inclined sidewall 222 is inclined at an angle α between 20 and 25 degrees compared to the vertical sidewall 221. uniformity problems can occur when the inclined sidewall 222 is inclined at an angle α of less than 20 degrees or greater than 25 degrees compared to the vertical sidewall 221.
As an example, the following steps are also included after the step 2):
a barrier layer 25 is formed on the top surface of the dielectric layer 20, the bottom and sidewalls of the contact hole 21, as shown in fig. 5.
As an example, an Atomic Layer Deposition (ALD) process may be used to deposit tantalum (Ta) on the upper surface of the dielectric layer 20, the bottom of the contact hole 21 and then as the barrier layer 25, and the thickness of the barrier layer 25 may be between 40 angstroms and 60 angstroms, and preferably, in this embodiment, the thickness of the barrier layer 25 may be 50 angstroms. Tantalum does not react with copper, thermal stability is very good, and adhesion between tantalum and copper and other dielectric layers is optimal, which can be achieved by selecting tantalum as the barrier layer 25. The barrier layer 25 is formed by an atomic layer deposition process, so that the step coverage of the barrier layer 25 is optimal.
It should be noted that the above and subsequent references to "between …" refer to a range of values including both endpoints, for example, the above reference to "between 40 angstroms and 60 angstroms" refers to a range of values including both 40 and 60 endpoints.
In step 3), referring to step S3 in fig. 2 and fig. 6, a seed layer 26 is formed on the bottom of the contact hole 21, the vertical sidewall 221, the inclined sidewall 222 and the upper surface of the dielectric layer 20.
As an example, the seed layer 26 may be formed by using a Physical Vapor Deposition (PVD) process, a material of the seed layer 26 is the same as that of the metal layer 23, and a thickness of the seed layer 26 is between 100 angstroms and 200 angstroms, and preferably, in this embodiment, the thickness of the seed layer may be 150 angstroms. The thickness of the seed layer 26 is minimized, and the top barrier of the contact hole 21 can be effectively reduced.
In step 4), referring to step S4 in fig. 2 and fig. 7 to 9, the metal layer 23 formed on the seed layer 26 is formed in the contact hole 21 by electroplating at least including multi-stage current density increase.
As an example, the hole 24 is formed in the metal layer 23 formed in the contact hole 21.
As an example, an electroplating process may be employed to gradually deposit metallic copper as the metal layer 23 from the bottom of the contact hole 21 up; the current density in the electroplating process is between 1.5 and 60 amperes, and the thickness of the metal layer 23 formed by electroplating is between 9000 and 11000 amperes.
As an example, step 3) comprises the following steps:
4-1) forming a first plating layer 231 in the contact hole 21 under the condition of a first current density, as shown in fig. 7, wherein the first plating layer 231 fills the bottom of the contact hole 21;
4-2) forming a second plating layer 232 on the upper surface of the first plating layer 231 under a second current density condition, as shown in fig. 8, wherein the second plating layer 232 may fill part of the contact hole 21 or may fill the contact hole 21; and
4-3) forming a third electroplated layer 233 on the upper surface of the second electroplated layer 232 and the dielectric layer 20 under a third current density condition, as shown in fig. 9, wherein the hole 24 is formed in the third electroplated layer 233; wherein the second current density is greater than the first current density and less than the third current density. Of course, in other examples, the hole 24 may be formed in the first electroplating layer 231 and the second electroplating layer 232.
It should be noted that, in an example, the first plating layer 231 may be located on the bottom, the sidewall of the contact hole 21 and the upper surface of the dielectric layer 20, and at this time, the thickness of the first plating layer 231 located on the bottom of the contact hole 21 is much greater than the thickness of the first plating layer 231 located on the sidewall of the contact hole 21 and the upper surface of the dielectric layer 20, as shown in fig. 7; the second plating layer 232 may be located on the bottom, sidewalls of the contact hole 21 and the upper surface of the dielectric layer 20, in which case the thickness of the second plating layer 232 located on the bottom of the contact hole 21 is much greater than the thickness of the second plating layer 232 located on the sidewalls of the contact hole 21 and the upper surface of the dielectric layer 20, as shown in fig. 8. In another example, the first plating layer 231 may be filled in the bottom of the contact hole 21 from bottom to top only from the bottom of the contact hole 21, and the second plating layer 232 may be located on the upper surface of the first plating layer 231 and only in the contact hole 21.
By way of example, the first current density is between 1.5 a and 3 a, the thickness of the first plating layer 231 is between 900 a and 1100 a, and preferably, in the embodiment, the thickness of the first plating layer 231 may be 1000 a; the second current density is between 5 amperes and 15 amperes, the thickness of the second electroplated layer 232 is between 2500 angstroms and 3500 angstroms, preferably, in the embodiment, the second current density can be 10 amperes, and the thickness of the second electroplated layer 232 can be 3000 amperes; the third current density is 35 a-45 a, the thickness of the third plating layer is 5500 a-6500 a, preferably, in this embodiment, the third current density may be 40 a, and the thickness of the third plating layer 233 may be 6000 a.
As an example, in the step 4-2), forming the second plating layer 232 on the upper surface of the first plating layer 231 under the second current density condition may be performed in two cycles, for example, the second plating layer 232 with a first thickness (e.g., 1500 a) may be formed on the upper surface of the first plating layer 231 under the second current density condition, and then another second plating layer 232 with a second thickness (e.g., 1500 a) may be formed on the upper surface of the second plating layer 232.
The metal layer 23 is formed by electroplating in multiple steps, and the current density for forming the metal layer 23 at the bottom of the contact hole 21 is lower than the current density for forming the metal layer 23 above the contact hole, and the lower the current density is, the slower the deposition rate of the metal layer 23 is, which can ensure the minimization of the hole 24 filled in the metal layer 23 at the lower part of the contact hole 21, because the hole 24 filled in the metal layer 23 at the lower part of the contact hole 21 is difficult to remove in the subsequent annealing process, and the residue of the hole 24 in the metal layer 23 is difficult to avoid.
When the barrier layer 25 and the seed layer 26 are formed on the dielectric layer 20, the metal layer 23 is formed on the upper surface of the seed layer 26.
In step 5), referring to step S5 in fig. 2 and fig. 10, the structure obtained in step 4) is annealed, so that the metal layer 23 is reflowed, and the metal layer 23 fills the contact hole 21 in a void-free filling manner.
As an example, the structure obtained in step 4) is placed in a hydrogen atmosphere to perform annealing treatment, but in other examples, the structure obtained in step 4) may be placed in a reducing atmosphere of another reducing gas to perform annealing treatment. Preferably, in this embodiment, the structure obtained in step 4) is placed in a hydrogen atmosphere for annealing treatment, because the optimal gas for reducing the Gibbs Free Energy (Gibbs Free Energy) of copper reflow is hydrogen under the optimal annealing temperature condition (e.g., 300 ℃ to 500 ℃), and the optimal reflow effect of copper under the annealing condition can be achieved.
As an example, the temperature of the annealing treatment is between 300 ℃ and 500 ℃, and the time of the annealing treatment is between 15 minutes and 35 minutes; preferably, in this embodiment, the temperature of the annealing treatment includes 400 ℃, and the time of the annealing treatment includes 30 minutes.
The metal layer 23 filled in the contact hole 21 is annealed, the metal layer 23 reflows under the annealing condition, and the hole 24 in the metal layer 23 can be discharged, so that the metal layer 23 fills the contact hole 21 in a hole-free manner, thereby reducing the resistance value of the filled metal layer 23 and improving the reliability of the device.
As an example, as shown in fig. 11, after step 5), the following steps are further included: the metal layer 23 on the dielectric layer 20 (i.e., above the upper surface of the dielectric layer 20) is removed. Specifically, the metal layer 23 on the dielectric layer 20 may be removed by, but not limited to, a Chemical Mechanical Polishing (CMP) process.
It should be noted that, when the barrier layer 25 and the seed layer 26 are formed on the dielectric layer 20, the barrier layer 25 and the seed layer 26 on the dielectric layer 20 are removed at the same time.
It should be further noted that the metal layer 23 is shown in fig. 11 as a whole, and the first plating layer 231, the second plating layer 232, and the third plating layer 233 are not specifically shown.
Example two
With continuing reference to fig. 10 to 11 with reference to fig. 2 to 9, the present invention further provides a semiconductor interconnect structure, including:
a substrate 2;
a dielectric layer 20, wherein the dielectric layer 20 is located on the upper surface of the substrate 2, a contact hole 21 is formed in the dielectric layer 20, the sidewall of the contact hole 21 includes a vertical sidewall 221 located at the lower part and an inclined sidewall 222 located at the upper part, the vertical sidewall 221 is connected with the upper surface of the dielectric layer 20 through the inclined sidewall 222, and the inclined sidewall 222 is oblique to the vertical sidewall 221 and the upper surface of the dielectric layer 20; the transverse opening size of the upper part of the contact hole 21 is larger than that of the lower part of the contact hole 21;
a seed layer 26, the seed layer 26 being formed on the bottom of the contact hole 21, the vertical sidewall 221, the inclined sidewall 222, and the upper surface of the dielectric layer; and
the metal layer 23 is formed in the contact hole 21 in an electroplating manner at least comprising multi-stage current density increasing, and the metal layer 23 is annealed on the seed layer 26 to generate reflux so as to fill the contact hole 21 in a non-hole filling manner.
By way of example, the substrate 2 may be any one of the existing substrates, and the material of the substrate 2 may include, but is not limited to, silicon dioxide, gallium nitride, sapphire, or the like.
By way of example, the dielectric layer 20 may be any semiconductor interconnect structure known in the art that can form the contact hole 21 and the contact hole 21 needs to be filled, such as an interlayer dielectric layer of a semiconductor device, the contact hole 21 may be formed, and after the contact hole 21 is adjusted and filled, an electrical connection structure (e.g., a conductive plug) is formed to serve as an interconnect structure of an upper device layer and a lower device layer. The material of the dielectric layer 20 may include, but is not limited to, silicon oxide or silicon nitride, etc.
As an example, the number of the contact holes 21 formed in the dielectric layer 20 may be plural, and the plural contact holes 21 are arranged at intervals in the dielectric layer 20. The plurality of contact holes 21 may be arranged at equal intervals or at unequal intervals in the dielectric layer 20. Fig. 3 only illustrates that one contact hole 21 is formed in the dielectric layer 20, and the actual number of the contact holes 21 is not limited thereto.
As an example, the contact hole 21 is preferably a contact hole with a high aspect ratio, and preferably, in this embodiment, the aspect ratio of the contact hole 21 may be greater than 5.
As an example, the inclined sidewall 222 is inclined at an angle α between 20 and 25 degrees compared to the vertical sidewall 221. uniformity problems can occur when the inclined sidewall 222 is inclined at an angle α of less than 20 degrees or greater than 25 degrees compared to the vertical sidewall 221.
The lateral opening size of the upper portion of the contact hole 21 is larger than the lateral size of the lower portion (i.e. the lateral size of the inclined sidewall 222 is larger than the lateral size of the vertical sidewall 221), which can effectively avoid the generation of overhang, so that no hole is generated inside the filled metal layer when the metal layer is filled in the contact hole 21 in the following step.
As an example, the material of the metal layer 23 may include copper.
As an example, the metal layer 23 includes:
a first plating layer 231, the first plating layer 231 being located within the contact hole 21;
a second plating layer 232, the second plating layer 232 being located within the contact hole 21 and on an upper surface of the first plating layer 231; and
a third electroplated layer 233, said third electroplated layer 233 being located on the upper surface of said second electroplated layer 232 and on said dielectric layer 20.
By way of example, the first plating layer 231 is formed by plating under a first current density condition of 1.5 to 3 amperes, the thickness of the first plating layer 231 is 900 to 1100 amperes, and preferably, in the embodiment, the thickness of the first plating layer 231 may be 1000 angstroms; the second plating layer 232 is formed by plating under the condition of a second current density of between 5 and 15 amperes, the thickness of the second plating layer 232 is between 2500 and 3500 amperes, preferably, in the embodiment, the second current density can be 10 amperes, and the thickness of the second plating layer 232 can be 3000 amperes; the third plating layer 233 is formed by plating under a third current density condition of 35 a to 45 a, the thickness of the third plating layer 233 is 5500 a to 6500 a, preferably, in the present embodiment, the third current density may be 40 a, and the thickness of the third plating layer 233 may be 6000 a. The second plating layer 232 may fill part of the contact hole 21, or may fill the contact hole 21.
In an example, the first plating layer 231 may be located on the bottom, the sidewall of the contact hole 21 and the upper surface of the dielectric layer 20, and at this time, the thickness of the first plating layer 231 located on the bottom of the contact hole 21 is much greater than the thickness of the first plating layer 231 located on the sidewall of the contact hole 21 and the upper surface of the dielectric layer 20; the second plating layer 232 may be located on the bottom, sidewalls of the contact hole 21 and the upper surface of the dielectric layer 20, in which case the thickness of the second plating layer 232 located on the bottom of the contact hole 21 is much greater than the thickness of the second plating layer 232 located on the sidewalls of the contact hole 21 and the upper surface of the dielectric layer 20, as shown in fig. 9. In another example, the first plating layer 231 may be filled in the bottom of the contact hole 21 from bottom to top only from the bottom of the contact hole 21, and the second plating layer 232 may be located on the upper surface of the first plating layer 231 and only in the contact hole 21.
The metal layer 23 is formed by electroplating in multiple steps, and the current density for forming the metal layer 23 at the bottom of the contact hole 21 is lower than the current density for forming the metal layer 23 above the contact hole, and the lower the current density is, the slower the deposition rate of the metal layer 23 is, which can ensure the minimization of the hole 24 filled in the metal layer 23 at the lower part of the contact hole 21, because the hole 24 filled in the metal layer 23 at the lower part of the contact hole 21 is difficult to remove in the subsequent annealing process, and the residue of the hole 24 in the metal layer 23 is difficult to avoid.
Illustratively, the metal layer 23 is formed by annealing after multi-step electroplating, the temperature of the annealing is between 300 and 500 ℃, and the time of the annealing is between 15 and 35 minutes; preferably, in this embodiment, the temperature of the annealing treatment includes 400 ℃, and the time of the annealing treatment includes 30 minutes.
The metal layer 23 electroplated and filled in the contact hole 21 is annealed, the metal layer 23 reflows under the annealing condition, and the hole 24 in the metal layer 23 can be discharged, so that the metal layer 23 fills the contact hole 21 in a hole-free manner, thereby reducing the resistance value of the filled metal layer 23 and improving the reliability of the device.
As an example, the semiconductor interconnect structure further includes:
a barrier layer 25, the barrier layer 25 being located on the bottom and sidewalls of the contact hole 21 and between the dielectric layer 20 and the metal layer 23.
As an example, the material of the barrier layer 25 may include tantalum, and the thickness of the barrier layer 25 may be between 40 angstroms and 60 angstroms, and preferably, in this embodiment, the thickness of the barrier layer 25 may be 50 angstroms. Tantalum does not react with copper, thermal stability is very good, and adhesion between tantalum and copper and other dielectric layers is optimal, which can be achieved by selecting tantalum as the barrier layer 25. The barrier layer 25 is formed by an atomic layer deposition process, so that the step coverage of the barrier layer 25 is optimal.
The material of the seed layer 26 is the same as the material of the metal layer 23, and the thickness of the seed layer 26 is between 100 angstroms and 200 angstroms, preferably, in this embodiment, the thickness of the seed layer may be 150 angstroms. The thickness of the seed layer 26 is minimized, and the top barrier of the contact hole 21 can be effectively reduced.
It should be noted that the above-mentioned "between …" means the range including both endpoints, for example, the above-mentioned "between 100 angstroms and 200 angstroms" means the range including both 100 and 200 endpoints.
In one example, as shown in fig. 10, the metal layer 23, the barrier layer 25 and the seed layer 26 are not only located in the contact hole 21, but also located on the upper surface of the dielectric layer 20.
In another example, as shown in fig. 11, the metal layer 23, the barrier layer 25 and the seed layer 26 are only located in the contact hole 21, that is, the upper surfaces of the metal layer 23, the barrier layer 25 and the seed layer 26 are all flush with the upper surface of the dielectric layer 20.
In fig. 11, the metal layer 23 is shown as a whole, and the first plating layer 231, the second plating layer 232, and the third plating layer 233 are not specifically shown.
In summary, the present invention provides a semiconductor interconnect structure and a method for fabricating the same, wherein the method for fabricating the semiconductor interconnect structure comprises the following steps: 1) providing a substrate, forming a dielectric layer on the upper surface of the substrate, and forming a contact hole in the dielectric layer; 2) carrying out shape adjustment on a top opening of the contact hole to enable the side wall of the contact hole to comprise a vertical side wall positioned at the lower part and an inclined side wall positioned at the upper part, wherein the vertical side wall is connected with the upper surface of the dielectric layer through the inclined side wall, the vertical side wall and the upper surface of the dielectric layer are obliquely crossed, and the transverse opening size of the upper part of the contact hole is larger than the transverse size of the lower part of the contact hole; 3) forming a seed layer on the bottom of the contact hole, the vertical side wall, the inclined side wall and the upper surface of the dielectric layer; 4) forming a metal layer on the seed layer in the contact hole in an electroplating manner at least comprising multi-stage current density increasing; and 5) annealing the structure obtained in the step 4) to enable the metal layer to reflow, and filling the contact hole with the metal layer in a non-porous filling mode. According to the invention, the top appearance of the contact hole is adjusted before the metal layer is filled, so that the transverse size of the upper part of the contact hole obtained after adjustment is larger than that of the lower part of the contact hole, and the generation of overhang can be effectively avoided; after the metal layer is filled, annealing treatment is carried out, holes in the metal layer can be discharged, so that the contact holes are filled with the metal layer in a hole-free mode, the resistance value of the filled metal layer is reduced, and the reliability of the device is improved; forming a barrier layer by adopting an atomic layer deposition process, so that the step coverage of the barrier layer is optimal; meanwhile, the thickness of the seed layer is minimized, so that the top obstacle of the contact hole can be effectively relieved; the metal layer is formed by multi-step electroplating, the current density corresponding to the formation of the metal layer at the bottom is low, and the minimization of holes in the metal layer can be ensured in the process of forming the metal layer by electroplating.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (23)
1. A preparation method of a semiconductor interconnection structure is characterized by comprising the following steps:
1) providing a substrate, forming a dielectric layer on the upper surface of the substrate, and forming a contact hole in the dielectric layer;
2) carrying out shape adjustment on a top opening of the contact hole to enable the side wall of the contact hole to comprise a vertical side wall positioned at the lower part and an inclined side wall positioned at the upper part, wherein the vertical side wall is connected with the upper surface of the dielectric layer through the inclined side wall, the vertical side wall and the upper surface of the dielectric layer are obliquely crossed, and the transverse opening size of the upper part of the contact hole is larger than the transverse size of the lower part of the contact hole;
3) forming a seed layer on the bottom of the contact hole, the vertical side wall, the inclined side wall and the upper surface of the dielectric layer;
4) forming a metal layer on the seed layer in the contact hole in an electroplating manner at least comprising multi-stage current density increasing; and
5) and (4) annealing the structure obtained in the step (4) to enable the metal layer to reflow, and filling the contact hole with the metal layer in a non-porous filling manner.
2. The method for preparing a semiconductor interconnection structure according to claim 1, wherein the contact hole formed in step 1) has an aspect ratio of more than 5.
3. The method of claim 1, wherein the sidewalls of the contact hole formed in step 1) are perpendicular to the upper surface of the dielectric layer.
4. The method for manufacturing a semiconductor interconnection structure according to claim 1, wherein in step 2), the top of the contact hole is wet etched using ammonium bifluoride and a mixture of ammonium fluoride and water or hydrogen peroxide to form the sloped sidewall.
5. The method for manufacturing a semiconductor interconnect structure according to claim 1, wherein in step 2), the top of the contact hole is etched using argon gas to form the sloped sidewall.
6. The method for preparing a semiconductor interconnect structure according to claim 1, further comprising the following steps after step 2) and before step 3):
and forming a barrier layer on the upper surface of the dielectric layer, the bottom and the side wall of the contact hole.
7. The method of claim 6, wherein an atomic layer deposition process is used to deposit tantalum as the barrier layer on the upper surface of the dielectric layer, the bottom of the contact hole and the sidewall, wherein the thickness of the barrier layer is between 40 angstroms and 60 angstroms; the material of the seed layer is the same as that of the metal layer, and the thickness of the seed layer is between 100 angstroms and 200 angstroms.
8. The method for manufacturing a semiconductor interconnection structure according to claim 1, wherein in step 4), a plating process is used to gradually deposit copper metal as the metal layer from the bottom of the contact hole to the top; the current density in the electroplating process is between 1.5 and 60 amperes, and the thickness of the metal layer formed by electroplating is between 9000 and 11000 amperes.
9. The method for manufacturing a semiconductor interconnect structure according to claim 8, wherein the step 4) comprises the steps of:
4-1) forming a first electroplated layer in the contact hole under the condition of first current density;
4-2) forming a second electroplated layer on the upper surface of the first electroplated layer under the condition of second current density; and
4-3) forming a third electroplated layer on the upper surface of the second electroplated layer and the dielectric layer under a third current density condition; wherein,
the second current density is greater than the first current density and less than the third current density.
10. The method of claim 9, wherein the first current density is between 1.5A and 3A, and the thickness of the first plating layer is between 900A and 1100A; the second current density is between 5 and 15 amperes, and the thickness of the second electroplated layer is between 2500 and 3500 amperes; the third current density is 35-45A, and the thickness of the third electroplated layer is 5500-6500A.
11. The method as claimed in claim 1, wherein in step 4), the metal layer is formed in the contact hole and on the dielectric layer.
12. The method as claimed in claim 1, wherein a hole is formed in the metal layer formed in the contact hole in step 4).
13. The method for preparing a semiconductor interconnection structure according to claim 1, wherein in the step 5), the structure obtained in the step 4) is placed in a hydrogen atmosphere for annealing, the annealing temperature is between 300 ℃ and 500 ℃, and the annealing time is between 15 minutes and 35 minutes.
14. The method for manufacturing a semiconductor interconnect structure according to claim 1, further comprising, after the step 5), the steps of: and removing the metal layer on the dielectric layer.
15. The method as claimed in any one of claims 1 to 14, wherein in step 2), the inclined sidewall is inclined at an angle of 20 to 25 degrees with respect to the vertical sidewall.
16. A semiconductor interconnect structure, comprising:
a substrate;
the dielectric layer is positioned on the upper surface of the substrate, a contact hole is formed in the dielectric layer, the side wall of the contact hole comprises a vertical side wall positioned at the lower part and an inclined side wall positioned at the upper part, the vertical side wall is connected with the upper surface of the dielectric layer through the inclined side wall, and the inclined side wall is obliquely crossed with the vertical side wall and the upper surface of the dielectric layer; the transverse opening size of the upper part of the contact hole is larger than that of the lower part of the contact hole;
a seed layer formed on the bottom of the contact hole, the vertical sidewall, the inclined sidewall and the upper surface of the dielectric layer; and
and the metal layer is formed in the contact hole in an electroplating mode at least comprising multi-stage current density increasing, and the metal layer is annealed on the seed layer, reflows and fills the contact hole in a non-hole filling mode.
17. The semiconductor interconnect structure of claim 16, wherein the material of the metal layer comprises copper.
18. The semiconductor interconnect structure of claim 16, wherein the contact hole has an aspect ratio greater than 5.
19. The semiconductor interconnect structure of claim 16, further comprising:
and the barrier layer is positioned on the bottom and the side wall of the contact hole and positioned between the dielectric layer and the metal layer.
20. The semiconductor interconnect structure of claim 19, wherein the material of the barrier layer comprises tantalum, and the material of the seed layer is the same as the material of the metal layer.
21. The semiconductor interconnect structure of claim 20, wherein the barrier layer has a thickness of between 40 and 60 angstroms; the thickness of the seed layer is between 100 angstroms and 200 angstroms.
22. The semiconductor interconnect structure of claim 16, wherein the metal layer comprises:
the first electroplated layer is positioned in the contact hole;
the second electroplated layer is positioned in the contact hole and positioned on the upper surface of the first electroplated layer; and
a third electroplated layer located on the upper surface of the second electroplated layer and the dielectric layer.
23. The semiconductor interconnect structure of claim 22, wherein the first electroplated layer is electroplated at a first current density of between 1.5 a and 3 a, the first electroplated layer having a thickness of between 900 a and 1100 a; the second electroplated layer is formed by electroplating under the condition of second current density between 5 and 15 amperes, and the thickness of the second electroplated layer is between 2500 angstroms and 3500 angstroms; the third electroplated layer is formed by electroplating under the condition of third current density between 35A and 45A, and the thickness of the third electroplated layer is between 5500A and 6500A.
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| CN112259499A (en) * | 2020-10-20 | 2021-01-22 | 长江存储科技有限责任公司 | Semiconductor device and method for manufacturing the same |
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