CN110930920B - Display device and driving method thereof - Google Patents
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The invention provides a display device, which comprises a display panel, a driving chip, a data memory and a time schedule controller, wherein the time schedule controller is used for reading and writing a speckle removing compensation value by using a first working frequency and the data memory when the working state of the display device is a debugging state; when the working state of the display device is a starting state, reading and writing the speckle reduction compensation value by using a second working frequency and the data memory, wherein the first working frequency is less than the second working frequency; the working state of the display device is detected in real time through the time schedule controller, if the display device is in a starting state, the time schedule controller uses higher frequency to communicate with the data memory, so that the starting time of a product is ensured to meet the requirement, if the display device is in a debugging state before leaving a factory, the time schedule controller can execute reset operation and uses lower frequency to communicate with the data memory, so that the interference of a GOA signal to the time schedule controller can be reduced, and the normal communication of the time schedule controller can be ensured.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display device and a driving method thereof.
Background
With the increasing size of display panels, in the manufacturing process of display panels, the phenomenon of uneven display of panel brightness caused by manufacturing process defects often occurs, i.e. Mura (spots) exist, and as the quality requirements of users on display devices are higher and higher, de-Mura (spot removal) technology is introduced, after the display panels are produced, in the adjustment of a back-end system, the uniformity of the panel can be improved by setting and adjusting the gray scale coefficient (Gama) of a spot area to be consistent with the gray scale coefficient of a normal area, the image quality is improved, and color de-Mura (color spot removal) technology is required to be introduced for color spots such as color cast. Usually, the de-speckle compensation value is stored in a data memory, from which the timing controller reads the corresponding data when compensation is needed.
In a factory debugging stage, because a GOA signal displayed by a driving panel is a high-voltage signal, if the communication frequency of reading and writing data between a time schedule controller and a data memory is too high, the GOA signal can be interfered, and communication abnormity can be caused, however, after a product leaves a factory, because a spot removing value needs to be read in a starting state, the data volume of colored spots is 2-3 times of the data volume of normal spots, and the reading and writing efficiency can be influenced due to too low communication frequency, namely, the starting time of the display device is directly influenced.
In summary, in the display device of the prior art, because in the factory debugging stage, the timing controller will suffer from the interference of the GOA signal if adopting the high-frequency communication, and in the factory starting stage, the timing controller will influence the starting time if adopting the low-frequency communication. Therefore, it is necessary to improve this defect.
Disclosure of Invention
The embodiment of the invention provides a display device, which is used for solving the technical problems that in a factory debugging stage, a time schedule controller suffers interference of GOA signals if high-frequency communication is adopted, and in a factory starting stage, the time schedule controller affects starting time if low-frequency communication is adopted.
An embodiment of the present invention provides a display device, including: a display panel; the driving chip is used for driving the display panel; a data storage storing a speckle removal compensation value; the time schedule controller is used for reading and writing the speckle removing compensation value and sending the speckle removing compensation value to the driving chip; the time sequence controller is used for reading and writing the speckle reduction compensation value by using a first working frequency and the data memory when the working state of the display device is a debugging state; and when the working state of the display device is a starting state, reading and writing the speckle reduction compensation value by using a second working frequency and the data memory, wherein the first working frequency is less than the second working frequency.
Further, the display device further comprises an interface connector, the interface connector is used for transmitting a compensation instruction sent by the central processing unit to the time sequence controller, and the time sequence controller is used for determining the working state according to the compensation instruction.
Further, the compensation instruction comprises a power-on instruction and a reset instruction, and the time sequence controller is configured to determine that the working state is the power-on state when the compensation instruction is the power-on instruction; and when the compensation instruction is a reset instruction, determining that the working state is a debugging state.
Further, the second operating frequency is twice the first operating frequency.
Further, the time schedule controller is connected with the data memory through a serial peripheral interface bus.
Further, the data memory is a flash memory.
Furthermore, the display device further comprises a pulse width modulation circuit, wherein the pulse width modulation circuit is used for outputting a driving electric signal, and the pulse width modulation circuit is electrically connected with the driving chip.
Further, the pulse width modulation circuit includes an oscillator, an error amplifier, and a pulse width comparator.
Further, the driving chip includes a source driving chip and a gate driving chip, the source driving chip is configured to provide a data signal to the display panel, and the gate driving chip is configured to provide a scan signal to the display panel.
The embodiment of the invention provides a driving method of a display device, which comprises the following steps: providing a display device, which comprises a display panel, a driving chip, a data memory and a time schedule controller, wherein the driving chip is used for driving the display panel, the data memory stores a speckle removing compensation value, and the time schedule controller is used for reading and writing the speckle removing compensation value and sending the speckle removing compensation value to the driving chip; the time schedule controller judges the working state of the display device, if the working state is a debugging state, the time schedule controller executes reset operation, and reads and writes the speckle removing compensation value by using a first working frequency and the data memory; and if the working state is the starting-up state, the time schedule controller uses a second working frequency and the data memory to read and write the speckle reduction compensation value, and the first working frequency is smaller than the second working frequency.
Has the beneficial effects that: according to the display device provided by the embodiment of the invention, the working state of the display device is detected in real time through the time schedule controller, if the display device is in the starting state, the time schedule controller uses higher frequency to communicate with the data memory, so that the starting time of a product is ensured to meet the requirement, and if the display device is in the debugging state before leaving the factory, the time schedule controller can execute reset operation and uses lower frequency to communicate with the data memory, so that the interference of a GOA signal to the time schedule controller can be reduced, and the normal communication of the time schedule controller can be ensured.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a block diagram of a display device according to an embodiment of the invention;
fig. 2 is a flowchart of a driving method of a display device according to an embodiment of the invention;
fig. 3 is a block diagram of a display device according to a second embodiment of the present invention;
fig. 4 is a driving flow diagram of a display device according to a second embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the process of engineering manufacture of a display panel, pressure, scratch, offset, vibration and pollution caused by equipment and tools, or pixel characteristic changes caused by the influence of ambient temperature and driving conditions may finally cause corresponding display unevenness to be seen during display monitoring, so that various traces caused by uneven brightness appear on a display screen, which are collectively referred to as spots, and the expression forms of the spots are mainly three: a display portion that is slightly dark in a white screen, a display portion that is slightly white in a dark screen, or a display portion that is visible or bright or dark in an intermediate gray-scale screen, and display unevenness is a very common phenomenon that affects display quality, and causes of formation are intricate and complicated.
As the quality of display devices is more and more demanding for users, the skilled person introduces a speckle reduction technique, after the display panel is produced, the uniformity of the panel can be improved by adjusting the gray scale coefficient setting of the spot area to be consistent with the gray scale coefficient setting of the normal area in the adjustment of the back-stage system, namely, in the factory debugging stage, an optimal despeckle compensation value is found in a sample database, the optimal despeckle compensation value is recorded in a data storage, the brightness of the spot area is compensated as a despeckle compensation value after the display device is shipped from the factory, however, in the display device of the prior art, because the timing controller will suffer from interference of GOA signal if high frequency communication is adopted in the factory debugging stage, and in the factory startup stage, if the time schedule controller adopts low-frequency communication, the startup time is influenced, and the defect can be solved by the embodiment.
As shown in fig. 1, a structural block diagram of a display device according to a first embodiment of the present invention is provided, in which components of the display device and relative position relationships between the components can be seen visually, the display device includes a display panel 101, a driving chip 102, a data storage 103, and a timing controller 104, the driving chip 102 is configured to drive the display panel 101, the data storage 103 stores a speckle reduction compensation value, the timing controller 104 is configured to read and write the speckle reduction compensation value and send the speckle reduction compensation value to the driving chip 102, where the timing controller 104 is configured to read and write the speckle reduction compensation value with the data storage 103 by using a first operating frequency when an operating state of the display device is a debug state; and when the working state of the display device is a power-on state, reading and writing the speckle reduction compensation value by using a second working frequency and the data memory 103, wherein the first working frequency is less than the second working frequency, and specifically, the second working frequency is twice as high as the first working frequency.
In one embodiment, the display panel 101 includes scan lines distributed along a first direction, data lines distributed along a second direction, and subpixels disposed on the scan lines and the data lines, wherein the scan lines are used for turning on or off pixel channels in a certain row, and the data lines are used for inputting voltage data and controlling gray-scale values, i.e., light emission colors, of the subpixels; the driving chip 102 includes a source driving chip and a gate driving chip, the source driving chip is configured to provide a data signal to the display panel 101 through the data line, and the gate driving chip is configured to provide a scan signal to the display panel 101 through the scan line.
In one embodiment, the timing controller 104 is mainly composed of six unit circuits, i.e., a power control circuit, a power conversion circuit, a mechanical dial (minute, second) timing circuit, and a digital trigger; the power control circuit of the time sequence controller 104 outputs electric energy at any time within 0 to 99 seconds or electric energy at any time within 0 to 99 minutes according to control signals output by the mechanical dial (second) timing circuit and the mechanical dial (minute) timing circuit; the time schedule controller 104 is connected with the data memory 103 through a serial peripheral interface bus, the serial peripheral interface bus is a high-speed, full-duplex and synchronous communication bus, and only four lines are occupied on pins of a chip, so that the pins of the chip are saved, and meanwhile, the space is saved on the layout of a printed circuit board; the data memory 103 is a flash memory which is a form of eeprom that allows multiple erasing or writing in operation and has non-volatility, i.e., it does not require power consumption in terms of a single finger holding data, and is different from a conventional eeprom in that it performs data erasing in a large block, whereas a conventional eeprom can perform erasing and rewriting only a single memory location, which makes the flash memory significantly advantageous in writing a large amount of data.
In one embodiment, the display device further comprises an interface connector 105, the interface connector 105 is configured to transmit a compensation command sent by a central processing unit to the timing controller 104, and the timing controller 104 is configured to determine the operating state according to the compensation command; the compensation instruction comprises a starting instruction and a reset instruction, and the timing controller 104 is configured to determine that the working state is a starting state when the compensation instruction is the starting instruction; and when the compensation instruction is a reset instruction, determining that the working state is a debugging state.
In one embodiment, the display device further includes a pulse width modulation circuit 106, the pulse width modulation circuit 106 is configured to output a driving electrical signal, the driving electrical signal is a gate driving signal, the pulse width modulation circuit 106 is electrically connected to the driving chip 102, that is, the pulse width modulation circuit 106 is electrically connected to the gate driving chip; the pulse width modulation circuit 106 includes an oscillator, an error amplifier, and a pulse width comparator.
It should be noted that, in order to improve the display unevenness, the display device needs to be debugged before the factory shipment, a sample database of the speckle reduction compensation value is stored in the data memory 103, and the timing controller 104 continuously reads or writes the speckle reduction compensation value until finding an optimal speckle reduction compensation value, and stores the optimal speckle reduction compensation value into the data memory 103 as a final speckle reduction compensation value after the factory shipment, so as to optimize the quality parameter of the display device, wherein, in the debugging stage before the factory shipment, the pulse width modulation circuit 106 will always output a gate driving signal, which belongs to a high voltage signal, if the timing controller 104 uses a higher frequency to communicate with the data memory 103, the gate driving signal will interfere with the communication between the timing controller 104 and the data memory 103, and the timing controller 104 will not be able to read the data stored in the data memory 103, in this embodiment, the interference of the gate driving signal to the timing controller can be reduced by reading and writing the speckle reduction compensation value with the data memory 103 at a lower first operating frequency, so as to ensure the quality of communication, that is, the quality of the display device; after the display device leaves the factory, in the process of starting up the display device by a user, because the pulse width modulation circuit 106 does not start to work at this time, in order to reduce the starting-up time, in the embodiment of the present invention, a higher second working frequency is adopted to perform reading and writing of the speckle reduction compensation value with the data memory 103, that is, the reading efficiency is improved, so that the starting-up time of the product meets the requirement.
As shown in fig. 2, a flowchart of a driving method of a display device according to a first embodiment of the present invention includes the following steps:
s201, providing a display device, which comprises a display panel, a driving chip, a data memory and a time schedule controller, wherein the driving chip is used for driving the display panel, the data memory stores a speckle removing compensation value, and the time schedule controller is used for reading and writing the speckle removing compensation value and sending the speckle removing compensation value to the driving chip;
s202, the time schedule controller judges the working state of the display device, if the working state is a debugging state, the time schedule controller executes reset operation, and reads and writes the speckle reduction compensation value by using a first working frequency and the data memory;
and S203, if the working state is the starting state, the time schedule controller uses a second working frequency and the data memory to read and write the speckle reduction compensation value, and the first working frequency is less than the second working frequency.
In one embodiment, the display device further comprises an interface connector, the interface connector is used for transmitting a compensation instruction sent by a central processing unit to the time schedule controller, and the time schedule controller is used for determining the working state according to the compensation instruction; the compensation instruction comprises a starting instruction and a reset instruction, and the time schedule controller is used for determining that the working state is a starting state when the compensation instruction is the starting instruction; and when the compensation instruction is a reset instruction, determining that the working state is a debugging state.
In one embodiment, the display device further includes a pulse width modulation circuit, the pulse width modulation circuit is configured to output a driving electrical signal, the driving electrical signal is a gate driving signal, and the pulse width modulation circuit is electrically connected to the driving chip, that is, the pulse width modulation circuit is electrically connected to the gate driving chip; the pulse width modulation circuit includes an oscillator, an error amplifier, and a pulse width comparator.
In an embodiment, the timing controller may further determine an operating state of the display device by determining an operating state of the pulse width modulation circuit, and if the pulse width modulation circuit is in the operating state, that is, if the display device is in a debug state, the timing controller performs a reset operation, and performs reading and writing of the speckle reduction compensation value using a first operating frequency and the data memory; and if the pulse width modulation circuit is in a non-working state, namely the display device is in a starting state, the time schedule controller uses a second working frequency and the data memory to read and write the speckle reduction compensation value, and the first working frequency is less than the second working frequency.
As shown in fig. 3, a block diagram of a display device according to a second embodiment of the present invention is provided, in which components of the present invention and relative position relationships between the components can be visually seen, and the display device includes a conversion module 301 and a control module 302; the conversion module 301 includes a chip on film 303 and a data storage 304, the chip on film 303 includes a driving chip and a flexible circuit board integrated on the driving chip, the flexible circuit board is connected to a display panel (not shown in the figure) of the display device, and the data storage 304 stores a speckle reduction compensation value.
The control module 302 includes a timing controller 305, an interface connector 306, and a pulse width modulation circuit 307, where the timing controller 305 is configured to read and write the speckle reduction compensation value, and send the speckle reduction compensation value to a driving chip on the chip on film 303; the timing controller 305 is configured to perform reading and writing of the speckle reduction compensation value with the data storage 304 by using a first operating frequency when the operating state of the display apparatus is a debug state; when the working state of the display device is a power-on state, reading and writing the speckle reduction compensation value by using a second working frequency and the data memory 304, wherein the first working frequency is less than the second working frequency; the interface connector 306 is configured to transmit a compensation command sent by the central processing unit to the timing controller 305, and the timing controller 305 is configured to determine the operating state according to the compensation command; the compensation instruction includes a power-on instruction and a reset instruction, and the timing controller 305 is configured to determine that the working state is a power-on state when the compensation instruction is the power-on instruction; when the compensation instruction is a reset instruction, determining that the working state is a debugging state; the pulse width modulation circuit 307 is configured to output a driving electrical signal, where the driving electrical signal is a gate driving signal, and the pulse width modulation circuit 307 is electrically connected to a driving chip on the chip on film 303, that is, the pulse width modulation circuit 307 is electrically connected to the gate driving chip; the pulse width modulation circuit 307 includes an oscillator, an error amplifier, and a pulse width comparator.
The control module 302 is connected with the conversion module 301 through a connector 308.
As shown in fig. 4, in the driving flow diagram of the display device according to the second embodiment of the present invention, two working modes are provided in the timing controller 401, one is the power-on mode 402, and the other is the reset mode 403, the front end of the timing controller 401 is connected to the interface connector 404, the front end of the interface connector 404 is connected to the central processing unit of the display device, the compensation instruction issued by the central processing unit is transmitted to the timing controller 401, and the timing controller 401 determines the working state through the compensation instruction transmitted by the interface connector 404 of the front end; the rear end of the timing controller 401 is connected to the data memory 405, and the operating frequency, i.e., the communication frequency with the data memory 405, is adjusted by the operating state.
The compensation instruction includes a power-on instruction and a reset instruction, and the timing controller 401 is configured to determine that the working state is a power-on state (i.e., a power-on mode 402) when the compensation instruction is the power-on instruction; when the compensation command is a reset command, determining that the working state is a debug state (i.e., a reset mode 403), where the timing controller 401 is configured to use a first working frequency and the data memory 405 to read and write the speckle reduction compensation value when the working state of the display device is the debug state; and when the working state of the display device is a startup state, reading and writing the speckle reduction compensation value by using a second working frequency and the data memory 405, wherein the first working frequency is less than the second working frequency.
It should be noted that the boot mode 402 refers to a boot process of a user after the display device leaves a factory, and at this time, a higher second operating frequency is used to communicate with the data storage 405, so that the reading efficiency can be increased, the boot time can be shortened, and the boot time of a product can meet requirements; the reset mode 403 is a debugging process of the display device before leaving the factory, and an optimal de-speckling compensation value needs to be found from a sample database, and at this time, a lower first working frequency is used to communicate with the data storage 405, so that interference of a GOA signal is reduced, and communication quality, that is, quality of a product is guaranteed.
In summary, in the display device provided in the embodiments of the present invention, the working state of the display device is detected in real time by the timing controller, if the display device is in the power-on state, the timing controller uses a higher frequency to communicate with the data memory, so as to ensure that the power-on time of the product meets the requirement, if the display device is in the debugging state before factory leaving, the timing controller performs the reset operation, and uses a lower frequency to communicate with the data memory, so as to reduce the interference of the GOA signal to the timing controller, and ensure that the timing controller can normally communicate.
The display device and the driving method thereof according to the embodiments of the present invention are described in detail above. It should be understood that the exemplary embodiments described herein should be considered merely illustrative for facilitating understanding of the method of the present invention and its core ideas, and not restrictive.
Claims (10)
1. A display device, comprising:
a display panel;
the driving chip is used for driving the display panel;
a data storage storing a speckle removal compensation value;
the time schedule controller is used for reading and writing the speckle removing compensation value and sending the speckle removing compensation value to the driving chip;
the time sequence controller is used for reading and writing the speckle reduction compensation value by using a first working frequency and the data memory when the working state of the display device is a debugging state; and when the working state of the display device is a starting state, reading and writing the speckle reduction compensation value by using a second working frequency and the data memory, wherein the first working frequency is less than the second working frequency.
2. The display device according to claim 1, further comprising an interface connector for transmitting a compensation command transmitted from a central processing unit to the timing controller, the timing controller for determining the operation state according to the compensation command.
3. The display device according to claim 2, wherein the compensation command comprises a power-on command and a reset command, and the timing controller is configured to determine that the operating state is a power-on state when the compensation command is the power-on command; and when the compensation instruction is a reset instruction, determining that the working state is a debugging state.
4. The display device of claim 1, wherein the second operating frequency is twice the first operating frequency.
5. The display device of claim 1, wherein the timing controller is coupled to the data memory through a serial peripheral interface bus.
6. The display device of claim 5, wherein the data memory is a flash memory.
7. The display device according to claim 1, further comprising a pulse width modulation circuit for outputting a driving electric signal, the pulse width modulation circuit being electrically connected to the driving chip.
8. The display device of claim 7, wherein the pulse width modulation circuit comprises an oscillator, an error amplifier, and a pulse width comparator.
9. The display device according to claim 1, wherein the driving chips include source driving chips for supplying data signals to the display panel and gate driving chips for supplying scan signals to the display panel.
10. A method of driving a display device, comprising the steps of:
providing a display device, which comprises a display panel, a driving chip, a data memory and a time schedule controller, wherein the driving chip is used for driving the display panel, the data memory stores a speckle removing compensation value, and the time schedule controller is used for reading and writing the speckle removing compensation value and sending the speckle removing compensation value to the driving chip;
the time schedule controller judges the working state of the display device, if the working state is a debugging state, the time schedule controller executes reset operation, and reads and writes the speckle removing compensation value by using a first working frequency and the data memory;
and if the working state is the starting state, the time schedule controller uses a second working frequency and the data memory to read and write the speckle reduction compensation value, and the first working frequency is less than the second working frequency.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103680451A (en) * | 2013-12-18 | 2014-03-26 | 深圳市华星光电技术有限公司 | GOA circuit and display device applied to liquid crystal display |
| CN105280149A (en) * | 2015-11-11 | 2016-01-27 | 深圳市华星光电技术有限公司 | Mura compensation data writing apparatus and method |
| CN107016953A (en) * | 2017-05-22 | 2017-08-04 | 武汉天马微电子有限公司 | Display panel driving method, display panel and display device |
| CN109903713A (en) * | 2019-03-06 | 2019-06-18 | 深圳市华星光电技术有限公司 | Show compensation circuit and display compensation method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9741301B2 (en) * | 2014-04-17 | 2017-08-22 | Shenzhen China Star Optoelectronics Technology Co., Ltd | Driving circuit of display panel, display device, and method for driving the driving circuit of the display panel |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103680451A (en) * | 2013-12-18 | 2014-03-26 | 深圳市华星光电技术有限公司 | GOA circuit and display device applied to liquid crystal display |
| CN105280149A (en) * | 2015-11-11 | 2016-01-27 | 深圳市华星光电技术有限公司 | Mura compensation data writing apparatus and method |
| CN107016953A (en) * | 2017-05-22 | 2017-08-04 | 武汉天马微电子有限公司 | Display panel driving method, display panel and display device |
| CN109903713A (en) * | 2019-03-06 | 2019-06-18 | 深圳市华星光电技术有限公司 | Show compensation circuit and display compensation method |
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