CN110912637B - Clock synchronization system and method - Google Patents
Clock synchronization system and method Download PDFInfo
- Publication number
- CN110912637B CN110912637B CN201911418420.0A CN201911418420A CN110912637B CN 110912637 B CN110912637 B CN 110912637B CN 201911418420 A CN201911418420 A CN 201911418420A CN 110912637 B CN110912637 B CN 110912637B
- Authority
- CN
- China
- Prior art keywords
- clock signal
- frequency
- reference clock
- local clock
- local
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The embodiment of the invention discloses a clock synchronization system and a clock synchronization method. The counter counts the pulse number of the local clock signal generated by the voltage-controlled oscillator in the time interval of two adjacent rising edges or two adjacent falling edges in the reference clock signal; the microprocessor calculates the frequency of the reference clock signal according to the count value and determines a frequency division coefficient according to the frequency of the reference clock signal; the first frequency divider divides the frequency of the reference clock signal based on a frequency division coefficient; the phase discriminator performs phase discrimination on the reference clock signal and the local clock signal after frequency division; and the microprocessor adjusts the voltage signal according to the phase discrimination value to control a local clock signal generated by the voltage-controlled oscillator until the frequency of the local clock signal is the same as that of the reference clock signal and the phase of the local clock signal is synchronous with that of the reference clock signal, and outputs the local clock signal. Through the scheme, the frequency of the reference clock signal input by the reference source can be automatically identified, and the reference clock signal is tracked.
Description
Technical Field
The embodiment of the invention relates to the technical field of communication, in particular to a clock synchronization system and a clock synchronization method.
Background
Generally, a clock synchronization system is a closed-loop system, and the frequency of a local clock signal gradually approaches the frequency of a reference clock signal of a reference source by continuously comparing the reference clock signal and the local clock signal of the input reference source and continuously adjusting the local clock signal according to the difference between the reference clock signal and the local clock signal. Generally speaking, the input reference source is a precision clock signal with a fixed frequency, such as the more common signals of 1Hz, 10MHz, etc.
In a clock synchronization system in the prior art, only a few clock signals with specific frequencies can be tracked, that is, a reference clock signal input by a reference source is generally a signal with a specific frequency, and the frequency of the reference clock signal of the reference source needs to be obtained by distinguishing through different hardware ports or manually configuring, which is troublesome and has limited application scenarios.
Disclosure of Invention
The embodiment of the invention provides a clock synchronization system and a clock synchronization method, which can automatically identify the frequency of a reference clock signal input by a reference source, track the reference clock signal and widen the application scene of the clock synchronization system.
In a first aspect, an embodiment of the present invention provides a clock synchronization method, where the system includes: a microprocessor, a counter, a voltage controlled oscillator, a first frequency divider and a phase discriminator, wherein,
the voltage-controlled oscillator controls oscillation to generate a local clock signal according to the voltage signal generated by the microprocessor; the counter receives a reference clock signal input by a reference source, and counts the pulse number of the local clock signal within the time interval of two adjacent rising edges or two adjacent falling edges in the reference clock signal to obtain a count value;
the microprocessor calculates the frequency of the reference clock signal according to the counting value and the period of the local clock signal, and determines a frequency division coefficient according to the frequency of the reference clock signal;
the first frequency divider divides the reference clock signal based on the division coefficient;
the phase discriminator performs phase discrimination on the reference clock signal and the local clock signal after frequency division to obtain a phase discrimination value;
and the microprocessor adjusts the voltage signal according to the phase discrimination value to control a local clock signal generated by the voltage-controlled oscillator until the frequency of the local clock signal is the same as that of a reference clock signal, and outputs the local clock signal when the phase of the local clock signal is synchronous with that of the reference clock signal.
In a second aspect, an embodiment of the present invention further provides a clock synchronization method, where the method includes:
the voltage controlled oscillator controls oscillation according to the voltage signal generated by the microprocessor to generate a local clock signal;
the counter receives a reference clock signal input by a reference source, and counts the pulse number of the local clock signal in the time interval of two adjacent rising edges or two adjacent falling edges in the reference clock signal to obtain a count value;
the microprocessor calculates the frequency of the reference clock signal according to the count value and the period of the local clock signal, and determines a frequency division coefficient according to the frequency of the reference clock signal;
a first frequency divider divides the reference clock signal based on the division coefficient;
the phase discriminator performs phase discrimination on the reference clock signal and the local clock signal after frequency division to obtain a phase discrimination value;
and the microprocessor adjusts the voltage signal according to the phase discrimination value to control a local clock signal generated by the voltage-controlled oscillator until the frequency of the local clock signal is the same as that of a reference clock signal, and outputs the local clock signal when the phase of the local clock signal is synchronous with that of the reference clock signal.
According to the clock synchronization scheme provided by the embodiment of the invention, a voltage-controlled oscillator controls oscillation to generate a local clock signal according to a voltage signal generated by a microprocessor; the counter receives a reference clock signal input by a reference source, and counts the pulse number of a local clock signal in the time interval of two adjacent rising edges or two adjacent falling edges in the reference clock signal to obtain a count value; the microprocessor calculates the frequency of the reference clock signal according to the count value and the period of the local clock signal, and determines a frequency division coefficient according to the frequency of the reference clock signal; the first frequency divider divides the frequency of the reference clock signal based on a frequency division coefficient; the phase discriminator performs phase discrimination on the reference clock signal and the local clock signal after frequency division to obtain a phase discrimination value; and the microprocessor adjusts the voltage signal according to the phase discrimination value to control a local clock signal generated by the voltage-controlled oscillator until the frequency of the local clock signal is the same as that of the reference clock signal and the phase of the local clock signal is synchronous with that of the reference clock signal, and outputs the local clock signal. By adopting the technical means, the frequency of the reference clock signal input by the reference source can be automatically identified, and the frequency division coefficient of the first frequency divider is automatically adjusted based on the frequency of the reference clock signal, so that the reference clock signal is tracked, the reference clock signal with any frequency can be adapted, and the application scene of a clock synchronization system can be widened.
Drawings
Fig. 1 is a schematic structural diagram of a clock synchronization system according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another clock synchronization system according to an embodiment of the present invention;
fig. 3 is a schematic flowchart of a clock synchronization method according to an embodiment of the present invention;
fig. 4 is a flowchart illustrating another clock synchronization method according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Fig. 1 is a schematic structural diagram of a clock synchronization system according to an embodiment of the present invention. As shown in fig. 1, a clock synchronization system 100 provided by the embodiment of the present invention includes: a microprocessor 101, a counter 102, a voltage controlled oscillator 103, a first frequency divider 104 and a phase detector 105, wherein,
the voltage-controlled oscillator 103 controls oscillation according to the voltage signal generated by the microprocessor 101 to generate a local clock signal;
the counter 102 receives a reference clock signal input by a reference source, and counts the number of pulses of a local clock signal within a time interval between two adjacent rising edges or two adjacent falling edges in the reference clock signal to obtain a count value;
the microprocessor 101 calculates the frequency of the reference clock signal according to the count value and the period of the local clock signal, and determines a frequency division coefficient according to the frequency of the reference clock signal;
the first frequency divider 104 divides the frequency of the reference clock signal based on the division coefficient;
the phase discriminator 105 discriminates phases of the frequency-divided reference clock signal and the local clock signal to obtain a phase discrimination value;
the microprocessor 101 adjusts the voltage signal according to the phase detection value to control the local clock signal generated by the voltage controlled oscillator 103 until the frequency of the local clock signal is the same as the frequency of the reference clock signal and the phase of the local clock signal is synchronous with the phase of the reference clock signal, and outputs the local clock signal.
In the embodiment of the present invention, the microprocessor 101 generates a voltage signal and inputs the voltage signal to the voltage controlled oscillator 103, wherein the voltage signal is an analog voltage signal converted by the digital-to-analog converter. The voltage controlled oscillator 103 controls oscillation according to the input voltage signal to generate a local clock signal, and inputs the local clock signal to the counter 102. The reference clock signal input by the reference source is transmitted to the counter 102, and the counter 102 counts the number of pulses of the local clock signal in the time interval between two adjacent rising edges or two adjacent falling edges in the reference clock signal to obtain a count value. That is, the counter 102 counts the number of pulses of the local clock signal with the period t of the local clock signal as a counting period, and obtains a count value n. The counter 102 feeds back the count value n to the microprocessor 101, and the microprocessor 101 calculates the frequency of the reference clock signal according to the count value n and the period t of the local clock signal. Wherein the reference clock signal comprises a reference frequency signal and a reference time signal. Specifically, the period of the reference clock signal is T ═ n × T, and the frequency of the reference clock signal is f ═ 1/T, that is, f ═ 1/(n × T). Then, the microprocessor 101 determines a frequency division coefficient according to the frequency of the reference clock signal, and causes the first frequency divider 104 to divide the reference clock signal based on the frequency division coefficient. Optionally, determining a frequency division coefficient according to the frequency of the reference clock signal includes: determining a frequency division coefficient according to the frequency of the reference clock signal and the frequency of the local clock signal; the frequency division coefficient is the ratio of the frequency of the reference clock signal to the frequency of the local clock signal. It is understood that, after the first frequency divider 104 divides the reference clock signal by the division coefficient, the frequency of the divided reference clock signal is the same as the frequency of the local clock signal. The phase detector 105 performs phase detection on the frequency-divided reference clock signal and the local clock signal to obtain a phase detection value, that is, a phase difference between the frequency-divided reference clock signal and the local clock signal is compared, and the phase detection value is fed back to the microprocessor 101. The microprocessor 101 adjusts the voltage signal input to the vco 103 according to the phase detection value, thereby further adjusting the local clock signal generated by the vco 103. And continuously repeating the steps until the frequency of the local clock signal is the same as that of the reference clock signal and the phase of the local clock signal is synchronous with that of the reference clock signal, and outputting the local clock signal to realize the tracking and synchronization of the reference clock signal.
Optionally, the microprocessor 101 performs low-pass filtering on the phase detection value fed back by the phase detector 105 to obtain a voltage signal, and inputs the voltage signal to the voltage-controlled oscillator 103, the voltage-controlled oscillator 103 controls oscillation to generate a clock signal according to the input voltage signal, and after the microprocessor 101 performs low-pass filtering on the phase detection value, jitter and drift caused by transmission of a reference clock signal input by a reference source can be eliminated. The voltage signal output from the microprocessor 101 reflects the magnitude of the phase difference between the local clock signal and the reference clock signal, and the voltage signal generated based on the magnitude of the phase difference controls the voltage-controlled oscillator 103 to oscillate the generated clock signal, so that the phase of the local clock signal can be finally synchronized with the phase of the reference clock signal.
Optionally, the voltage-Controlled Oscillator 103 includes an oven Controlled Crystal Oscillator (ocxo) and a Temperature compensated Crystal Oscillator (TCXO).
In the clock synchronization system provided by the embodiment of the invention, the voltage-controlled oscillator controls oscillation to generate a local clock signal according to the voltage signal generated by the microprocessor; the counter receives a reference clock signal input by a reference source, and counts the pulse number of a local clock signal in the time interval of two adjacent rising edges or two adjacent falling edges in the reference clock signal to obtain a count value; the microprocessor calculates the frequency of the reference clock signal according to the count value and the period of the local clock signal, and determines a frequency division coefficient according to the frequency of the reference clock signal; the first frequency divider divides the frequency of the reference clock signal based on a frequency division coefficient; the phase discriminator performs phase discrimination on the reference clock signal and the local clock signal after frequency division to obtain a phase discrimination value; and the microprocessor adjusts the voltage signal according to the phase discrimination value to control a local clock signal generated by the voltage-controlled oscillator until the frequency of the local clock signal is the same as that of the reference clock signal and the phase of the local clock signal is synchronous with that of the reference clock signal, and outputs the local clock signal. By adopting the technical means, the frequency of the reference clock signal input by the reference source can be automatically identified, and the frequency division coefficient of the first frequency divider is automatically adjusted based on the frequency of the reference clock signal, so that the reference clock signal is tracked, the reference clock signal with any frequency can be adapted, and the application scene of a clock synchronization system can be widened.
Fig. 2 is a schematic structural diagram of another clock synchronization system according to an embodiment of the present invention. As shown in fig. 2, the clock synchronization system 100 further includes a frequency multiplier 106, and the frequency multiplier 106 is connected between the voltage-controlled oscillator 103 and the counter 102; counting the number of pulses of the local clock signal in a time interval between two adjacent rising edges or two adjacent falling edges in the reference clock signal to obtain a count value, comprising: counting the pulse number of the local clock signal which is frequency-multiplied by the frequency multiplier 106 in the time interval of two adjacent rising edges or two adjacent falling edges in the reference clock signal to obtain a count value; accordingly, the microprocessor 101 calculates the frequency of the reference clock signal according to the count value and the period of the local clock signal, and includes: the microprocessor 101 calculates the frequency of the reference clock signal according to the count value and the period of the multiplied local clock signal.
For example, the frequency multiplier 106 multiplies the local clock signal to obtain a multiplied clock signal, for example, N multiplies the local clock signal, where N is an integer greater than or equal to 1. And counting the frequency-multiplied clock signals in the time interval of two adjacent rising edges or two adjacent falling edges in the reference clock signal, namely counting by taking the period of the frequency-multiplied clock signals as a counting period to obtain a counting value. The microprocessor 101 calculates the frequency of the reference clock signal based on the count value and the period of the multiplied clock signal. Since the frequency of the frequency-multiplied clock signal is increased, the period of the frequency-multiplied clock signal is decreased, the counting frequency is increased, and the accuracy of the obtained count value can be improved, thereby further improving the accuracy of calculating the frequency of the reference clock signal.
In some embodiments, as shown in fig. 2, the clock synchronization system 100 further comprises: the second frequency divider 107, the second frequency divider 107 is connected between the voltage controlled oscillator 103 and the phase detector 105; the phase discriminator 105 discriminates phases of the reference clock signal and the local clock signal after frequency division to obtain a phase discrimination value, which includes: the phase discriminator 105 discriminates the phase of the frequency-divided reference clock signal and the frequency-divided local clock signal by the second frequency divider 107 to obtain a phase discrimination value; wherein the frequency of the divided reference clock signal is the same as the frequency of the divided local clock signal.
Illustratively, in order to have the same frequency of the two clock signals input to the phase detector 105 for phase detection, the first frequency divider 104 is required to divide the frequency of the reference clock signal, and the second frequency divider 107 is required to divide the frequency of the local clock signal. The frequency division coefficient of the first frequency divider 104 when dividing the frequency of the reference clock signal is determined by the frequency of the reference clock signal and the frequency of the clock signal to be input to the phase detector 105, that is, the frequency division coefficient of the first frequency divider 104 is the ratio of the frequency of the reference clock signal to the frequency of the clock signal to be input to the phase detector 105; the frequency division coefficient of the second frequency divider 107 when dividing the local clock signal is determined by the frequency of the local clock signal and the frequency of the clock signal to be input to the phase detector 105, that is, the frequency division coefficient of the second frequency divider 107 is the ratio of the frequency of the local clock signal to the frequency of the clock signal to be input to the phase detector 105. For example, the frequency of the clock signal to be input to the phase detector 105 may be set to 1Hz, and then the frequency division coefficient of the first frequency divider 104 is the frequency value of the reference clock signal, and the frequency division coefficient of the second frequency divider 107 is the frequency value of the local clock signal.
The present embodiment provides a clock synchronization method based on the clock synchronization system provided in the foregoing embodiment, and fig. 3 is a schematic flow chart of the clock synchronization method provided in the embodiment of the present invention, as shown in fig. 3, the method includes the following steps:
Optionally, the voltage controlled oscillator includes an oven controlled crystal oscillator OCXO and a temperature compensated crystal oscillator TCXO.
Optionally, determining a frequency division coefficient according to the frequency of the reference clock signal includes: determining a frequency division coefficient according to the frequency of the reference clock signal and the frequency of the local clock signal; the frequency division coefficient is the ratio of the frequency of the reference clock signal to the frequency of the local clock signal.
And 304, the first frequency divider divides the frequency of the reference clock signal based on the frequency division coefficient.
And 305, phase discrimination is carried out on the reference clock signal and the local clock signal after frequency division by the phase discriminator to obtain a phase discrimination value.
According to the clock synchronization method provided by the embodiment of the invention, a voltage-controlled oscillator controls oscillation to generate a local clock signal according to a voltage signal generated by a microprocessor; the counter receives a reference clock signal input by a reference source, and counts the pulse number of a local clock signal in the time interval of two adjacent rising edges or two adjacent falling edges in the reference clock signal to obtain a count value; the microprocessor calculates the frequency of the reference clock signal according to the count value and the period of the local clock signal, and determines a frequency division coefficient according to the frequency of the reference clock signal; the first frequency divider divides the frequency of the reference clock signal based on a frequency division coefficient; the phase discriminator performs phase discrimination on the reference clock signal and the local clock signal after frequency division to obtain a phase discrimination value; and the microprocessor adjusts the voltage signal according to the phase discrimination value to control a local clock signal generated by the voltage-controlled oscillator until the frequency of the local clock signal is the same as that of the reference clock signal and the phase of the local clock signal is synchronous with that of the reference clock signal, and outputs the local clock signal. By adopting the technical means, the frequency of the reference clock signal input by the reference source can be automatically identified, and the frequency division coefficient of the first frequency divider is automatically adjusted based on the frequency of the reference clock signal, so that the reference clock signal is tracked, the reference clock signal with any frequency can be adapted, and the application scene of a clock synchronization system can be widened.
The present embodiment provides a clock synchronization method based on the clock synchronization system provided in the foregoing embodiment, and fig. 4 is a schematic flow chart of another clock synchronization method provided in the embodiment of the present invention, as shown in fig. 4, the method includes the following steps:
Optionally, the voltage controlled oscillator includes an oven controlled crystal oscillator OCXO and a temperature compensated crystal oscillator TCXO.
And 403, the counter receives a reference clock signal input by the reference source, and counts the pulse number of the local clock signal multiplied by the frequency multiplier within the time interval of two adjacent rising edges or two adjacent falling edges in the reference clock signal to obtain a count value.
And step 406, the second frequency divider divides the frequency of the local clock signal to obtain a divided local clock signal, wherein the frequency of the divided local clock signal is the same as the frequency of the divided reference clock signal.
For example, the frequency of the reference clock signal divided by the first frequency divider and the frequency of the local clock signal divided by the second frequency divider may be both 1 Hz.
The clock synchronization method provided by the embodiment of the invention counts the pulse number of the local clock signal multiplied by the frequency multiplier in the time interval of two adjacent rising edges or two adjacent falling edges in the reference clock signal, enables the microprocessor to calculate the frequency of the reference clock signal according to the obtained count value, further determines the frequency division coefficient of the first frequency divider, and enables the phase discriminator to discriminate the reference clock signal divided by the frequency division coefficient and the local clock signal divided by the second frequency divider, wherein the frequency of the divided reference clock signal is the same as the frequency of the divided local clock signal, thereby enabling the microprocessor to adjust the voltage signal according to the obtained phase discrimination value to control the local clock signal generated by the voltage-controlled oscillator until the frequency of the local clock signal is the same as the frequency of the reference clock signal and the phase of the local clock signal is synchronous with the phase of the reference clock signal, the local clock signal is output, the frequency of the reference clock signal input by the reference source can be automatically identified, and the frequency division coefficient of the first frequency divider is automatically adjusted based on the frequency of the reference clock signal, so that the reference clock signal is tracked, the reference clock signal with any frequency can be adapted, and the application scene of a clock synchronization system can be widened.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A clock synchronization system, comprising: a microprocessor, a counter, a voltage controlled oscillator, a first frequency divider and a phase discriminator, wherein,
the voltage-controlled oscillator controls oscillation to generate a local clock signal according to the voltage signal generated by the microprocessor;
the counter receives a reference clock signal input by a reference source, and counts the pulse number of the local clock signal within the time interval of two adjacent rising edges or two adjacent falling edges in the reference clock signal to obtain a count value;
the microprocessor calculates the frequency of the reference clock signal according to the counting value and the period of the local clock signal, and determines a frequency division coefficient according to the frequency of the reference clock signal;
the first frequency divider divides the reference clock signal based on the division coefficient;
the phase discriminator performs phase discrimination on the reference clock signal and the local clock signal after frequency division to obtain a phase discrimination value;
and the microprocessor adjusts the voltage signal according to the phase discrimination value to control a local clock signal generated by the voltage-controlled oscillator until the frequency of the local clock signal is the same as that of a reference clock signal, and outputs the local clock signal when the phase of the local clock signal is synchronous with that of the reference clock signal.
2. The system of claim 1, further comprising: the frequency multiplier is connected between the voltage-controlled oscillator and the counter;
counting the number of pulses of the local clock signal in a time interval between two adjacent rising edges or two adjacent falling edges in the reference clock signal to obtain a count value, including:
counting the number of pulses of the local clock signal multiplied by the frequency multiplier within the time interval between two adjacent rising edges or two adjacent falling edges in the reference clock signal to obtain a count value;
correspondingly, the microprocessor calculates the frequency of the reference clock signal according to the count value and the period of the local clock signal, including:
and the microprocessor calculates the frequency of the reference clock signal according to the count value and the period of the frequency-multiplied local clock signal.
3. The system of claim 1, wherein determining a division factor based on the frequency of the reference clock signal comprises:
determining a frequency division coefficient according to the frequency of the reference clock signal and the frequency of the local clock signal; the frequency division coefficient is the ratio of the frequency of the reference clock signal to the frequency of the local clock signal.
4. The system of claim 1, further comprising: a second frequency divider connected between the voltage controlled oscillator and the phase detector;
the phase discriminator carries out phase discrimination on the reference clock signal and the local clock signal after frequency division to obtain a phase discrimination value, and the phase discrimination method comprises the following steps:
the phase discriminator performs phase discrimination on the reference clock signal after frequency division and the local clock signal after frequency division by the second frequency divider to obtain a phase discrimination value; wherein the frequency of the divided reference clock signal is the same as the frequency of the divided local clock signal.
5. The system of any of claims 1-4, wherein the voltage controlled oscillator comprises an oven controlled crystal oscillator (OCXO) and a temperature compensated crystal oscillator (TCXO).
6. A method of clock synchronization, comprising:
the voltage controlled oscillator controls oscillation according to the voltage signal generated by the microprocessor to generate a local clock signal;
the counter receives a reference clock signal input by a reference source, and counts the pulse number of the local clock signal in the time interval of two adjacent rising edges or two adjacent falling edges in the reference clock signal to obtain a count value;
the microprocessor calculates the frequency of the reference clock signal according to the count value and the period of the local clock signal, and determines a frequency division coefficient according to the frequency of the reference clock signal;
a first frequency divider divides the reference clock signal based on the division coefficient;
the phase discriminator performs phase discrimination on the reference clock signal and the local clock signal after frequency division to obtain a phase discrimination value;
and the microprocessor adjusts the voltage signal according to the phase discrimination value to control a local clock signal generated by the voltage-controlled oscillator until the frequency of the local clock signal is the same as that of a reference clock signal, and outputs the local clock signal when the phase of the local clock signal is synchronous with that of the reference clock signal.
7. The method of claim 6,
counting the number of pulses of the local clock signal in a time interval between two adjacent rising edges or two adjacent falling edges in the reference clock signal to obtain a count value, including:
counting the pulse number of the local clock signal which is frequency-multiplied by the frequency multiplier in the time interval of two adjacent rising edges or two adjacent falling edges in the reference clock signal to obtain a count value;
correspondingly, the microprocessor calculates the frequency of the reference clock signal according to the count value and the period of the local clock signal, and includes:
and the microprocessor calculates the frequency of the reference clock signal according to the count value and the period of the frequency-multiplied local clock signal.
8. The method of claim 6, wherein determining a division factor based on the frequency of the reference clock signal comprises:
determining a frequency division coefficient according to the frequency of the reference clock signal and the frequency of the local clock signal; the frequency division coefficient is the ratio of the frequency of the reference clock signal to the frequency of the local clock signal.
9. The method of claim 6, wherein the phase detector phase-detects the divided reference clock signal and the local clock signal to obtain a phase-detected value, comprising:
the phase discriminator performs phase discrimination on the reference clock signal after frequency division and the local clock signal after frequency division by the second frequency divider to obtain a phase discrimination value; wherein the frequency of the divided reference clock signal is the same as the frequency of the divided local clock signal.
10. Method according to any of claims 6-9, wherein the voltage controlled oscillator comprises an oven controlled crystal oscillator, OCXO, and a temperature compensated crystal oscillator, TCXO.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911418420.0A CN110912637B (en) | 2019-12-31 | 2019-12-31 | Clock synchronization system and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911418420.0A CN110912637B (en) | 2019-12-31 | 2019-12-31 | Clock synchronization system and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110912637A CN110912637A (en) | 2020-03-24 |
| CN110912637B true CN110912637B (en) | 2021-06-29 |
Family
ID=69814239
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911418420.0A Active CN110912637B (en) | 2019-12-31 | 2019-12-31 | Clock synchronization system and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110912637B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112565554B (en) * | 2020-12-09 | 2022-03-18 | 威创集团股份有限公司 | Clock synchronization system based on FPGA |
| US11817864B2 (en) * | 2021-06-28 | 2023-11-14 | Stmicroelectronics S.R.L. | Timing system including a master device and at least a slave device synchronized with each other and related synchronization method |
| CN114124342B (en) * | 2021-11-25 | 2024-07-30 | 广东大普通信技术股份有限公司 | Clock frequency maintaining system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201328110Y (en) * | 2008-11-10 | 2009-10-14 | 石强 | Phase-locking frequency tracking device |
| CN101610123A (en) * | 2009-07-10 | 2009-12-23 | 中兴通讯股份有限公司 | A kind of clock unit and its implementation |
| CN101098220B (en) * | 2006-06-29 | 2010-08-18 | 中兴通讯股份有限公司 | Digital phase-locked loop based clock synchronization method and system thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1878054B (en) * | 2006-02-07 | 2010-05-12 | 华为技术有限公司 | Clock reference device and method for IP network transmission base station |
| US8737551B1 (en) * | 2012-11-06 | 2014-05-27 | Motorola Mobility Llc | Synchronizing receive data over a digital radio frequency (RF) interface |
| CN104954016A (en) * | 2015-04-29 | 2015-09-30 | 南华大学 | Rapidly-adaptive all-digital phase-locked loop and design method thereof |
-
2019
- 2019-12-31 CN CN201911418420.0A patent/CN110912637B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101098220B (en) * | 2006-06-29 | 2010-08-18 | 中兴通讯股份有限公司 | Digital phase-locked loop based clock synchronization method and system thereof |
| CN201328110Y (en) * | 2008-11-10 | 2009-10-14 | 石强 | Phase-locking frequency tracking device |
| CN101610123A (en) * | 2009-07-10 | 2009-12-23 | 中兴通讯股份有限公司 | A kind of clock unit and its implementation |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110912637A (en) | 2020-03-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110912637B (en) | Clock synchronization system and method | |
| US6275553B1 (en) | Digital PLL circuit and clock generation method | |
| JP3066690B2 (en) | Phase-locked oscillation circuit | |
| US5781054A (en) | Digital phase correcting apparatus | |
| US20080272810A1 (en) | Filterless digital frequency locked loop | |
| US9124415B2 (en) | PLL glitchless phase adjustment system | |
| EP2312756A2 (en) | A dual reference oscillator phase-lock loop | |
| US8536911B1 (en) | PLL circuit, method of controlling PLL circuit, and digital circuit | |
| US8947139B1 (en) | Apparatus for doubling the dynamic range of a time to digital converter | |
| US20050062505A1 (en) | Clock generating circuit | |
| US6556086B2 (en) | Fractional-N synthesizer and method of synchronization of the output phase | |
| JPS6256689B2 (en) | ||
| JP2007189455A (en) | Phase comparison circuit, and pll frequency synthesizer using same | |
| US10018970B2 (en) | Time-to-digital system and associated frequency synthesizer | |
| KR100414864B1 (en) | Digital Counter and Digital PLL Circuit | |
| JPH09321617A (en) | Pll frequency synthesizer | |
| CN109712591B (en) | Time sequence control method, time sequence control chip and display device | |
| EP2963826A1 (en) | Frequency synthesiser circuit | |
| JP2006119123A (en) | Phase difference detection device | |
| CN102082658B (en) | Method and device for enhancing frequency stability of target clock | |
| US11088695B2 (en) | Phase-locked loop apparatus and method for clock synchronization | |
| CN104639158B (en) | Synchronous two phase-locked loop adjusting method | |
| EP0454955B1 (en) | Sampling clock generating circuit | |
| US9385860B2 (en) | Fractional PLL circuit | |
| JP3246459B2 (en) | Clock synchronization method and clock synchronization circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: 523000 Room 401 and 402, building 5, No. 24, industrial East Road, Songshanhu Park, Dongguan City, Guangdong Province Patentee after: Guangdong daguangxin Technology Co.,Ltd. Address before: 523808 the first, second and third floors of building 16, small and medium-sized science and technology enterprise Pioneer Park, North Industrial City, Songshanhu high tech Industrial Development Zone, Dongguan City, Guangdong Province Patentee before: Guangdong Dapu Telecom Technology Co.,Ltd. |