CN110890367A - Memory and forming method thereof - Google Patents
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- CN110890367A CN110890367A CN201811045784.4A CN201811045784A CN110890367A CN 110890367 A CN110890367 A CN 110890367A CN 201811045784 A CN201811045784 A CN 201811045784A CN 110890367 A CN110890367 A CN 110890367A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
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Abstract
The invention provides a memory and a forming method thereof. In the memory and the forming method thereof provided by the invention, at least one group of word lines are formed in the substrate, the doped layers are respectively arranged at two sides of each word line, the depth of the doped layers between two adjacent word lines of each group of word lines is greater than that of the doped layers at the deviating sides of the two adjacent word lines, and the depth of the doped layers at the deviating sides of the two adjacent word lines is reduced along with the distance from the two adjacent word lines. Therefore, the leakage current is reduced, and meanwhile, the starting current is improved, so that the performance of the memory is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a memory and a forming method thereof.
Background
Integrated circuits have evolved from integrating tens of devices on a single chip to integrating millions of devices. The performance and complexity of conventional integrated circuits has far exceeded the original imagination. To achieve improvements in complexity and circuit density (the number of devices that can be accommodated on a given chip area), the feature size of devices, also referred to as "geometry", has become smaller with each generation of integrated circuits. Increasing integrated circuit density not only increases the complexity and performance of the integrated circuit, but also reduces consumption for the consumer. Making devices smaller is challenging because there are limits to each process in integrated circuit fabrication, i.e., a process or device placement that needs to be changed if the process is to be performed below the feature size; in addition, conventional processes and materials have process limitations due to the demand for faster and faster device design.
Dram (dynamic Random Access memory), i.e., dynamic Random Access memory, is the most common system memory; the DRAM memory is a semiconductor device, and its performance has been greatly developed, but there is still a demand for further development. In the prior art, a buried-gate DRAM is a common structure, such as a single-deep-junction (single-junction) DRAM, but the leakage current of the DRAM is not ideal, and the turn-on current is also easy to be abnormal, so that the performance of the DRAM is limited.
Disclosure of Invention
The invention aims to provide a memory and a forming method thereof, which can improve the performance of the memory.
To solve the above technical problem, the present invention provides a memory, including:
a substrate having a first surface and a second surface disposed opposite;
at least one group of word lines (50) formed inside the substrate, each group of word lines comprising two adjacent word lines; and a process for the preparation of a coating,
the doped layers extend from the first surface of the substrate to the inside of the substrate and are respectively arranged on two sides of each word line, the depth of the doped layers between two adjacent word lines of each group of word lines is larger than that of the doped layers on the deviating sides of the two adjacent word lines, and the depth of the doped layers on the deviating sides of the two adjacent word lines is reduced along with the distance from the two adjacent word lines.
Optionally, for the memory, the doped layer includes a first portion, a second portion and a third portion, the depth of the first portion is greater than that of the second portion, the depth of the second portion is greater than that of the third portion, the first portion is located between two adjacent word lines, the second portion is located on a side of the two adjacent word lines facing away from each other, and the third portion is located on a side of the second portion away from the word lines.
Optionally, for the memory, the depth of the first portion is 50nm to 70nm, the depth of the second portion is 40nm to 60nm, the depth of the third portion is 30nm to 50nm, and the width of the second portion is 4nm to 8 nm.
Optionally, for the memory, the doping type of the doping layer is N type.
Optionally, for the memory, the doping concentration of the doping layer is between 1E12/cm2～1E16/cm2。
Optionally, for the memory, the doped layer includes a source region and a drain region, the source region and the drain region are respectively arranged at two sides of the word line, and the source region or the drain region between two adjacent word lines is shared.
Optionally, for the memory, an isolation structure layer is further formed on the substrate, and the isolation structure layer surrounds the source region and the drain region.
Optionally, for the memory, the word line includes a first dielectric layer, a semiconductor layer and a second dielectric layer, the first dielectric layer is formed on a groove wall surface of a groove in a substrate, the semiconductor layer is formed on the first dielectric layer in the groove, a top surface of the semiconductor layer is lower than the first surface, the second dielectric layer is located on the top surface of the semiconductor layer, and the second dielectric layer covers the semiconductor layer and is connected to the first dielectric layer.
The invention also provides a forming method of the memory, which comprises the following steps:
providing a substrate, wherein the substrate is provided with a first surface and a second surface which are oppositely arranged;
forming at least one set of first trenches in the substrate, the first trenches having openings formed on the first surface, each set of first trenches including two adjacent first trenches;
forming at least one set of word lines in the at least one set of first trenches;
performing first ion implantation on the substrate on two sides of the word line and close to the first surface;
forming a barrier layer on the substrate and forming an opening, wherein the opening at least exposes a partial area between two adjacent word lines of each group of word lines; and
and performing second ion implantation on the substrate in an inclined manner from the opening, forming doped layers after performing at least the first ion implantation and the second ion implantation, wherein the doped layers are respectively arranged at two sides of each word line, the depth of the doped layers between two adjacent word lines of each group of word lines is greater than that of the doped layers at the deviating sides of the two adjacent word lines, and the depth of the doped layers at the deviating sides of the two adjacent word lines is reduced along with the distance from the two adjacent word lines.
Optionally, for the method for forming the memory, the first ion implantation is an N-type implantation, and the implantation dose is between 1E14/cm2～1E16/cm2The implantation energy is 10 KeV-50 KeV.
Optionally, for the method for forming the memory, the second ion implantation is an N-type implantation, and the implantation dose is between 1E12/cm2～1E13/cm2The implantation energy is 30 KeV-60 KeV, and the implantation angle is 3-20 deg.
Optionally, for the method for forming a memory, after performing the second ion implantation from the opening, the method further includes: performing a heat treatment to form the doped layer.
Optionally, for the method for forming the memory, the heat treatment includes spike annealing at 900-1000 ℃, and the annealing is performed in a nitrogen environment.
Optionally, for the method for forming the memory, the doped layer includes a first portion, a second portion and a third portion, the depth of the first portion is greater than that of the second portion, the depth of the second portion is greater than that of the third portion, the first portion is located between two adjacent word lines, the second portion is located on an opposite side of the two adjacent word lines, and the third portion is located on a side of the second portion away from the word lines.
Optionally, for the method for forming the memory, the depth of the first portion is 50nm to 70nm, the depth of the second portion is 40nm to 60nm, the depth of the third portion is 30nm to 50nm, and the width of the second portion is 4nm to 8 nm.
In the memory and the forming method thereof provided by the invention, at least one group of word lines are formed in the substrate, the doped layers are respectively arranged at two sides of each word line, the depth of the doped layers between two adjacent word lines of each group of word lines is greater than that of the doped layers at the deviating sides of the two adjacent word lines, and the depth of the doped layers at the deviating sides of the two adjacent word lines is reduced along with the distance from the two adjacent word lines. Therefore, the leakage current is reduced, and meanwhile, the starting current is improved, so that the performance of the memory is improved.
Drawings
FIG. 1 is a diagram illustrating a memory structure;
FIG. 2 is a flow chart illustrating a method for forming a memory according to an embodiment of the invention;
FIG. 3 is a schematic diagram illustrating a substrate provided in a method for forming a memory device according to an embodiment of the invention;
FIG. 4 is a schematic diagram illustrating the formation of word lines in a substrate in a method of forming a memory according to an embodiment of the invention;
FIG. 5 is a cross-sectional view taken along line A-A' of FIG. 4;
FIG. 6 is a schematic diagram illustrating a first ion implantation step in a method for forming a memory according to an embodiment of the invention;
FIG. 7 is a schematic view illustrating the formation of a barrier layer and an opening in the method for forming a memory according to an embodiment of the invention;
FIGS. 8-9 illustrate a second ion implantation step in a method of forming a memory device according to an embodiment of the invention;
FIG. 10 is a schematic diagram of a memory formed in accordance with an embodiment of the present invention;
wherein the reference numbers are as follows:
an S-source region;
a D-drain region;
1, 10-substrate;
2, 20-semiconductor layer;
3, 30-dielectric layer;
4, 40-isolation structure layer;
50-word line;
60-a barrier layer;
61-opening;
70-second ion implantation;
81-a first ion-implanted layer;
82-a second ion-implanted layer;
91-a first part;
92-a second portion;
93-a third portion;
101-a first surface;
102-second surface.
Detailed Description
The memory of the present invention and method of forming the same will now be described in greater detail with reference to the schematic drawings in which preferred embodiments of the invention are shown, it being understood that one skilled in the art may modify the invention herein described while still achieving the advantageous results of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
The invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the description that follows, it will be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, pad, and/or pattern, it can be directly on another layer or substrate, and/or intervening layers may also be present. In addition, it will be understood that when a layer is referred to as being "under" another layer, it can be directly under the other layer, and/or one or more intervening layers may also be present. In addition, references to "on" and "under" layers may be made based on the drawings.
Fig. 1 is a schematic structural diagram of a memory, specifically, a single cell junction (single junction) DRAM. As shown in fig. 1, the memory comprises a substrate 1, wherein an isolation structure layer 4 is formed in the substrate 1, and the isolation structure layer 4 is formed by a grooving and filling process, for example. A word line (gate structure), for example, an embedded word line, is formed between the isolation structure layers 4, and includes a semiconductor layer 2 and a dielectric layer 3, where the dielectric layer 3 covers the semiconductor layer 2, and active regions are formed on both sides of the word line, for example, a source region S and a drain region D are respectively arranged on both sides of the word line, and the active regions can be obtained by performing ion implantation according to actual needs.
After the research of the inventor, it is found that the junction depths of such a buried gate structure are substantially uniform, thereby causing large leakage currents, such as a tube junction leakage (cell junction leakage) and a gate induced drain leakage (GIDL leakage), and also having a large influence on the turn-on current, thereby causing performance limitation and reliability degradation.
To this end, the present invention provides a memory to improve the above-mentioned drawbacks. Specifically, refer to fig. 2 which is a schematic flow chart of a method for forming a memory according to a first embodiment of the present invention. The forming method comprises the following steps:
step S11, providing a substrate, wherein the substrate is provided with a first surface and a second surface which are oppositely arranged;
step S12 of forming at least one group of first trenches in the substrate, openings of the first trenches being formed on the first surface, each group of first trenches including two adjacent first trenches;
step S13, forming at least one group of word lines in the at least one group of first trenches;
step S14, performing a first ion implantation on the substrate at two sides of the word line and close to the first surface;
step S15, forming a barrier layer on the substrate and forming an opening, wherein the opening at least exposes a partial area between two adjacent word lines of each group of word lines; and
step S16, performing a second ion implantation on the substrate in an inclined manner from the opening, forming doped layers after performing at least the first ion implantation and the second ion implantation, the doped layers being respectively arranged on both sides of each word line, the depth of the doped layers between two adjacent word lines of each group of word lines being greater than the depth of the doped layers on the sides of the two adjacent word lines facing away from each other, and the depth of the doped layers on the sides of the two adjacent word lines facing away from each other being smaller as the two adjacent word lines are farther away from each other.
Fig. 3 to 9 are schematic structural diagrams of steps of a memory forming method according to an embodiment of the invention.
First, referring to fig. 3, fig. 3 is a schematic diagram illustrating a substrate provided in a method for forming a memory according to an embodiment of the invention.
For step S11, a substrate 10 is provided, the substrate 10 having a first surface 101 and a second surface 102 disposed opposite to each other. Specifically, the substrate 10 may be formed of undoped single crystal silicon, impurity-doped single crystal silicon, Silicon On Insulator (SOI), or the like. By way of example, in one embodiment, the substrate 10 is formed from a single crystal silicon material. A known structure such as a buried layer (not shown) may be formed in the substrate 10, which is not limited by the present invention.
Next, referring to fig. 4 and fig. 5, fig. 4 is a schematic diagram of a word line in a method for forming a memory according to an embodiment of the invention, and fig. 5 is a cross-sectional view taken along a-a' in fig. 4. Specifically, the word line 50 is formed as follows:
for step S12, at least one set of first trenches is formed in the substrate 10, the openings of the first trenches being formed on the first surface 101, each set of first trenches including two adjacent first trenches. In one embodiment, the mask may be formed by photolithography. In one embodiment, before etching to form at least one group of first trenches, a plurality of second trenches may be further formed, the second trenches opening toward the first surface 101, and bottom ends of the second trenches facing away from the first surface 101. The first trench and the second trench may have the same size, and in order to improve the isolation effect, the depth of the second trench is greater than that of the first trench, and the second trench is used to surround the first trench, the source region 111 and the drain region 112. As shown in fig. 4, an isolation material layer is filled in the second trench, and an isolation structure layer 40 is formed. In one embodiment, a plurality of trenches may be formed by etching, the peripheral portion (e.g., a row or a column) serves as the second trench, and the remaining trenches are at least one group of the first trenches. The first trench will be used for the preparation of the subsequent buried word line (or gate structure), and the second trench will be used for the preparation of the subsequent isolation structure layer.
With continued reference to fig. 5, for step S13, at least one set of word lines is formed in the at least one set of first trenches. The first dielectric layer may be formed on the wall surface of the first trench. In one embodiment, the first dielectric layer may be formed by a chemical vapor deposition process, and may be made of, for example, silicon oxide, and may have a depth of 1nm to 200 nm. The first dielectric layer may have other depths according to actual product requirements.
In one embodiment, the isolation structure layer 40 is already formed in the second trench, for example, so that the formation of the first dielectric layer does not affect the second trench. The first dielectric layer functions as, for example, a gate oxide layer.
The material of the first dielectric layer and the isolation structure layer 40 may be at least one of silicon oxide, silicon nitride and silicon oxynitride.
After the first dielectric layer and/or the isolation structure layer 40 is formed, a planarization process, for example, a chemical mechanical polishing process, may be performed to make the upper surface of the first dielectric layer and/or the isolation structure layer 40 flush with the first surface 101.
It is understood that the first dielectric layer and the isolation structure layer 40 may have any preparation order.
Thereafter, a semiconductor layer 20 is formed on the first dielectric layer in the first trench, a top surface of the semiconductor layer 20 being lower than the first surface. The semiconductor layer 20 is made of, for example, a metal material, but other materials such as polysilicon may be selected, and a metal material may be preferable in terms of contributing to obtaining a better thermal stability and a suitable work function when used as a gate electrode. Further, the metal material is not limited to a metal simple substance, and may be a binary alloy of metals, a conductive metal oxide, a metal silicide, a metal nitride, a metal silicide nitride, a metal aluminum nitride, or the like.
Thereafter, a second dielectric layer is filled in the first trench, the second dielectric layer being located on the top surface of the semiconductor layer 20, the second dielectric layer covering the semiconductor layer 20 and connecting the first dielectric layer, whereby the first and second dielectric layers serve as dielectric layers 30 for the word line 50 (or gate structure).
The second dielectric layer may be formed by a chemical vapor deposition process, for example, the second dielectric layer may be one or a combination of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.
The word lines 50 intersect the corresponding active regions so as to be in contact with the gate structures formed in the active regions. In this embodiment, the word lines 50 extend along a first direction, and therefore, the gate structures aligned in the first direction are all connected to the same word line 50. The word line 50 may be a buried word line, i.e., the word line 50 is formed in the substrate 10. In this embodiment, the gate structure formed in the active region also forms a part of the word line 50, and the isolation structure layer 40 corresponding to the position of the word line 50 also forms a word line material, and the word line material in the isolation structure 40 is connected to the gate structure, so as to form the word line 50 together. Specifically, the word line 50 includes the semiconductor layer 20 and the dielectric layer 30, the semiconductor layer 20 in the active region forms a gate structure and is connected to the semiconductor layer 20 in the isolation structure layer 40, and the dielectric layer 30 covers the semiconductor layer 20 to prevent the semiconductor layer 20 from being electrically connected to other conductive lines.
Referring to fig. 6, fig. 6 is a schematic diagram illustrating a first ion implantation performed in a method for forming a memory according to an embodiment of the invention. For step S14, a first ion implantation is performed on the substrate 10 on both sides of the word line and near the first surface.
In one embodiment, the first ion implantationThe implant may be an N-type implant, for example, phosphorus may be implanted at a dose of 1E14/cm2～1E16/cm2The implantation energy may be 10KeV to 50 KeV.
After the first ion implantation, a first ion implantation layer 81 is formed on the substrate 10 near the first surface.
Next, referring to fig. 7, fig. 7 is a schematic diagram illustrating a barrier layer and an opening formed in a method for forming a memory according to an embodiment of the invention. For step S15, a barrier layer 60 is formed on the substrate 10 and an opening 61 is formed, wherein the opening 61 exposes at least a partial region between two adjacent word lines of each group of word lines.
In one embodiment, the barrier layer 60 may be made of photoresist, for example, and it is understood that the barrier layer 60 may be made of other materials, such as silicon nitride, etc.
For the example of the barrier layer 60 being a photoresist, the opening 61 can be realized by a photolithography process, for example.
In one embodiment, opening 61 may be, for example, an opening for forming a subsequent bitline.
It will be appreciated that the opening 61 may restrict the tilt angle for subsequent ion implantation, and therefore the actual size of the opening 61 and the depth of the barrier layer 60 may be adapted to the actual process requirements.
Referring to fig. 8-10, fig. 8-9 are schematic diagrams illustrating a second ion implantation process performed in a method for forming a memory according to an embodiment of the invention; FIG. 10 is a diagram of a memory formed in accordance with an embodiment of the present invention. For step S16, performing a second ion implantation 70 with inclination to the substrate from the opening, and forming doped layers after performing at least the first ion implantation and the second ion implantation, wherein the doped layers are respectively arranged on two sides of each word line, the depth of the doped layers between two adjacent word lines of each group of word lines is greater than the depth of the doped layers on the opposite sides of the two adjacent word lines, and the depth of the doped layers on the opposite sides of the two adjacent word lines becomes smaller as the two adjacent word lines are farther away.
Specifically, as shown in fig. 8, the second ion implantation 70 is an N-type implantation, for example, phosphorus may be implanted, and the implantation dose may be 1E12/cm2～1E13/cm2The implantation energy may be 30KeV to 60KeV, the implantation angle may be 3 to 20 °, and the implantation angle is an angle between the implantation direction and a normal to the first surface of the substrate.
After the second ion implantation, as shown in fig. 9, a second ion implantation layer 82 is formed, and the second ion implantation layer 82 is mainly concentrated in the substrate 10 below the opening, including between two adjacent word lines and in a small partial area of the side where the two adjacent word lines depart from each other.
After the second ion implantation 70 is performed from the opening, the method further includes: performing a heat treatment to form the doped layer. That is, after the second ion implantation layer 82 is formed, the dopant ions are activated by a heat treatment to obtain a desired doped layer.
In one embodiment, the heat treatment comprises a spike (rapid) anneal, which may be performed at 900 ℃ to 1000 ℃, for example, in a nitrogen atmosphere.
Performing a heat treatment may also effect lattice damage.
Referring to fig. 10, the doped layer includes a first portion 91, a second portion 92 and a third portion 93, a depth of the first portion 91 is greater than a depth of the second portion 92, a depth of the second portion 92 is greater than a depth of the third portion 93, the first portion 91 is located between two adjacent word lines, the second portion 92 is located on an opposite side of the two adjacent word lines, and the third portion 93 is located on a side of the second portion 92 away from the word lines. The first ion implantation layer 81, for example, where adjacent isolation structure layers 40 are facing away as shown in fig. 10, may become a third portion at another word line after annealing.
In one embodiment, the depth H1 of the first portion 91 may be 50nm to 70nm, the depth H2 of the second portion 92 may be 40nm to 60nm, the depth H3 of the third portion 93 may be 30nm to 50nm, and the width W of the second portion 92 may be 4nm to 8 nm.
After the formation of the doped layer, the doped layer includes a source region S and a drain region D of the present invention, which are formed in the substrate 10, the source region S and the drain region D are respectively located at two sides of the word line, for example, the drain region D includes the second portion 92 and the third portion 93, a depth position of a bottom end of the drain region D in the substrate 10 with respect to the first surface is higher than a depth position of the top surface of the semiconductor layer 20 in the substrate 10 with respect to the first surface, the source region S includes the first portion, and a depth position of a bottom end of the source region S in the substrate 10 with respect to the first surface is lower than a depth position of the top surface of the semiconductor layer 20 in the substrate 10 with respect to the first surface.
It can be seen that the depth distribution of the doped layer is not uniform, and in an embodiment of the present invention, the depth decreases from between two adjacent word lines to a direction away from the two adjacent word lines. Therefore, the leakage current is reduced, and meanwhile, the starting current is improved, so that the performance of the memory is improved.
In one embodiment, the source region S or the drain region D between adjacent word lines is common, and the source region S is common as shown in fig. 10.
Thereafter, other operations of the memory may proceed, such as completing fabrication of the bit lines.
To this end, the present invention obtains a memory, and with continued reference to fig. 3 to fig. 10, it can be seen that the memory of the present invention includes:
a substrate 10, the substrate 10 having a first surface 101 and a second surface 102 oppositely disposed;
at least one group of word lines 50 formed inside the substrate 10, each group of word lines 50 including two adjacent word lines 50;
the doped layers extend from the first surface 101 of the substrate 10 to the inside of the substrate 10 and are respectively arranged at two sides of the word lines 50, the depth of the doped layers between two adjacent word lines 50 of each group of word lines 50 is greater than the depth of the doped layers at the side where the two adjacent word lines 50 depart from, and the depth of the doped layers at the side where the two adjacent word lines 50 depart from becomes smaller as the two adjacent word lines 50 depart from.
In one embodiment, the doped layer includes a first portion 91, a second portion 92 and a third portion 93, the depth of the first portion 91 is greater than that of the second portion 92, the depth of the second portion 92 is greater than that of the third portion 93, the first portion 91 is located between two adjacent word lines, the second portion 92 is located on an opposite side of the two adjacent word lines, and the third portion 93 is located on a side of the second portion 92 away from the word lines. The first ion implantation layer 81, for example, where adjacent isolation structure layers 40 are deviated as shown in fig. 10, may become a third portion at another word line.
In one embodiment, the depth H1 of the first portion 91 may be 50nm to 70nm, the depth H2 of the second portion 92 may be 40nm to 60nm, the depth H3 of the third portion 93 may be 30nm to 50nm, and the width W of the second portion 92 may be 4nm to 8 nm.
A source region S and a drain region D are formed in the substrate 10, the source region S and the drain region D are respectively located at two sides of the word line, for example, the drain region D includes the second portion 92 and the third portion 93, a depth position of a bottom end of the drain region D in the substrate 10 with respect to the first surface is higher than a depth position of the top surface of the semiconductor layer 20 in the substrate 10 with respect to the first surface, the source region S includes the first portion 91, a depth position of a bottom end of the source region S in the substrate 10 with respect to the first surface is lower than a depth position of the top surface of the semiconductor layer 20 in the substrate 10 with respect to the first surface.
In one embodiment, the doping type of the doped layer is N-type. For example, phosphorus doping may be used. The doping concentration of the doping layer is 1E12/cm2～1E16/cm2。
In one embodiment, the source region S or the drain region D between adjacent word lines is common, and the source region S is common as shown in fig. 10.
The word line 50 includes a first dielectric layer formed on a trench wall surface of a trench in a substrate, a semiconductor layer formed on the first dielectric layer in the trench, a top surface of the semiconductor layer lower than the first surface, and a second dielectric layer on the top surface of the semiconductor layer, the second dielectric layer covering the semiconductor layer and connecting to the first dielectric layer.
For example, the word line 50 is a buried word line, i.e., a first dielectric layer formed in the substrate 10, formed on a sidewall of a first trench, and a semiconductor layer 20 formed on the first dielectric layer in the first trench, wherein a top surface of the semiconductor layer 20 is lower than the first surface. The semiconductor layer 20 is made of, for example, a metal material, but other materials such as polysilicon may be selected, and a metal material may be preferable in terms of contributing to obtaining a better thermal stability and a suitable work function when used as a gate electrode. Further, the metal material is not limited to a metal simple substance, and may be a binary alloy of metals, a conductive metal oxide, a metal silicide, a metal nitride, a metal silicide nitride, a metal aluminum nitride, or the like.
A second dielectric layer formed in the first trench on the semiconductor layer 20, the second dielectric layer being on the top surface of the semiconductor layer 20, the second dielectric layer covering the semiconductor layer 20 and connecting the first dielectric layer, whereby the first and second dielectric layers act as dielectric layers 30 for a word line 50 (or gate structure).
For example, the second dielectric layer may be one or a combination of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.
The word lines 50 intersect the corresponding active regions so as to be in contact with the gate structures formed in the active regions. In this embodiment, the word lines 50 extend along a first direction, and therefore, the gate structures aligned in the first direction are all connected to the same word line 50. The word line 50 may be a buried word line, i.e., the word line 50 is formed in the substrate 10. In this embodiment, the gate structure formed in the active region also forms a part of the word line 50, and the isolation structure layer 40 corresponding to the position of the word line 50 also forms a word line material, and the word line material in the isolation structure 40 is connected to the gate structure, so as to form the word line 50 together. Specifically, the word line 50 includes the semiconductor layer 20 and the dielectric layer 30, the semiconductor layer 20 in the active region forms a gate structure and is connected to the semiconductor layer 20 in the isolation structure layer 40, and the dielectric layer 30 covers the semiconductor layer 20 to prevent the semiconductor layer 20 from being electrically connected to other conductive lines.
In one embodiment, the substrate 10 is further formed with an isolation structure layer 40, wherein the isolation structure layer 40 surrounds the source region S and the drain region D.
In summary, in the memory and the forming method thereof provided by the present invention, at least one group of word lines is formed in the substrate, the doped layers are respectively arranged at two sides of the word lines, the depth of the doped layer between two adjacent word lines of each group of word lines is greater than the depth of the doped layer at the deviating side of the two adjacent word lines, and the depth of the doped layer at the deviating side of the two adjacent word lines is reduced as the doped layer is farther away from the two adjacent word lines. Therefore, the leakage current is reduced, and meanwhile, the starting current is improved, so that the performance of the memory is improved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (15)
1. A memory, comprising:
a substrate having a first surface and a second surface disposed opposite;
at least one group of word lines formed inside the substrate, each group of word lines including two adjacent word lines; and a process for the preparation of a coating,
the doped layers extend from the first surface of the substrate to the inside of the substrate and are respectively arranged on two sides of each word line, the depth of the doped layers between two adjacent word lines of each group of word lines is larger than that of the doped layers on the deviating sides of the two adjacent word lines, and the depth of the doped layers on the deviating sides of the two adjacent word lines is reduced along with the distance from the two adjacent word lines.
2. The memory of claim 1, wherein the doped layer includes a first portion, a second portion and a third portion, the first portion has a depth greater than a depth of the second portion, the second portion has a depth greater than a depth of the third portion, the first portion is located between the two adjacent word lines, the second portion is located on a side of the two adjacent word lines facing away from each other, and the third portion is located on a side of the second portion away from the word lines.
3. The memory of claim 2, wherein the first portion has a depth of 50nm to 70nm, the second portion has a depth of 40nm to 60nm, the third portion has a depth of 30nm to 50nm, and the second portion has a width of 4nm to 8 nm.
4. The memory of claim 1, wherein the doping type of the doped layer is N-type.
5. The memory of claim 1 wherein said doped layer has a doping concentration of 1E12/cm2～1E16/cm2。
6. The memory of claim 1, wherein the doped layers comprise source and drain regions, the source and drain regions are arranged on two sides of the word lines, and the source or drain region between two adjacent word lines is common.
7. The memory of claim 6, wherein the substrate is further formed with an isolation structure layer surrounding the source region and the drain region.
8. The memory of claim 1, wherein the word line comprises a first dielectric layer formed on a trench wall surface in a substrate, a semiconductor layer formed on the first dielectric layer in the trench, a top surface of the semiconductor layer lower than the first surface, and a second dielectric layer on the top surface of the semiconductor layer, the second dielectric layer covering the semiconductor layer and connecting the first dielectric layer.
9. A method for forming a memory, comprising:
providing a substrate, wherein the substrate is provided with a first surface and a second surface which are oppositely arranged;
forming at least one set of first trenches in the substrate, the first trenches having openings formed on the first surface, each set of first trenches including two adjacent first trenches;
forming at least one set of word lines in the at least one set of first trenches;
performing first ion implantation on the substrate on two sides of the word line and close to the first surface;
forming a barrier layer on the substrate and forming an opening, wherein the opening at least exposes a partial area between two adjacent word lines of each group of word lines; and
and performing second ion implantation on the substrate in an inclined manner from the opening, forming doped layers after performing at least the first ion implantation and the second ion implantation, wherein the doped layers are respectively arranged at two sides of each word line, the depth of the doped layers between two adjacent word lines of each group of word lines is greater than that of the doped layers at the deviating sides of the two adjacent word lines, and the depth of the doped layers at the deviating sides of the two adjacent word lines is reduced along with the distance from the two adjacent word lines.
10. The method of claim 9, wherein the first ion implantation is an N-type implantation with an implantation dose of 1E14/cm2～1E16/cm2The implantation energy is 10 KeV-50 KeV.
11. The method of claim 9, wherein the second ion implantation is an N-type implantation with a dose of 1E12/cm2～1E13/cm2The implantation energy is 30 KeV-60 KeV, and the implantation angle is 3-20 deg.
12. The method of claim 9, further comprising, after the second ion implantation from the opening: performing a heat treatment to form the doped layer.
13. The method of claim 12, wherein the heat treating comprises a spike anneal at a temperature of 900 ℃ to 1000 ℃ in a nitrogen atmosphere.
14. The method according to claim 9, wherein the doped layer includes a first portion, a second portion and a third portion, the depth of the first portion is greater than that of the second portion, the depth of the second portion is greater than that of the third portion, the first portion is located between the two adjacent word lines, the second portion is located on an opposite side of the two adjacent word lines, and the third portion is located on a side of the second portion, which is far away from the word lines.
15. The method of claim 14, wherein the first portion has a depth of 50nm to 70nm, the second portion has a depth of 40nm to 60nm, the third portion has a depth of 30nm to 50nm, and the second portion has a width of 4nm to 8 nm.
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